5

ZQK ULV SYSTEM BLOCK DIAGRAM

Memory Down x8pcs
128Mb X 16 * 4pcs = 1GB
256Mb X 16 * 4pcs = 2GB

Channel A
256Mb X 16 * 8pcs
D

Max. 4G P13,14
Channel B

DDRIII-SODIMM x1pc
P15

P21
D

N14P-GV2
X'TAL
27.0MHz

Display

P2,3,4,5,6

P16~P21

Dual Channel DDR III 1333/1600 MHZ

FDI

DDR3

GPU

PCI-E
X8

Ivy Bridge
BGA 1023
17W

IMC

VRAM Max. 2G

DMI

eDP

INT_eDP

4 Lane reserve

DMI(x4)

eDP Con.
Touch Panel (option)

USB2.0-(3)

P24

SATA 0

SATA - HDD

SATA

FDI

DMI

MINI CARD 2
mSATA SSD

SATA 1

Dongle SW
HD3SS2521RHUR

USB3.0-(3)

SATA

USB3.0-(1)

Display

INT_HDMI

HDMI Con.

P25

USB2.0-(1)

USB2.0 Port

P31

Panther Point

USB2.0-(4)

USB2.0 Port

USB2.0-(8)

CCD(Camera)

USB2.0

PCIE-8

PCI-E x1

USB2.0

MINI CARD1
WLAN+BT

USB2.0-(10)

PCH
BGA 989

P31

I/O board

P23

USB3.0

USB2.0-(0)

P31

Mini DP Con.

P23

P26

USB3.0/2.0 Port
(Charger)
C

INT_DP

Display

P27

P26

RTL8411AAR
Giga LAN

PCIE-3

PCI-E x1

P7, 8, 9, 10, 11, 12

P24

W/Card Reader
X'TAL
32.768KHz

RJ45 CONN
P28
P28

Card Reader CONN

P29

X'TAL
25MHz

P8

Azalia

BATTERY

RTC
IHDA

SPI

SPI ROM*2
2M+4M(EC) P8

LPC
B

ALC3225
AUDIO CODEC

EC ITE 8587

P30

TPM
P27

P34

Int. DMIC
P30

Combo Jack
P30

ALC1001
AMP P30

K/B Conn

BQ24737RGRR

Touch Pad
Con. P30

P30

Batery Charger

TPS51216RUKR
P35

+1.5V_SUS

Discharger
Thermal Protection

P37

P41

TPL@

Touch panel

TPM@

TPM module

NP@

Normal panel(Default)

CH@

Charge function(Default)

NCH@

No Charge function

EV@

Optimize SKU

RAMID@

RAMID strap pin

SUG@

LAN Surge

NSW@

w/o Dongle switch

SW@

w Dongle switch

KBL@

KB Backlight LED

RD@

mSATA Re-driver
5

HALL SENSOR

Speaker

TPS51463

3V/5V

VCCSA

P36

P39

Fan*2 (PWM Type)

P32

AH9249NTR-G1

P30

TPS51225RUKR

TPS51650RSLR

uP1642PQAG

+VCC_CORE/+VCC_GFX P40

P24

TPS51219RTER

+VGPU_CORE

P43

TPS51211DSCR

+1.05V_VTT

+1.5V_GFX/1.05V_GFX/3V_GFX

P38

P42

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

Block Diagram
4

Sheet
1

of

46

02

Ivy Bridge Processor (DMI,PEG,FDI) (CPU)

U47A

M2
P6
P1
P10

[7]
[7]
[7]
[7]

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

N3
P7
P3
P11

[7]
[7]
[7]
[7]

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

K1
M8
N4
R2

[7]
[7]
[7]
[7]

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

K3
M7
P4
T3

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

U6
W 10
W3
AA7
W7
T4
AA3
AC8

[7] FDI_FSYNC0
[7] FDI_FSYNC1

AA11
AC12

[7] FDI_INT

U11

[7] FDI_LSYNC0
[7] FDI_LSYNC1

AA10
AG8

eDP_ICOMPO 12mil
eDP_COMPIO 4mil

AF3
AD2
AG11

EDP_AUXN
EDP_AUXP

AG4
AF4

EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3

AC3
AC4
AE11
AE7

EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3

AC1
AA4
AE10
AE6

[24] EDP_AUXN
[24] EDP_AUXP

[24]
[24]
[24]
[24]

EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3

[24]
[24]
[24]
[24]

EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD
eDP_AUX#
eDP_AUX

DP

EDP_COMP
INT_EDP_HPD#

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

Intel(R) FDI

[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]

U7
W 11
W1
AA6
W6
V4
Y2
AC9

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

PCI EXPRESS -- GRAPHICS

[7]
[7]
[7]
[7]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

G3
G1
G4

PEG_COMP

PEG_ICOMPO 12mil
PEG_ICOMPI, PEG_RCOMPO 4mil,

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PEG_RX#15 [16]
PEG_RX#14 [16]
PEG_RX#13 [16]
PEG_RX#12 [16]
PEG_RX#11 [16]
PEG_RX#10 [16]
PEG_RX#9 [16]
PEG_RX#8 [16]

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

PEG_RX15 [16]
PEG_RX14 [16]
PEG_RX13 [16]
PEG_RX12 [16]
PEG_RX11 [16]
PEG_RX10 [16]
PEG_RX9 [16]
PEG_RX8 [16]

PEG_ICOMPI and RCOMPO signals

should be shorted and routed with
- max length = 500 mils
- typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with
- max length = 500 mils
- typical impedance = 14.5 mohms

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

PEG_TX#15 [16]
PEG_TX#14 [16]
PEG_TX#13 [16]
PEG_TX#12 [16]
PEG_TX#11 [16]
PEG_TX#10 [16]
PEG_TX#9 [16]
PEG_TX#8 [16]

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_TX15 [16]
PEG_TX14 [16]
PEG_TX13 [16]
PEG_TX12 [16]
PEG_TX11 [16]
PEG_TX10 [16]
PEG_TX9 [16]
PEG_TX8 [16]

0.22uF AC coupling Caps for PCIE GEN1/2/3

Ivy Bridge

DP_COMPIO and ICOMPO signals

should be shorted near balls and routed with
- typical impedance < 25 mohms

DP & PEG Compensation

CAD Note: Place PU resistor
within 2 inches of CPU

DG 1.0 :
The recommended AC cap value is changed to 220nF for compatibility with
PCIe Gen3 on future platforms.
For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.

eDP Hot-plug (Disable)

+1.05V_VTT

HPD PU/PD resistor values based

on CRB and different to DG

R327
1K/J_4

+1.05V_VTT
INT_EDP_HPD#

EDP_COMP

R669

24.9/F_4

Quanta Computer Inc.

R310

1
PEG_COMP

R675

EDP_HPD [24]

Q23
2N7002K

+1.05V_VTT

24.9/F_4

PROJECT : ZQK

100K/J_4

Size

Document Number

Rev
1A

Ivy Bridge 1/5 (HOST & PCIE)

Date:
5

Monday, January 07, 2013

Sheet
1

of

46

Boot

S3

S3 RSM

03

+1.5V_CPU
DRAM_PWRGD

Ivy Bridge Processor (CLK,MISC,JTAG) (CPU)

U47B

SM_DRAMPWROK

C49

C770 2

56/J_4 H_PROCHOT#_R

THERMAL

R715

[34,35,40] H_PROCHOT#

PECI

C45

PROCHOT#

1 *43P/50V_4
D45

[10] PM_THRMTRIP#

BCLK_ITP
BCLK_ITP#

SM_DRAMRST#

THERMTRIP#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

Over 130 degree C will drive low

PRDY#
PREQ#

R717

Isolate Space:20mils
+1.05V_VTT

R735

PM_SYNC

39P/50V_4
H_PWRGOOD_R

0/J_4

B46

UNCOREPW RGOOD

10K/J_4

BE45

PM_DRAM_PWRGD_R

SM_DRAMPW ROK

75/F_4
CPU_PLTRST#

R740

43/J_4

CPU_PLTRST#_R

R736
*750/F_4

D44

RESET#

C841

TCK
TMS
TRST#

JTAG & BPM

C774
R719

[10] H_PWRGOOD

C48

PM_SYNC_R

0/J_4

PWR MANAGEMENT

R720

CLK_CPU_BCLKP [9]
CLK_CPU_BCLKN [9]

AG3 CLK_DPLL_SSCLKP_R
AG1 CLK_DPLL_SSCLKN_R

R677
R676

N59 CLK_PCIE_XDPP_R
N58 CLK_PCIE_XDPN_R

0/J_4
0/J_4

R750
R749

If motherboard only supports external graphics or if it supports

Processor Graphics but without eDP:
Connect DPLL_REF_SSCLK on Processor to GND through 1K +/5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistor

CLK_DPLL_SSCLKP [9]
CLK_DPLL_SSCLKN [9]

*0/J_4
*0/J_4

CLK_PCIE_XDPP [9]
CLK_PCIE_XDPN [9]

Momory Down Layout notes

Isolate Space:20mils

AT30

CAD NOTE: All DDR_COMP signals

should be routed such that :- max length = 500 mils
- trace width = 15mils and
- MB trace impedance < 68 mohms
(worst case resistance)

CPU_DRAMRST# [4]

BF44
BE43
BG43

SM_RCOMP_0 R707
SM_RCOMP_1 R702
SM_RCOMP_2 R705

140/F_4
25.5/F_4
200/F_4

SM_RCOMP Impedance 85ohm

[7] PM_SYNC

J3
H2

CATERR#

A48

[10,34] EC_PECI

DPLL_REF_CLK
DPLL_REF_CLK#

DDR3
MISC

TP_CATERR#

TP54

PROC_DETECT#

BCLK
BCLK#

CLOCKS

PROC_SELECT#

C57

TP46

MISC

F49

[8] H_SNB_IVB#

100 ns after +1.5V_CPU

reaches 80%

SYS_PWROK

TDI
TDO

DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

N53
N55

XDP_PRDY#
XDP_PREQ#

L56
L55
J58

XDP_TRST#

M60
L59

K58

XDP_TDI_VT

XDP_DBRST#_R R745

G58
E55
E59
G55
G59
H60
J59
J61

0/J_4

TP50
TP42

Layout Notes: Place near to XDP connector

05/15PCH_XDP_TDO_VT already pull high
+3V_S5 on PCH side

XDP_TCLK_VT [8]
XDP_TMS_VT [8]
TP73

R754

+1.05V_VTT

51/J_4

PCH_XDP_TDO_VT

TP76
PCH_XDP_TDO_VT [8]

Option for Prochot# function

68 ohm for unused, 62 ohm for used

XDP_DBRST# [7]

TP44
TP49
TP47
TP43
TP74
TP77
TP78
TP75

39P/50V_4

H_PROCHOT#

R722

62/J_4

XDP_TMS_VT
XDP_TDI_VT

R379
R755

51/J_4
51/J_4

XDP_PREQ#

R378

*51/J_4

XDP_TCLK_VT
XDP_TRST#

Ivy Bridge

R746
R744

+1.05V_VTT

51/J_4
51/J_4

When MP, JTAG PU/PD resistor can be

removed? (Yes Intel, TDI, TDO, TMS, TRST#,
TCK,PREQ#, PRDY#)

+3V

Thermal Trip (CPU)

S3 leakage circuit (CPU)

If PM_DRAM_PWEGD connector,the R5180 must stuff.
+3V_S5

+3V_S5

[9,34] PCI_PLTRST#

20111121 add Q31 becaue Vh=2.1/Vl=0.9.

+1.05V_VTT

3
+1.5V_CPU

2N7002K

3
1

130/F_4

[27,36,41]

74AHC1G09
R387

*39/J_4 3
Q33

[7] PM_DRAM_PWRGD

R384

*2N7002K

CPU_PLTRST#

*1.5K/F_4

CPU_PLTRST#_R

OUT

High-Z

Quanta Computer Inc.

PROJECT : ZQK
Size

R385
3

Document Number

Rev
1A

Ivy Bridge 2/5 (CLK & JTAG)

*0/J_4
Date:

0/J_4

20111030 add resistor.

5

GND OUT

PM_DRAM_PWRGD_R

[5,41] MAINON_G
SYS_SHDN#

IN

IN
R395

*2N7002DW
Q31

2
PM_THRMTRIP#

Q66
3 MMBT3904-7-F_200MA

PM_DRAM_PWRGD_Q

5
R734
1K/J_4

R396
200/F_4

U24

[7] SYS_PWROK

R747

+1.5V_CPU

Q67

C446
0.1u/10V_4

[7,40] IMVP_PWRGD

R367
*10K/J_4

NC VCC

74LVC1G07GW_NC

R368
*1K/J_4

C453
0.1u/10V_4

U50

20111128 change net to PCI_PLTRST#

Monday, January 07, 2013

Sheet
1

of

46

04

Ivy Bridge Processor (CPU)

Channel B: SO-DIMM

Channel A: On board RAM 2Rx16 8pcs

U47C

U47D
[15] M_B_DQ[63:0]

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

BD37
BF36
BA28

[13,14] M_A_BS#0
[13,14] M_A_BS#1
[13,14] M_A_BS#2
B

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

BE39
BD39
AT41

[13,14] M_A_CAS#
[13,14] M_A_RAS#
[13,14] M_A_WE#

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

SA_CAS#
SA_RAS#
SA_WE#

AU36
AV36
AY26

AT40
AU40
BB26

M_A_CLK1 [14]
M_A_CLK1# [14]
M_A_CKE1 [14]

BB40
BC41

M_A_CS#0 [13]
M_A_CS#1 [14]

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_A_CLK0 [13]
M_A_CLK0# [13]
M_A_CKE0 [13]

M_A_ODT0 [13]
M_A_ODT1 [14]

M_A_DQSN[7:0] [13,14]

M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQSP[7:0] [13,14]

M_A_A[15:0] [13,14]

[15] M_B_BS#0
[15] M_B_BS#1
[15] M_B_BS#2

[15] M_B_CAS#
[15] M_B_RAS#
[15] M_B_WE#

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

BG39
BD42
AT22

AV43
BF40
BD45

Ivy Bridge

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

BA34
AY34
AR22

M_B_CLK0 [15]
M_B_CLK0# [15]
M_B_CKE0 [15]
D

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

DDR SYSTEM MEMORY B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

DDR SYSTEM MEMORY A

[13,14] M_A_DQ[63:0]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_CAS#
SB_RAS#
SB_WE#

M_B_CLK1 [15]
M_B_CLK1# [15]
M_B_CKE1 [15]

BE41
BE47

M_B_CS#0 [15]
M_B_CS#1 [15]

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

M_B_ODT0 [15]
M_B_ODT1 [15]

M_B_DQSN[7:0] [15]

M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]

BA36
BB36
BF27

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQSP[7:0] [15]

M_B_A[15:0] [15]

Ivy Bridge

+0.75V_DDR_VTT

+1.5VSUS

S3 circuit: DRAM_RST# to memory should be high

during S3

[13,14,15] DDR3_DRAMRST#

R681

1K/F_4

[9] DRAMRST_CNTRL_PCH

R682

*0/J_4

R683

0/J_4

[34]

EC_DRAMRST_CNTRL

+3V_S5

20120914 Follow Z09 design to move R682 close to Q62

R684

R680
1K/F_4

*0/J_4

R686
1K/J_4
Q62
3

2N7002K
1

CPU_DRAMRST#

S3 leakage circuit (CPU)

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

C678
0.047u/10V_4

R693
4.99K/F_4

[3]

R263
R617
R603
R262
R636
R293
R304
R650
R297
R619
R239
R282
R602
R640
R287
R601

36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4
36/J_4

M_A_CS#0 R238
M_A_CS#1 R259

36/J_4
36/J_4

M_A_CKE0 R237
M_A_CKE1 R260

36/J_4
36/J_4

M_A_ODT0 R257
M_A_ODT1 R256

36/J_4
36/J_4

M_A_WE# R240
M_A_CAS# R258
M_A_RAS# R236

36/J_4
36/J_4
36/J_4

M_A_BS#0 R600
M_A_BS#1 R264
M_A_BS#2 R261

36/J_4
36/J_4
36/J_4

C240
1u/6.3V_4

C239
1u/6.3V_4

C238
1u/6.3V_4

C237
1u/6.3V_4

C236
1u/6.3V_4

C241
C279
1u/6.3V_4 10u/6.3V_6

20120112 for memory down PU CAP.

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

Ivy Bridge 3/5 (DDR3 I/F)

[13,14,15] DEEPS3_EC

20120204 Change to EC for new BIOS 0.6

5

Date:
4

Monday, January 07, 2013

Sheet
1

of

46

SNB : Spec

U47F
+1.05V_VTT

C755

C759

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C753

C754

C760

C758

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

20120120 remove C622 for debug IC.

C698

C705

10u/6.3V_6

10u/6.3V_6

C355

C354

C344

C743

2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4

C

C374

C356

C365

C699

C367

C744

C377

2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4

C338

C345

C368

C346

C730

C700

C697

2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4

C731

C376

C366

C696

C748

2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4

C337

C363

C393

C391

C392

C369

C375

2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4 2.2u/10V_4

CPU Core Power

470u/2V_7343

C463
C654

C652

C372

C342

C468
C660

C445

C462

C455

C458

C648

C645

C353

C349

C467

C449

C444

C454

C450

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

C447

1u/6.3V_4
C401

C347

C328

C348

C297

C299

C409

C408

C664

C323

C295

C435

1u/6.3V_4

C451

1u/6.3V_4

C443

1u/6.3V_4

1u/6.3V_4

C332

VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

C394

C325

C331

C339

C400

C296

C298

C395

C321

C370

C326

C350

C402

C405

C406

C399

C410

C403

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C324

1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4

IVY SPEC
22uF_8 x7 Socket TOP cavity
22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2

VCCAXG_SENSE/VSSAXG_SENSE R=100,
Trace impedance 15.5~34.5, <25mils.
W16
W17

R328

0/J_6

BC22

VCCIO_SEL

TP70

IVY 17W:1.5A

Spec

On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V

A44
B43
C44

R344

0/J_4

C340

1u/6.3V_4

F45
G45
100/J_4

Real

330uF/7mohm x 1 10uF x 1

+1.8V

R667

CPU_VCCPLL
C668
1u/6.3V_4

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

C669
1u/6.3V_4

BB3
BC1
BC4
+ C662
*330u/2.5V_3528

C670

+ C656
C666
C657
C672
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
330u/2V_7343
10u/6.3V_6 10u/6.3V_6

IVY SPEC
330uF x1, 10uF_8 x1 Socket BOT edge,
10uF_8 x2 Socket BOT cavity.

IVY 17W: 6A
SENSE LINES

Spec

VCCIO_SENSE
VSS_SENSE_VCCIO

+1.05V_VTT

+VCC_GFX

+VCCSA

+1.5V_CPU

R357

100/F_4 +VCC_CORE

R354

100/F_4

R325

10/J_4

R326

10/J_4

F43
G43

AN16
AN17

330uF/7mohm x 1 Real
10uF x 5
1uF x 5
10uF x 3

VCC_SENSE [40]
VSS_SENSE [40]

C334

C320

C327

C322

C335

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

+1.05V_VTT

STUFF

VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]

C845

C846

C847

39P/50V_4

39P/50V_4

39P/50V_4

39P/50V_4

39P/50V_4

39P/50V_4

disable
+SMDDR_VREF

NO_STUFF

4.5A

1uF x 10

C333
C380
C396
C441
C387
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

C775
+

C440
C414
C411
10u/6.3V_6 *10u/6.3V_6 *10u/6.3V_6

330u/2V_7343

C397

C437

C361

C362

C379

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C439

C329

C389

C360

C438

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

VDDQ_SENSE
VSS_SENSE_VDDQ

AM28
AN26

+1.5V_CPU
C378

BC43
BA43

1u/6.3V_4

R373
R372

*51/J_4
*51/J_4

+1.5V_CPU

R674

VCCSA_SENSE

*100/F_4

U10

+VCCSA
VCCSA_SENSE

SNB_IVB# N.A at SNB EDS #27637 0.7v1

D48
D49

R723

*10K/J_4

C777
R728

*33n/10V_4
0/J_4

R374

*10K/J_4

VCCSA_VID0
VCCSA_VID1

*0_1206 +1.5V_CPU

R362

Q64

*0_1206
AO4496

8
7
6
5

0.9V

0.8V

0.725V

0.675V

1
2
3

For SN Bridge

R738

VID[1]

*0/J_8

0/J_4

R709
130/F_4
[40]

H_CPU_SVIDDAT

R712

R711
75/F_4

SVID DATA
0/J_4

VR_SVID_DATA

H_CPU_SVIDALRT#

[40]

R714

43/J_4

VR_SVID_ALERT#_R

MAIND

Q65
2N7002K
R751
100K/J_4

0.9V

0.8V

R748
*1K/F_4

S3 circuit: 1.5V input to IVB is gated &

IVB Read Vref 0.75V is gated

SVID ALERT
R713

0/J_4

VR_SVID_ALERT#

R377
220/J_8

C779
470P/50V_4

[3,41] MAINON_G

MAINON_G

Quanta Computer Inc.

2
Q32
2N7002K

change to 1K/F_4

[40]

VR_SVID_CLK

+1.05V_VTT
[36,37,41] MAIND

SVID CLK

+VCCSA

0
MAIND

Place PU resistor close to CPU

+1.05V_VTT

+VCCSA

Place PU resistor close to CPU

VID[1]

*1K/F_4

Layout note: need routing

together and ALERT need
between CLK and DATA

[39]
[39]

For IV Bridge

R365

+1.5V_CPU

[39]

201201117 C767 for Intel fw issue,

if solve need un-stuff.

20111107 stuff Q5010 and un-stuff R5347/R362.

R5347/R6362

+VDDR_REF_CPU

R739

R710

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

R5347/R6362

20111024 from +1.5VSUS change to +1.5V_CPU

H_CPU_SVIDCLK

VCCDQ[1]
VCCDQ[2]

VCCSA_VID[0]
VCCSA_VID[1]

+1.5VSUS

enable
C844

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

VID[0]

S3
Ivy Bridge

C843

10uF x 8

Ivy Bridge

VCCP_SENSE [38]
VSSP_SENSE [38]

+1.8V

C842

+VDDR_REF_CPU

VCCPLL[1]
VCCPLL[2]
VCCPLL[3]

+VCCSA

C658

IVY SPEC
1.9m/LoadlineDesign
total : 2.2uF x 35
total : 10uF x 12
tatal : 470u x1(Power side*1)

20121203
Add 39pF for ESD

Spec
330uF/6mohm x 1

AY43

+1.5V_CPU

VAXG_SENSE
VSSAXG_SENSE

0/J_8

1uF x 2

IVY SPEC
330uF x1, 10uF_8 x1, 1uF_4 x2
Socket BOT edge.

CPU VCCSA

VCC_SENSE
VSS_SENSE

SM_VREF

100/J_4

R388

TP57

+1.05V_VTT

AM25
AN22

R386

+VCC_GFX
[40] VCC_AXG_SENSE
[40] VSS_AXG_SENSE

CPU VCCPL

1uF x 2

VIDALERT#
VIDSCLK
VIDSOUT

IVY 45W: 5A

CAD Note: +VDDR_REF_CPU should

have 10 mil trace width

TP56

Voltage selection for VCCIO:

this pin must be pulled high
on the motherboard

VCCPQE[1]
VCCPQE[2]

VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]

+1.05V_VTT

Cose down

+VCC_CORE

C457

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4

VCCIO50
VCCIO51

SVID

470u/2V_7343

470u/2V_7343

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

SA RAIL

C738
+

+ C641
330u/2V_7343

C655

CPU VDDQ

+VCC_GFX

C792
+

C407

VCCIO_SEL

IVY 17W:TDC 33A

C737
+

1uF x 26

C404

IVY SPEC
1.9m/LoadlineDesign
total : 2.2uF x 35
total : 22uF x 12
tatal : 470u x3(Power side*1)

10uF x 10

1uF x 26

U47G

3.9m/LoadlineDesign
total : 1uF x 11
total : 10uF x 12
tatal : 470u x 1(power side*2)

1.8V RAIL

C701

10uF x 10

Cose down

Spec
3.9m/LoadlineDesign
total : 1uF x 11
total : 10uF x 6
total : 22uF x 6
tatal : 470u x 1(power side*2)

SENSE
LINES

C695

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

330uF/6mohm x 1

05

IVY Bridge Processor (GRAPHIC POWER) (CPU)

IVY 17W:TDC 18A

Cose down

330uF/6mohm x 2

GRAPHICS

C336

C756

10u/6.3V_6

CORE SUPPLY

C364

C706

PEG AND DDR

C757

POWER

VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

QUIET RAILS

20120120 remove C621 for debug IC.

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

QUIET RAILS

VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

+VCC_CORE

CPU VCCAXG

- 1.5V RAILS

IVY 17W:8.5A

DDR3

CPU VCCIO

POWER

IVY Bridge Processor (POWER) (CPU)

SENSE LINES

PROJECT :ZQK
Size

Document Number

Rev
1A

Ivy Bridge 4/5 (POWER)

Date:
5

Monday, January 07, 2013

1

Sheet

of

46

IVY Bridge Processor (GND) (CPU)

U47H

06

IVY Bridge Processor (RESERVED, CFG) (CPU)

BE7 SA_DIMM_VREFDQ
BG7 SB_DIMM_VREFDQ

U47I
U47E

R678

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G48
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

R375
*0/J_4

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]

VSS

VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

G48no stuff for IVY

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59

TP72
TP79

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

TP45
TP71

H43
K43

TP53
TP48

H45
K45

TP51

F48

TP52
TP55

H48
K48
BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

N42
L42
L45
L47

M13
M14
U14
W14
P13

for M3 solution
need R5265/R5266,
W/O M3 then NC

AT49
K24
AH2
AG13
AM14
AM15
N50

VCC_DIE_SENSE
RSVD6
RSVD7
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

1
0

CFG6
CFG5

R753

*1K/F_4

R752

1K/F_4

CFG[6:5] (PCIE Port Bifurcation Straps)

0
0
0
1

The CFG signals have a default value of '1' if not terminated on the board.

Normal Operation

0
Lane Reversed

Normal Operation

Lane Reversed

Disable; No physical DP attached to eDP

Enable; An ext DP device is connected to eDP

PEG train immediately following

xxRESETB de assertion

PEG wait for BIOS training

N14P-GV2

CFG2

R743

1K/F_4

CFG3

R742

1K/F_4

CFG4

R741

1K/F_4

CFG7

R376

*1K/F_4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

Ivy Bridge 5/5 (GND)

Date:

[13,14]
[15]

*1K/J_4

processor signal balls BF3 and BG4 for

Ivy Bridge 4-core and balls BE7
and BG7 for Ivy Bridge 2-core

Ivy Bridge

CFG7
(PEG Defer Training)

*1K/J_4
SMDDR_VREF_DQ0_M3
SMDDR_VREF_DQ1_M3

Ivy Bridge

CFG4
(DP Presence Strap)

BE7
BG7
R679

11: 1x16 - Device 1 functions 1 and 2 disabled

10: (Default)2x8, 2x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: 1x8,2x4,2x4 - Device 1 functions 1 and 2 enabled

Processor Strapping

CFG3
(PCI-E Static x4 Lane Reversal)

RSVD28
RSVD29

Ivy Bridge

CFG2
(PCI-E Static x16 Lane Reversal)

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

RESERVED

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

NCTF

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

Monday, January 07, 2013

Sheet
1

of

46

U38D

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AW24
AW20
BB18
AV18

[2]
[2]
[2]
[2]

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AY24
AY20
AY18
AU18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT

BJ24
+1.05V_VTT

R543

49.9/F_4 DMI_COMP

BG25

R550

750/F_4 DMI_BIAS

BH21

DMI_ZCOMP

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0
FDI_LSYNC1

0/J_4

R591

0/J_4

R614

*0/J_4

R615

0/J_4

SYS_PWROK_R
EC_PWROK_R
0/J_4

R3

APWROK_R
*0/J_4

P12

L10

PM_DRAM_PWRGD

B13

PCH_RSMRST#

C21

[34] PCH_RSMRST#

20121219SUSWARN# connect to Pin78 of EC (GPJ2)

R836
0/J_4 SUSWARN#_R

[34] PCH_SUSWARN#

+3V_S5

PWROK

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

+3V_S5

APWROK
DRAMPWROK

+3V_S5

RSMRST#

K16

WAKE#

+3V

SYS_PWROK

L22

DPWROK

SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN#/SUSPWRDNACK/GPIO30 +3V_S5
SLP_S3#

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]

[24] INT_LVDS_BLON
[24] INT_LVDS_DIGON

J47
M45

[24] INT_LVDS_BRIGHT

P45
T40
K47
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48

FDI_INT [2]

AV12

FDI_FSYNC0

BC10
AV14
BB10

A18

[2]

FDI_FSYNC1

[2]

FDI_LSYNC0

[2]

FDI_LSYNC1

[2]

AN47
AM49
AK49
AJ47
AF40
AF39

DSWVREN [8]

AH45
AH47
AF49
AF45

E22

DPWROK_R

R169

0/J_4

DPWROK [34]

B9

PCIE_WAKE#_LAN

R616

0/J_4

PCIE_LAN_WAKE# [28]

N3

CLKRUN#

CLKRUN#

G8

[27,34]

LPCPD# [27]

N14

PCH_SUSCLK

AH43
AH49
AF47
AF43

N48
P49
T49
T39
M40
SUSC# [34]

F4

SUSB# [34]

M47
M49

Close to PCH
R198

[34] DNBSWON#

E20

0/J_4

PWRBTN#

H20

ACPRESENT

[35] ACPRESENT

ACPRESENT / GPIO31

PM_BATLOW# E10
PM_RI#

SLP_A#

A10

DSW

SLP_SUS#

BATLOW# / GPIO72+3V_S5

PMSYNCH

+3V_S5

SLP_LAN# / GPIO29

RI#

L_BKLTCTL

G10

SLP_A#

G16

SLP_SUS#

TP34

K14

DAC_IREF
SLP_SUS# [11,34]

AP14

SDVO_STALLN
SDVO_STALLP

L_DDC_CLK
L_DDC_DATA

SDVO_INTN
SDVO_INTP

R139
1K/F_4

T43
T42

AP43
AP45
AM42
AM40
AP39
AP40

L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

TP32

H4

SDVO_TVCLKINN
SDVO_TVCLKINP

20120914 Add for TPM LPCPD#

TP30

D10

L_BKLTEN
L_VDD_EN

CRT_DDC_CLK
CRT_DDC_DATA

DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

P38
M39

HDMI_DDCCLK_SW [25]
HDMI_DDCDATA_SW [25]

AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

HDMI_HP [25]
INT_HDMITX2N
INT_HDMITX2P
INT_HDMITX1N
INT_HDMITX1P
INT_HDMITX0N
INT_HDMITX0P
INT_HDMICLKINT_HDMICLK+

P46
P42

INT_HDMITX2N
INT_HDMITX2P
INT_HDMITX1N
INT_HDMITX1P
INT_HDMITX0N
INT_HDMITX0P
INT_HDMICLKINT_HDMICLK+
DDPC_CTRLCLK
DDPC_CTRLDAT

AP47
AP49
AT38

[25]
[25]
[25]
[25]
[25]
[25]
[25]
[25]
[23]
[23]

INT_DP_AUXDN [23]
INT_DP_AUXDP [23]
[23]
DP_HPD_Q

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

DP_TXN0
DP_TXP0
DP_TXN1
DP_TXP1
DP_TXN2
DP_TXP2
DP_TXN3
DP_TXP3

[23]
[23]
[23]
[23]
[23]
[23]
[23]
[23]

M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

DisplayPort D

R612
[3] PM_DRAM_PWRGD

SYS_RESET#

*1U/10V_4

R611
PWROK_EC

SUSACK#

K3
C206

SYS_PWROK

C12

XDP_DBRST#

[3] XDP_DBRST#

SUSACK#_R

System Power Management

R604

AW16

[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]

DisplayPort C

DSWVRMEN

20121219SUSACK# connect to Pin79 of EC (GPJ3)

[34] PCH_SUSACK#

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

Digital Display Interface

[2]
[2]
[2]
[2]

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

CRT

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

FDI

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI

[2]
[2]
[2]
[2]

BE24
BC20
BJ18
BJ20

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

INT. HDMI

BC24
BE20
BG18
BG20

LVDS

U38C

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

07

CPT/PPT (LVDS,DDI)

CPT/PPT (DMI,FDI,PM) (CLG)

[2]
[2]
[2]
[2]

Panther Point_R1P0

PM_SYNC [3]
SLP_LAN#

TP29

The required series-resistors are:

Direct Connect - 33
Docking Topology - 20

Panther Point_R1P0

System PWR_OK (CLG)

PCH Pull-high/low (CLG)

IMVP_PWRGD PU +3V
PWROK_EC PD
so AND gate output dont need PD again

+3V_S5

+3V_S5

CRB 1.0 use 1K

8.2K/J_4

PM_RI#

R609

10K/J_4

XDP_DBRST#

R283

1K/F_4

PM_BATLOW#

R242

8.2K/J_4

R271

*1K/J_4

PCIE_WAKE#_LAN R618

10K/J_4

PCH_RSMRST# R547

10K/J_4

SLP_LAN#

*10K/J_4

to PCH Pin12,

SYS_PWROK

R577

10K/J_4
*10K/J_4

SUSWARN#_R
ACPRESENT

R196
R180

XDP and EE debug

U41

U40

2
2

[3] SYS_PWROK

IMVP_PWRGD_R

SYS_PWROK

1
1

10K/J_4

PWROK_EC

PWROK_EC

[34]

*TC7SH08

TC7SH08FU

R174

R208

C598
*0.1U/10V_4

C631
0.1u/10V_4

R275

+3V

CLKRUN#

DPWROK_R

+3V_S5

IMVP_PWRGD [3,40]
GFX_PWRGD [34,40]

Follow CRB 1.5 to pull

up 1K ohm to +3V

R599
100K/J_4

*10K/J_4

Follow Z09 NO STUFF

PM_DRAM_PWRGD R586

200/F_4

R554
R576

ACPRESENT would need a pull-up to DSW well if DSW

mode is supported on platform

*0/J_4

0/J_4

20111128 add 0ohm to passed IMVP_PERGD

include GFX_PWRGD to SYS_PWROK for PCH check

A

20120706:Speed up 250ms to boot up

R1,R2,R3 for EC power on 250 ms
20121004(EC Anda)
Chage trigger pin from +0.75V_ON to APWROK
R2 change to 100K

[34] APWROK

R607

R1

0/J_4

R2

APWROK_R

Quanta Computer Inc.

R608

PROJECT : ZQK

100K/J_4
Size

Document Number

Rev
1A

PCH 1/6 (DMI/FDI/VIDEO)

Date:
5

Monday, January 07, 2013

1

Sheet

of

46

+3V_RTC
RTC_RST#

20K/J_4

R672

D30
0/J_6

C591

18p/50V_4

*SHORT_ PAD1

RTC_X1

A20

RTC_X2

C20

RTCX1

J1

C651
1u/6.3V_4

C595

18p/50V_4

*SHORT_ PAD1

RTC_RST#

D20

SRTC_RST#

G22

SM_INTRUDER#

K22

PCH_INVRMEN

C17

RTCX2
RTCRST#

FWH4 / LFRAME#
SRTCRST#

+5V_S5

3VCCRTC_3

4.7K/J_4 VCCRTC_4

R811

4.7K/J_4

R133

+5V

20MIL

R810

ML1220 Coin type

AHL03001424 FDK
(SAY) 15mAH
AHL03017100 Panasonic (MAT) 17mAH

1M/J_4

ZRH use 2N7002D

3

CRB 1.0

C141

[30] SPKR

R143
1M/J_4

*22p/50V_4

C34

[30] PCH_AZ_CODEC_SYNC

R153

33/J_4

ACZ_SYNC_CODEC

A34

[30] PCH_AZ_CODEC_RST#

R166

33/J_4

ACZ_RST#_R

33/J_4

ACZ_SDOUT_R
TP12

PCH JTAG Debug (CLG)

[23]

SYS_COM_REQ

PCH_GPIO33

C36

SYS_COM_REQ

N32

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

A36

ACZ_SDOUT_R

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

HDA_SDIN0

G34

TP24

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

HDA_RST#

E34

ACZ_BITCLK_R

R529

SPKR

K34

ACZ_RST#_R

33/J_4

[30] PCH_AZ_CODEC_SDOUT

SERIRQ

HDA_SYNC

T10

SPKR

R163

[30] PCH_AZ_CODEC_BITCLK

LDRQ0#
LDRQ1# / GPIO23

HDA_BCLK

L34

ACZ_SYNC_R

[30] PCH_AZ_CODEC_SDIN0

HDA Bus (CLG)

+3V

INTVRMEN

N34

ACZ_BITCLK_R

Q17
2N7002K

150K/F_4

INTRUDER#

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

HDA_SDO
HDA_DOCK_EN# / GPIO33

+3V

HDA_DOCK_RST# / GPIO13

+3V_S5

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

+3V_S5
[3] XDP_TCLK_VT
R294

210/F_4

210/F_4

[3] PCH_XDP_TDO_VT
TP35

XDP_TMS_VT
PCH_XDP_TDO_VT
PCH_XDP_TDO
XDP_TCLK_VT

J3

XDP_TMS_VT

H7

PCH_XDP_TDO_VT

K5

PCH_XDP_TDO

H1

R272
100/F_4

R292
100/F_4

R303
100/F_4

PCH_SPI_CS0#

0/J_6

+3V_PCH_ME
U44

3
C636
*22p/50V_4

VDD
HOLD#

WP#

VSS

7 R656

3.3K/J_4

Layout Notes:
Place Series Resistors close to Flash ROM

C640
0.1u/10V_4

C601

1
6
5
2
3

*22p/50V_4

CE#
SCK
SI
SO

VDD
HOLD#

WP#

VSS

8
7 R570

3.3K/J_4
C621
0.1u/10V_4

ROM-4M_EC

[34] PCH_SPI_CLK_EC
[34] PCH_SPI_SI_EC
[34] PCH_SPI_SO_EC

R589

3.3K/J_4

33/J_4 PCH_SPI_CLK_R
33/J_4 PCH_SPI_SI_R
33/J_4 PCH_SPI_SO_R

R555
R552
R558

R584

LPC_LFRAME# [26,27,34]

E36 PCH_DRQ#0
K36 PCH_DRQ#1
V5
R634

SERIRQ

10K/J_4

[27,34]
+3V

SPI_CLK

Y14

PCH_SPI_CS1#

T1

PCH_SPI_SI

V4

PCH_SPI_SO

U3

SATA3RBIAS

AM3
AM1
AP7
AP5

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

[27]
[27]
[27]
[27]

AM10
AM8
AP11
AP10

SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1

[26]
[26]
[26]
[26]

AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1

PWROK

GNT3# / GPIO55

Top-Block Swap Override

PWROK

INTVRMEN

Integrated 1.05V VRM enable

ALWAYS

GNT1# / GPIO51

Boot BIOS Selection 1 [bit-1]

PWROK

Follow CRB 1.5 to use 10K ohm pull high

TP14
TP9

SATA HDD

mSATA

DG recommended that AC coupling capacitors should be

close to the connector (<100 mils) for optimal signal quality.

TP31

UM77 SATA port 1,3 disable.

TP69

Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1

Y11
Y10

SATA_COMP

R219

37.4/F_4

AB13

SATA3_COMP

R210

49.9/F_4

AH1

SATA3_RBIAS

R633

750/F_4

P3

SATA_ACT#

+1.05V_VTT

AB12

SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO

SATALED#

+3V

SATA0GP / GPIO21

+3V

SATA1GP / GPIO19

V14
P1

BBS_BIT0

R628

10K/J_4

+3V

R222

10K/J_4

+3V

R643

*10K/J_4

Configuration
0 = Default (weak pull-down 20K)
+3V

1 = Setting to No-Reboot mode

0 = "top-block swap" mode

R291

*1K/J_4

R508

*1K/J_4

R564

330K/J_4

R507

*1K/J_4

R627

*1K/J_4

SPKR

+3V_RTC

Used as GPIO only. at chklist 1.2

PCI_GNT3# [9]

1 = Default (weak pull-up 20K)

Should be always pull-up

SATA0GP/GPIO21
SATA4GP/GPIO16
SATA5GP/GPIO49
If these pins are unused use 8.2k
to 10k pull-up to +Vcc3_3 or 8.2k
to 10k pull-down to ground

PCH_INVRMEN

GNT1#

GPIO19

Boot BIOS Selection 0 [bit-0]

PWROK

HDA_SDO

Flash Descriptor Security

RSMRST

GPIO19

Boot Location

SPI

LPC

0 = effect (default)(weak pull-down 20K)

1 = overridden

DF_TVS

DMI/FDI Termination voltage

PWROK

GPIO28

On-die PLL Voltage Regulator

RSMRST#

R536

[34] ME_WR#
R606
R613

0 = Set to Vss (weak pull-down 20K)

2.2K/J_4
1K/J_4

BBS_BIT1 [9]

0/J_4

HDA_SYNC

On-Die PLL VR Voltage Select

RSMRST

GPIO15

Intel ME Crypto Transport Layer

Security (TLS) cipher suite
internal PD

RSMRST

DSWVREN

DEEP S4/S5 well

On Die DSW VR Enable

DSW

NV_ALE

Intel Anti-Theft HDD protection

Only for Interposer

PWROK

R299

*1K/J_4

1 = Support by 1.5V

R164

PLL_ODVR_EN

+3V_S5

ME_WR default EC setting folating

for future CPU, Sandy Bridge NC
DF_TVS needs to be pulled up to VccDFTERM power rail
through 2.2 kOhm 5% - R8361 change to 0 or not??

DF_TVS [10]
H_SNB_IVB# [3]

1 = Enable (weak pull-up 10K)

0 = Support by 1.8V (weak pull-down)

ACZ_SDOUT_R

+1.8V

1 = Set to Vcc
0 = Disable

Default weak pull-up on GNT0/1#

[Need external pull-down for LPC BIOS]

BBS_BIT0

[10]

1K/J_4

ACZ_SYNC_R

1K/J_4

PCH_GPIO15

Needs to be pulled High for Chief River platform

chklist 2.0

0 = Disable (Default)
1 = Enable

R622

+3V_S5

[10]
A

Layout Notes:
Place Series Resistors close to Flash ROM

[34] SPI_CS0#_UR_ME

Sampled

No reboot mode setting

PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
+3V_PCH_ME

Strap description

SPKR

+3V_PCH_ME
U39

33/J_4
33/J_4
33/J_4

[26,27,34]
[26,27,34]
[26,27,34]
[26,27,34]

3.3K/J_4

PCH_SPI_CS1#
PCH_SPI_CLK R560
PCH_SPI_SI
R551
PCH_SPI_SO R566

Pin Name

ROM-2M_ME

R654

+3V_PCH_ME

CE#
SCK
SI
SO

D36

Panther Point_R1P0

+3V_PCH_ME

1
33/J_4 PCH_SPI_CLK_R26
33/J_4 PCH_SPI_SI_R2 5
33/J_4 PCH_SPI_SO_R2 2

PCH_SPI_CS0#
PCH_SPI_CLK R652
PCH_SPI_SI
R653
PCH_SPI_SO
R655

SATAICOMPI

JTAG_TDO

T3

PCH Strap Table

W25Q16BVSSIG / AKE38FP0N01----->2MB
Layout Notes:
Place Series Resistors close to Flash ROM

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

20120919 FOLLOW Z09 NO STUFF

W25Q32BVSSIG / AKE391P0N00----->4MB

R661

JTAG_TDI

SATAICOMPO

SATA3COMPI

PCH Dual SPI (CLG) (Default for WIN8)

+3V_S5

JTAG_TMS

SATA3RCOMPO

PCH_SPI_CLK
R621
51/J_4

JTAG_TCK

SPI

R302

210/F_4

[3] XDP_TMS_VT

XDP_TCLK_VT

JTAG

R289

C38
A38
B37
C37

0/J_4

68.1K/F_4

ACZ_SYNC_CODEC
CN14
RTC_SOCKET

R173

Add MOSFET to separate CODEC SYNC signal

R808

R809

+3V_RTC

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

R549
10M/J_4

SATA 6G

C647
1u/6.3V_4

R663
1K/J_4

Y4
32.768KHZ

SATA

BAT54C

20MIL

RTC

SRTC_RST#

20K/J_4

R673

Q70
MMBT3904

08

U38A

VCCRTC_1

VCCRTC_2

CPT/PPT (HDA,JTAG,SATA) (CLG)

IHDA

R665

+3VPCU

J2

C650
1u/6.3V_4

30MIL

20MIL

PCH2 (CLG)
1

RTC (RTC)

High = Enable (Default)

+3V_RTC

R557

330K/J_4

Low = Disable
0 = Disable (Internal pull-down 20kohm)

R553

*330K/J_4
DSWVREN

+1.8V

R597

*1K/J_4

[7]

NV_ALE [9]

Quanta Computer Inc.

+3V_PCH_ME

0/J_4 PCH_SPI_CS1#

PROJECT : ZQK
Size
SPI_CS0#_UR_ME

R596

47K/J_4

Rev
1A

PCH 2/6 (SATA/RTC/HDA/LPC)

Date:

Document Number

Monday, January 07, 2013

Sheet
1

of

46

09

CPT/PPT (PCI-E,SMBUS,CLK)
CPT/PPT (PCI,USB,NVRAM) (CLG)

U38B

20111122 add for Touch pad interrupt pin from GPIO13 to GPIO11.

[31] USB30_RX1+
TP18
[23] USB30_RX3+
TP61
[31] USB30_TX1TP27
[23] USB30_TX3TP16
[31] USB30_TX1+
TP28
[23] USB30_TX3+
TP19

[8] BBS_BIT1
[10,32] BOARD_ID2
[8] PCI_GNT3#

C46
C44
E40

REQ1# / GPIO50 +3V

REQ2# / GPIO52 +3V
REQ3# / GPIO54 +3V

BOARD_ID2

D47
E42
F46

GNT1# / GPIO51 +3V

GNT2# / GPIO53 +3V
GNT3# / GPIO55 +3V

G42
G40
C42
D44

PIRQE# / GPIO2 +3V

PIRQF# / GPIO3 +3V
PIRQG# / GPIO4 +3V
PIRQH# / GPIO5 +3V

[26] CLK_LPC_DEBUG
[34] CLK_PCI_EC

PCI_PME#

PCI

REQ1#_GPIO50
REQ2#_GPIO52
REQ#3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

C33

USBRBIAS#

USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+

[31]
[31]
[31]
[31]
[23]
[23]
[24]
[24]
[31]
[31]

USB Port1 can be used on debug mode

MB USB 2.0 Port

Touch Panel

TP60

EHCI1

DB USB 2.0 Port

Camera

USBP10- [26]
USBP10+ [26]

BT+WL

SMBUS

CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P

+3V_S5

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P

+3V_S5

CLKIN_SATA_N
CLKIN_SATA_P

PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P

REFCLK14IN

+3V_S5

L14

PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

A14
K20
B17
C16
L16
A16
D14
C14

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

USB_OC0#
USB_OC1#
USB_OC2#
RAM_ID0
USB_OC4#
RAM_ID1
RAM_ID2
RAM_ID3

USB_OC0#

LAN

[31]

PCIECLKRQ5# / GPIO44

AB42
AB40

[28] CLK_PCIE_LANN
[28] CLK_PCIE_LANP

CLKIN_PCILOOPBACK

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

A12

DRAMRST_CNTRL_PCH

C8

SMB_ME0_CLK

G12

SMB_ME0_DAT

C13

SML1ALERT#_R

E14

SMB_ME1_CLK

M16

SMB_ME1_DAT

M7

CL_CLK1

CL_CLK1 [26]

T11

CL_DATA1

CL_DATA1 [26]

P10

CL_RST1#

CL_RST1# [26]

[23,26]

DRAMRST_CNTRL_PCH

[4]
D

For LAN
TP68

For EC

M10 PCIE_CLKREQ_PEG#_R
AB37
AB38
AV22
AU22

R308

EV@0/J_4

CLK_PCIE_VGAN
CLK_PCIE_VGAP

[16]
[16]

CLK_CPU_BCLKN
CLK_CPU_BCLKP

[3]
[3]

PEG_A_CLKREQ#

AM12
AM13

CLK_DPLL_SSCLKN
CLK_DPLL_SSCLKP

[16]

[3]
[3]

BF18 CLK_BUF_PCIE_3GPLLN
BE18 CLK_BUF_PCIE_3GPLLP
BJ30 CLK_BUF_BCLKN
BG30 CLK_BUF_BCLKP
G24 CLK_BUF_DREFCLKN
E24 CLK_BUF_DREFCLKP

XTAL25_IN

Y3
25MHz_XTAL

AK7 CLK_BUF_DREFSSCLKN
AK5 CLK_BUF_DREFSSCLKP
K45 CLK_PCH_14M
H45 CLK_PCI_FB

C564

10p/50V_4

CLKOUT_PCIE7N
CLKOUT_PCIE7P

+3V_S5

K12

PCIECLKRQ7# / GPIO46

10K/J_4

AK14
AK13

[3] CLK_PCIE_XDPN
[3] CLK_PCIE_XDPP

Y47 XCLK_RCOMP R504

90.9/F_4

10p/50V_4

+1.05V_VTT
20120201 Change CAP from 27P to 10P.

PCIECLKRQ6# / GPIO45

V38
V37

CLK_PCIE_REQ7#

C565

XCLK_RCOMP

+3V_S5

Panther Point_R1P0
TP17

R511
1M/J_4

CLKOUT_PCIE6N
CLKOUT_PCIE6P

T13

CLK_PCIE_REQ6#

V47 XTAL25_IN
V49 XTAL25_OUT

PEG_B_CLKRQ# / GPIO56

V40
V42

TP10

XTAL25_IN
XTAL25_OUT

+3V_S5

E6

[28] CLK_PCIE_LAN_REQ#

+3V

R137

SMB_PCH_DAT [23,26]

PME#

C6

H49
H43
22/J_4 PCLK_TPM_R
J48
22/J_4 CLK_PCI_FB_R
22/J_4 CLK_LPC_DEBUG_R K42
H40
22/J_4 CLK_PCI_775_R

*100K/J_4 DGPU_PWR_EN

SMB_PCH_CLK

SMB_PCH_DAT

CLKOUT_PCIE3N
CLKOUT_PCIE3P

V45
V46

[26] CLK_PCIE_WLAN_REQ#

R132

SMBALERT# [32]

SMB_PCH_CLK

C9

XTAL25_OUT

[26] CLK_PCIE_WLAN#
[26] CLK_PCIE_WLAN

Wireless

CLKOUT_DMI_N
CLKOUT_DMI_P

+3V

L12

20110908 WLAN support S3 wake up function.

22.6/F_4

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

PCIECLKRQ2# / GPIO20

Y43
Y45
PCIE_CLKREQ4#

+3V_S5

CLKOUT_PCIE2N
CLKOUT_PCIE2P

EHCI2

UM77 USB port 6,7,12,13 disable.

CL_RST1#

CLKOUT_DP_N
CLKOUT_DP_P

A8

PCIE_CLKREQ3#

CL_CLK1

PCIECLKRQ1# / GPIO18

Y37
Y36

1001(BIOS) Use port1 is enough

PCI-E*
+3V

V10

USB Port9 can be used on debug mode

R539

CLKOUT_PCIE1N
CLKOUT_PCIE1P

M1

PCIE_CLKREQ2#

TP21
TP25

USB_BIAS

PCIECLKRQ0# / GPIO73

AA48
AA47

USB port6/7 may not be available on all PCH sku

(HM55 support 12port only)

SML1DATA / GPIO75

PEG_A_CLKRQ# / GPIO47

+3V_S5

AB49
AB47

PCIE_CLKREQ1#

SML1CLK / GPIO58

CL_DATA1

CLKOUT_PCIE0N
CLKOUT_PCIE0P

XHCI for USBP0-3

Mini DP WITH 3.0 PORT

USBP8- [24]
USBP8+ [24]

PERN8
PERP8
PETN8
PETP8

J2

PCIE_CLKREQ0#

+3V_S5

PERN7
PERP7
PETN7
PETP7

Y40
Y39

MB USB WITH 3.0 PORT

+3V_S5

PERN6
PERP6
PETN6
PETP6

BE38
BC38
AW38
AY38

B33

USBRBIAS

K10

PCI_PLTRST#

R91
CLK_PCI_FB R122
R116
R138

[27] PCLK_TPM

USB2.0
PIRQA#
PIRQB#
PIRQC#
PIRQD#

AT12
BF3

RSVD28
RSVD29

K40
K38
H38
G38

TP33
[3,34] PCI_PLTRST#

USB30_RX1N
USB30_RX2N
USB30_RX3N
USB30_RX4N
USB30_RX1P
USB30_RX2P
USB30_RX3P
USB30_RX4P
USB30_TX1N
USB30_TX2N
USB30_TX3N
USB30_TX4N
USB30_TX1P
USB30_TX2P
USB30_TX3P
USB30_TX4P

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

MPC_PWR_CTRL#
DGPU_PWR_EN
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH

[42] DGPU_PWR_EN
[16] DGPU_HOLD_RST#

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

SML1ALERT# / PCHHOT# / GPIO74

SMBALERT#

H14

3
4

TP62

AY5
BA2

RSVD26
RSVD27

+3V_S5

PERN5
PERP5
PETN5
PETP5

BG40
BJ40
AY40
BB40

SML0CLK

E12

1
2

TP23
[23] USB30_RX3-

AT8

RSVD25

SML0ALERT# / GPIO60

SML0DATA

PERN4
PERP4
PETN4
PETP4

BJ38
BG38
AU36
AV36

UM77/HM70 will disable 5~8 PCIE ports

+3V_S5

PERN3
PERP3
PETN3
PETP3

BG37
BH37
AY36
BB36

NV_ALE [8]

SMBDATA

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

+3V

CLKOUTFLEX0 / GPIO64

+3V

CLKOUTFLEX1 / GPIO65

FLEX CLOCKS

[31] USB30_RX1-

BG36
BJ36
AV34
AU34

[28] PCIE_RXN3_LAN
[28] PCIE_RXP3_LAN
[28] PCIE_TXN3_LAN
[28] PCIE_TXP3_LAN

SMBALERT# / GPIO11
SMBCLK

PERN2
PERP2
PETN2
PETP2

BF36
BE36
AY34
BB34

AV5
AV10

RSVD23
RSVD24

USB3.0

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

LAN

+3V_S5

Link

TP21
TP22
TP23
TP24

USB30 Port1: EXT USB3.0 Port

USB30 Port3: Mini DP port

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

PERN1
PERP1
PETN1
PETP1

BE34
BF34
BB32
AY32

[26] PCIE_RX8[26] PCIE_RX8+

[26] PCIE_TX8[26] PCIE_TX8+

Wireless

BG34
BJ34
AV32
AU32

Controller

B21
M20
AY16
BG46

PCIE port 1 for commeral model S3 can't weak up.

AT10
BC8

RSVD5
RSVD6

USB

Layout Notes:
USB3 TX AC cap place at connector side, AC cap to
connector < 400mils

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

RSVD

AY7
AV7
AU3
BG4

RSVD1
RSVD2
RSVD3
RSVD4

CLOCKS

U38E

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

+3V

CLKOUTFLEX2 / GPIO66

+3V

CLKOUTFLEX3 / GPIO67

K43

SKU_ID1

F47

CLK_FLEX1

TP8

H47

BOARD_ID4

K49

[10,24]

TP59

Panther Point_R1P0

PLTRST#(CLG)

PCI/USBOC# Pull-up(CLG)
+3V

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC4#

R587
R201
R561
R206

R149
R152
R159
R155

MPC Switch Control

4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

10K/J_4
10K/J_4
10K/J_4
10K/J_4

2
PLTRST#

PLTRST# [16,26,27,28,34]

1
U42
TC7SH08FU

MPC_PWR_CTRL#

R624
100K/J_4

+3V_S5

RP1

R129

10
9
8
7
6

REQ1#_GPIO50
REQ2#_GPIO52
EXTTS_SNI_DRV1_PCH

*1K/J_4

1
2
3
4
5

DGPU_HOLD_RST#
MPC_PWR_CTRL#
REQ#3

+3V

RAMID@15K/F_4
*RAMID@15K/F_4
RAMID@15K/F_4
RAMID@15K/F_4

RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3

R575
R569
R203
R582

*RAMID@10K/J_4
RAMID@10K/J_4
*RAMID@10K/J_4
*RAMID@10K/J_4

EV@: For Optimize SKU

IV@: For UMA SKU
R115
R123

EV@10K/J_4
*IV@10K/J_4

R642
R626

EV@10K/J_4
*IV@10K/J_4

dGPU_PW_CTRL#
(GPIO68)
CTL : dGPU_VRON

SKU_ID1

UMA Only

dGPU Only
+3V

Elpida

Q PN

Mfr. PN

Freq.

SKU_ID0

+3V

R630
R632

10K/J_4
10K/J_4

PCIE_CLKREQ1#
PCIE_CLKREQ2#

R559
2.2K/J_4

R592
2.2K/J_4

5
3

[19,34] 2ND_MBCLK

R645
4.7K/J_4

S5

Q57

SMB_ME1_CLK

AKD5JGST400 EDJ4216EBBG-DJ-F
AKD5JGST407 EDJ4216EFBG-GNL-F

1333MHz
1600MHz

+3V
R144
R145

*IV@1K/J_4
EV@100K/F_4

0 or 1

SKU_ID1
SKU_ID0
VGA H/W
(GPIO64) (GPIO16)
Signal

DGPU_PW_CTRL#

[10]

S0

SMB_PCH_DAT

CLK_SDATA [13,15,32]

CLK_SCLK [13,15,32]

[19,34] 2ND_MBDATA

SMB_ME1_DAT

SMB_PCH_CLK

Setup
Menu

UMA

Hidden

UMA boot

Hidden

GPU boot

dGPU/SG

UMA boot

UMA/SG

UMA boot

GPU

Switchable
(Mux)

UMA+GPU

Optimize
(Muxless)

UMA

dGPU_PW_CTRL#
1 = GPU power is control by H/W (pure Discrete SKU)
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize)

CLK_BUF_BCLKN
CLK_BUF_BCLKP

R535
R530

10K/J_4
10K/J_4

CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M

R183
R192
R190
R191
R249
R247
R141

10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4

R215

*0/J_4

R220

*0/J_4

2N7002DW

20120712Add 0ohm reserved for two sides of

SMBUS since they are the same power plane
(CRB no level shift)

+3V_S5

R218
R625
R649
R231
R221
R595

CLOCK TERMINATION for FCIM

(Full Clock Integration Mode )

10K/J_4
2.2K/J_4
2.2K/J_4
2.2K/J_4
2.2K/J_4
10K/J_4

SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

PCH 3/6 (PCIE/USB/CLK/SMB)

Date:

R659
4.7K/J_4

Q60

+3V

[10]

0000
0001
0010

PCIE_CLKREQ4#
CLK_PCIE_WLAN_REQ#
PCIE_CLKREQ0#
PCIE_CLKREQ3#
CLK_PCIE_LAN_REQ#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#
PCIE_CLKREQ_PEG#_R

+3V_S5

Hynix

10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4

2N7002DW

Vender RAM_IDn

R216
R205
R648
R620
R276
R300
R228
R301

*0/J_4

DDRIII Memory down strap (CLG)

R574
R567
R200
R581

SMBus(PCH) (CLG)

+3V_S5

+3V

Low = MPC ON
High = MPC OFF (Default)

MPC_PWR_CTRL#

8.2K/J_4
8.2K/J_4
8.2K/J_4
8.2K/J_4

10K_10P8R

R658

SMBus(EC) (CLG)

+3V_S5

C634
0.1u/10V_4

PCI_PLTRST#

CLK_REQ/Strap Pin(CLG)
+3V

20120522follow CRB to modify power plan to +3V

check list 2.0When connected to the processor the PLTRST# signal
should be level shifted to 1.05V.

Monday, January 07, 2013

1

Sheet

of

46

CPT/PPT (GPIO,VSS_NCTF,RSVD) (CLG)

10

GPIO Pull-up/Pull-down (CLG)

U38F
S_GPIO
[34] SIO_EXT_SMI#

R278

100/J_4

T7

SIO_EXT_SMI#

A42

BOARD_ID1

H36

[34] SIO_EXT_SCI#

SIO_EXT_SCI#

E38

[24] TP_INT_PCH

TP_INT_PCH

C10
C4

SMIB
[8] PCH_GPIO15

G2

[9] SKU_ID0

U2

BMBUSY# / GPIO0

+3V

+3V

TACH4 / GPIO68

TACH1 / GPIO1

+3V

+3V

TACH5 / GPIO69

TACH2 / GPIO6

+3V

+3V

TACH6 / GPIO70

TACH3 / GPIO7

+3V

+3V

TACH7 / GPIO71

GPIO8

LAN_PHY_PWR_CTRL / GPIO12

[8] PLL_ODVR_EN

[20,43] DGPU_VRON
C

T5

PCH_GPIO24

E8

W K_GPIO27

E16

PLL_ODVR_EN

P8

STP_PCI#

K1

DGPU_VRON

K4

DMI_OVRVLTG

V8

FDI_OVRVLTG

M5

MFG_MODE

N2

BOARD_ID0

M3
V13

TEST_SET_UP

TP36

CRIT_TEMP_REP#

V3

SV_DET

D6

SATA4GP / GPIO16

PECI

+3V

TACH0 / GPIO17

+3V

SCLOCK / GPIO22

+3V

GPIO24 / MEM_LED +3V_S5

GPIO27

DSW

GPIO28

+3V_S5

INIT3_3V#
DF_TVS

SATA2GP / GPIO36
SATA3GP / GPIO37

TS_VSS3

+3V

TS_VSS4

+3V

+3V

NC_1

SDATAOUT0 / GPIO39

+3V

SDATAOUT1 / GPIO48

+3V

A45
A46
A5
B

A6
B3
B47
BD1
BD49
BE1

SATA2GP/SATA3GP : When Unused as GPIO or SATA*GP - Use

8.2K-10K pull-down to ground by chklist 2.0
NOTE: The internal pull-down is disabled after PLTRST#
deasserts.
NOTE: This signal should not be pulled high when strap is
sampled.

BE49
BF1
BF49

A40

R524

20120625
<PCH_GPIO24>Follow CRB to pull up 10K ohm

1.5K/F_4

+3V

+3V

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57 +3V_S5

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4
VSS_NCTF_5

P4

SIO_A20GATE

AU16

EC_PECI_R

P5

SIO_RCIN#

SIO_A20GATE
R212

*0/J_4

AY10

EC_PECI [3,34]
SIO_RCIN#

AY11

[34]

[34]

H_PW RGOOD [3]

PCH_THRMTRIP#

R225

390/J_4

R252

*10K/J_4

PLL_ODVR_EN

R307

10K/J_4

SIO_EXT_SMI#
SIO_EXT_SCI#

R509
R148

10K/J_4
10K/J_4

STP_PCI#
SIO_A20GATE
SIO_RCIN#
CRIT_TEMP_REP#

R647
R270
R288
R635

*10K/J_4
10K/J_4
10K/J_4
10K/J_4

R185
R181

10K/J_4
*10K/J_4

R131

*10K/J_4

+3VPCU

PM_THRMTRIP# [3]

T14
AY1

W K_GPIO27
20111017 un-stuff R5126 for DSW

DF_TVS [8]

AH8
AK11

GPIO27 : If not used then use 8.2-k to 10-k pull-down to GND.

AH10

AK10

DMI TERMINATION
VOLTAGE OVERRIDE
P37

USB3.0 IC CTL

Low = Tx, Rx terminated to

same voltage (DC Coupling Mode)
(DEFAULT)

+3V

VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2
BG48
+3V_S5

R229

*10K/J_4 DMI_OVRVLTG

R279

*200K/F_4

BH3
SMIB

R623

10K/J_4

BH47
BJ4
BJ44
+3V_S5

SV_SET_UP

high VDDR=+1.35V_SUS for DDR3L

Low VDDR =+1.5V_SUS(default)

BJ45
R280

BJ46

*10K/J_4

SV_DET

R274

100K/J_4

High = Strong (Default)

assign to VID for VDDR control

BJ5
+3V

BJ6
TEST_SET_UP

C2

R273
R248

+3V

10K/J_4
*1K/J_4

R631
R162
R99
R520
R506

C48
D1
D49

10K/J_4
10K/J_4
*10K/J_4
10K/J_4
*10K/J_4

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4

R646
R151
R105
R522
R505

*10K/J_4
*10K/J_4
10K/J_4
*10K/J_4
10K/J_4

[9,32] BOARD_ID2
[9,24] BOARD_ID4

SGPIO

E1
E49
+3V

F1
S_GPIO

F49

R285
R284

1K/J_4
*1K/J_4

BOARD_ID0

High
GDDR5

Low
DDR3

BOARD_ID1 Disable on board memory

Enable on board memory

BOARD_ID2 Pin8 of SYNAPTICS and ELAN are NC pin

Default is pull high
BIOS maybe will use EEPROM detection
BOARD_ID3

Panther Point_R1P0

BOARD_ID4

+3V

20120607follow CRB pull down

2011/09/01 add select resistor

+3V_S5

PCH_GPIO24

LOW = USB3.0 IC
VSS_NCTF_15

NCTF

A44

BOARD_ID3

DGPU_PW ROK

TS_VSS2

GPIO35 +3V

SLOAD / GPIO38

THRMTRIP#

TS_VSS1

+3V

STP_PCI# / GPIO34

PROCPWRGD

VSS_NCTF_18
A4

TACH5_GPIO69

C41

+3V

A20GATE

CPU/MISC

SCLOCK_GPIO22

B41

+3V_S5

GPIO15 +3V_S5

GPIO

D40

DGPU_PW ROK

DGPU_PW _CTRL# [9]

+3V_S5

RCIN#
[20] DGPU_PW ROK

C40

+3V

No touch panel

Touch panel

MFG-TEST
R298
TACH5_GPIO69

R510

LVDS = Pull HIGH

eDP = Pull LOW

100K/J_4 FDI_OVRVLTG

R290

*1K/J_4

SCLOCK_GPIO22 R268
R250

10K/J_4
*1K/J_4

1K/J_4

Quanta Computer Inc.

+3V

FDI TERMINATION
VOLTAGE OVERRIDE

LOW - Tx, Rx terminated

to same voltage

High = Disable (Default)

G_SENSOR_ID

MFG_MODE

R644
R629

10K/J_4
*1K/J_4

PROJECT : ZQK
Size

Low = Enable
4

Rev
1A

PCH 4/6 (GPIO/MISC)

Date:

Document Number

Monday, January 07, 2013

Sheet
1

10

of

46

PCH5(CLG)

+1.05V_VTT
R182
+1.05V_VTT

0/J_6

+1.05V_VCCAPLL_EXP

L30

*1uH/25mA_6

AK37

AN16
AN17

R172

0/J_6

C161
1u/6.3V_4

C187
1u/6.3V_4

C166
1u/6.3V_4
AN21
AN26
AN27

C201
1u/6.3V_4

C172
10u/6.3V_6

AP21
AP23
AP24
AP26

+3V

AT24

+3V_VCC_EXP
R540

0/J_8

AN33
AN34
C583
0.1u/10V_4
BH29

+VCCAFDI_VRM

+VCCAFDI_VRM
+1.05V_VTT

R605

AP16

*0/J_8 +1.05V_VCCAPLL_FDI

BG6

+1.05V_VCCDPLL_FDI

AP17

0/J_8
AU20

+3V_SUS_CLKF33

T38

VCCIO[30]
VCCDSW3_3

C219
*0.1u/10V_4

+VCCAPLL_CPY_PCH

DCPSUSBYP

VCCIO[32]
VCCIO[33]

L29

*10uH/100mA_8

BH23
R170

+1.05V_VTT
C589
*10u/6.3V_6

AP36

0/J_6

+VCCDPLL_CPY

AP37

+VCCSUS1

AL29
AL24

+3V_VCC_GIO

VCCAPLLEXP
VCCIO[15]
VCCIO[16]

+1.05V_VTT

V33

VCC3_3[6]

R93
V34

VCC3_3[7]

0/J_6

+1.05V_VTT

C85
0.1u/10V_4

C176
*1u/6.3V_4

VCCME(+1.05V) = ??A(??mils)

+3V

VCCSUS3_3[7]
VCCAPLLDMI2
VCCSUS3_3[8]
VCCIO[14]
DCPSUS[3]

R204

0/J_6

+1.1V_VCC_DMI

AA26
R197

C180
1u/6.3V_4

VCCIO[19]

AA27

0/J_4

AT16

VCCVRM[3]

+VCCAFDI_VRM

C182
1u/6.3V_4

+VCCAFDI_VRM

AA31

20120216 remove R168 for power plant chnge to +1.05V_VTT.

+1.1V VCC_DMI witdth >= 20mils.

AC26

VCCIO[20]
VCCIO[21]

VCCIO[24]

C179
1u/6.3V_4

AA29

VCCIO[18]

VCCIO[23]

AA24

+1.05V_VCCASW

VCCDMI = 42mA(10mils)

VCCIO[17]

VCCIO[22]

AA21

VccASW =1.01 A(60mils)

C157
1u/6.3V_4

AT20

VCCDMI[1]

+1.1V_VCC_DMI_CCI
AB36

VCCCLKDMI

C159
10u/6.3V_6

VCCCLKDMI = 20mA(8mils)
+VCC_DMI_CCI

L12

*10uH/100mA_8
R124

C167
10u/6.3V_6

AC27

+1.05V_VTT

AC29
AC31

*1/F_4
AD29

C131
1u/6.3V_4

C120
*10u/6.3V_6

R125

0/J_4
AD31

VCCIO[25]

W21

VCCIO[26]

AG16

VCCDFTERM[1]

VCC3_3[3]

VCCVRM[2]
VccAFDIPLL

+VCCP_NAND

+1.8V

VCCIO[27]
VCCDMI[2]

W23

VCCPNAND = 190 mA(15mils)

AG17

VCCDFTERM[2]

W24
R568

0/J_8
W26

AJ16

VCCDFTERM[3]

C203
0.1u/10V_4

W29
+1.05V_VTT

AJ17

VCCDFTERM[4]

R213

W31
0/J_6

VCCIO[34]

C635
1u/6.3V_4

R158

C200

0.1u/10V_4 +VCCRTCEXT

N16

VCCASW[3]

V5REF_SUS

VCCASW[4]

+VCCAFDI_VRM

Y49

VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]

DCPSUS[4]
VCCSUS3_3[1]

V5REF

VCCASW[15]
VCCASW[16]

C142
1u/6.3V_4

20120105 change power plant to +3V for power saving.

+1.05V_VTT

VCCDIFFCLKN= 55mA(18mils)

*0/J_6

R637

0/J_6

VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]

VCCASW[20]
DCPRTC
VCCVRM[4]

VCCIO[13]

VCCADPLLA
VCCADPLLB

R209

*0/J_6

+V1.05V_SSCVCC
C209
*1u/6.3V_4

Reserve +3V_S5 to VCCSPI for EC 795 co-layout

C190

0.1u/10V_4 +VCCSST

+1.05V_VTT

*0/J_6

+V1.05M_VCCSUS
R585

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCIO[2]
VCCIO[3]

0/J_4

AG33
V16
T17
V19

VCCRTC<1mA(8mils)

+3V_RTC

C616
4.7u/6.3V_6

C618
0.1u/10V_4

C619
0.1u/10V_4
A22

C586
1u/6.3V_4

VCCSSC

VCCIO[4]

C585
0.1u/10V_4

C587
0.1u/10V_4

T23

+3V_VCCPUSB

T24
R545
V24

C181
0.1u/10V_4

P24

+3V_VCCAUBG

T26

+VCCAUPLL

M26

+5V_PCH_VCC5REFSUS

VCCASW[22]

V_PROC_IO

VCCRTC

VCCASW[23]
VCCASW[21]

VCCSUSHDA

AN23

+VCCA_USBSUS

AN24

+3V_VCCPSUS

P34

10uH/100mA_8

L27

10uH/100mA_8

C77
4.7u/6.3V_6

C569
1u/6.3V_4

10uH/100mA_8

+1.05V_VCCA_B_DPL
+ C574
220u/2.5V_3528

10/F_4

+5V

RB500V-40

+3V
20111018 change for DSW

P20

R548

+3V_VCCPSUS

P22

0/J_6

+3VCC_S5

VCCSUS3_3 = 119mA(15mils)

C594
1u/10V_4
AA16
W16

R202

+3V_VCCPCORE

T34

0/J_6

+3V

VCCPCORE = 28mA(10mils)

+3V

C188
0.1u/10V_4

AJ2

+3V

AF13

C637
0.1u/10V_4

AH13

R267

+1.05V_VCC_IO

AH14

0/J_6

R515
100K/J_4

+1.05V_VTT

C224
1u/10V_4

AF14

??mA(??mils)
AK1

L31

+V1.1LAN_VCCAPLL

*10uH/100mA_8

+1.05V_VTT

VCCVRM= 114mA(15mils)
AF11

C638
*10u/6.3V_6

+VCCAFDI_VRM

AC16

+1.05V_VTT

AC17
C202
1u/6.3V_4

AD17

T21

R146

VCCME = 1.01A(60mils)

0/J_6

V21
T19

P32

+V3.3A_1.5A_HDA_IO
R179

*0/J_4

+5VCC_S5

+3V_S5

0/J_4

VCCSUSHDA= 10mA(8mils)

C160
0.1u/10V_4

R531

+3V_S5

*0/J_4

Q51
AO3413

C570
*0.33u/10V_6

+3VCC_S5

R518
100K/J_4

Q54
AO3413

R546
0/J_6

[7,34] SLP_SUS#

C571
1u/6.3V_4

Q55
2N7002DW

+3VCC_S5

C105
1u/6.3V_4

R514
0/J_6

C86
1u/10V_4
L28

+5VCC_S5

RB500V-40

N22

R521

C568
*0.33u/10V_6

+1.05V_VCCA_A_DPL
+ C563
220u/2.5V_3528

+3V_SUS_CLKF33

10/F_4

20111018 change for DSW

R117

+5V_PCH_VCC5REF

1/F_4 L8

VCC5REFSUS=1mA

R532

N20

+1.05V_VTT

*0/J_6

+1.05V_VTT

C186
*1u/6.3V_4

R81

0/J_6

C155
0.1u/10V_4

C139
*1u/6.3V_4

+5V_S5

R89

R193

+1.05V_VTT

DCPSUS[1]
DCPSUS[2]

Panther Point_R1P0

+3V

0/J_6

V23

DCPSST

+VTT_VCCPCPU

1mA(8mils)

BJ8
20120216 remove R172 for power plant chnge to +1.05V_VTT.

VCCIO[6]
VCCAPLLSATA
VCCVRM[1]

MISC

R130

R638

VCCSUS3_3[3]

VCC3_3[2]

VCCSSC= 95mA(10mils)

+3V_S5

20111018 change for DSW

C582
0.1u/10V_4

C130
0.1u/10V_4

VCCASW[19]

CPU

+1.05V_VTT

VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1

1.5V (Mobile)

AF17
AF33
AF34
AG34

0/J_6

T29

VCCASW[18]

RTC

+VCCAFDI_VRM

0/J_6

BF47

R537

VCCASW[17]

HDA

+3V_VCCME_SPI

VCCSUS3_3[2]

VCC3_3[4]

0/J_6

+3V

R108

BD47

+1.05V_VCCA_B_DPL
+VCCDIFFCLK
+VCCDIFFCLKN

VccDMI needs to be powered by the same 1.05 V voltage source as

the CPU VCCIO, and the trace needs to be at least 20 mils width with full VSS/
VCC reference plane.

+1.5V

+1.05V_VCCA_A_DPL

8mA(8mils)

T27

D6

SATA

R157

65mA(10mils)

VCCSUS3_3 = 119mA(15mils)
+3VCC_S5

P28

V5REF= 1mA

Panther Point_R1P0
C143
1u/6.3V_4

P26

D24

VCCIO[12]
+VCCAFDI_VRM

0/J_6

C151
1u/6.3V_4

VCCASW[2]

VCCIO[5]

V1

VCCSPI

W33

VCCASW[1]

VCCSPI = 20mA(8mils)
C204
1u/6.3V_4

+1.1V VCC_DMI witdth >= 20mils.

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]

AA19

N26

VCC3_3[5]

VCCIO[28]

FDI

R556

V12

VCCIO[31]

When Dis sku and eDP , LVDS power can short to GND

+3V_VCCME_SPI

+1.1V_VCC_DMI

T16

PCH_VCCDSW

AM38

VCCTX_LVDS[2]

HVCMOS

0/J_8

+VCCPDSW

+1.05V_VTT
0/J_6

R178

+1.05V_VCCIO
VCCIO[29]

VCCDSW3_3= 3mA

C253
0.1u/10V_4
+1.05V_VTT

VCCACLK

AM37

VCCTX_LVDS[1]

DMI

R165

VccIO =2.925 A(140mils)

AD49

0/J_4

20120104 change power plant from +3V_S5 to +3VPCU.

VSSALVDS

POWER

U38J
R269

+3VPCU

AK36

VCCTX_LVDS[4]

VCCIO

BJ22

*0/J_8

+VCCACLK

VCCALVDS

DFT / SPI

AN19

+1.05V_VTT

R104

+1.05V_VTT

C561
10u/6.3V_6

U47

VSSADAC

VCCTX_LVDS[3]
C590
*10u/6.3V_6

C562
0.1u/10V_4

C566
0.01u/25V_4

C567
10u/6.3V_6

C169
4.7u/6.3V_6

U48

VCCADAC

C184
1u/6.3V_4

POWER

USB

C156
1u/6.3V_4

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

Clock and Miscellaneous

C173
1u/6.3V_4

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

CPT/PPT (POWER) (CLG)

180ohm/1.5A

PCI/GPIO/LPC

+1.05V_VCCCORE

CRT

0/J_8

VCC CORE

R135

LVDS

U38G

VccCORE =1.3 A(60mils)

+1.05V_VTT

11

+3V
L26

+VCCA_DAC_1_2

VccADAC =1mA(8mils)

CPT/PPT (POWER) (CLG)

20111117 change mose footprint to dual type.

20111018 ADD DSW Cricuit

20111030 modify cuirucit.

Quanta Computer Inc.

PROJECT :ZQK
Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

PCH 5/6 (POWER)

5

Sheet

11

of

46

12

PCH6(CLG)
IBEX PEAK-M (GND) (CLG)
U38H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

U38I

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

Panther Point_R1P0

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

Panther Point_R1P0

Quanta Computer Inc.

PROJECT :ZQK
Size

Document Number

Rev
1A

PCH 6/6 (GND)

Date:
5

Monday, January 07, 2013

Sheet
1

12

of

46

[4,14] M_A_DQSN[7:0]

[4,14] M_A_A[15:0]

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

SO-DIMMB SPD Address is 0XA4

SO-DIMMB TS Address is 0X34

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

[4,14] M_A_BS#0
[4,14] M_A_BS#1
[4,14] M_A_BS#2

M2
N8
M3

[4] M_A_CLK0
[4] M_A_CLK0#
[4] M_A_CKE0

J7
K7
K9

[4]
[4]
[4,14]
[4,14]
[4,14]

K1
L2
J3
K3
L3

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_DQSP0
M_A_DQSP1

F3
C7
E7
D3

M_A_DQSN0
M_A_DQSN1

[4,14,15]

T2

DDR3_DRAMRST#

L8

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ

R255
240/F_4
M_A_CLK0

J1
L1
J9
L9

C485
1.6P/50V_4
M_A_CLK0#
R266
30/F_4

R265
30/F_4

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_A_DQ6
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ0

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ8
M_A_DQ15
M_A_DQ14
M_A_DQ11
M_A_DQ13
M_A_DQ10
M_A_DQ9
M_A_DQ12

+SMDDR_VREF_DIMM M8
H1
SMDDR_VREF_DQ0

+1.5VSUS

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

M_A_ZQ1

Should be 240
Ohms +-1%

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_A_BS#0
M_A_BS#1
M_A_BS#2

M2
N8
M3

M_A_CLK0
M_A_CLK0#
M_A_CKE0

J7
K7
K9

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

K1
L2
J3
K3
L3

M_A_DQSP2
M_A_DQSP3

F3
C7
E7
D3

M_A_DQSN2
M_A_DQSN3

DDR3_DRAMRST#
M_A_ZQ2

Should be 240
Ohms +-1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

G3
B7

T2
L8

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_A_DQ19
M_A_DQ22
M_A_DQ18
M_A_DQ16
M_A_DQ21
M_A_DQ20
M_A_DQ23
M_A_DQ17

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ28
M_A_DQ25
M_A_DQ30
M_A_DQ27
M_A_DQ24
M_A_DQ26
M_A_DQ29
M_A_DQ31

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_A_BS#0
M_A_BS#1
M_A_BS#2

M2
N8
M3

M_A_CLK0
M_A_CLK0#
M_A_CKE0

J7
K7
K9

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

K1
L2
J3
K3
L3

M_A_DQSP5
M_A_DQSP4

F3
C7

ODT
CS
RAS
CAS
WE
DQSL
DQSU

E7
D3
M_A_DQSN5
M_A_DQSN4

G3
B7

DDR3_DRAMRST#

T2

B1
B9
D1
D8
E2
E8
F9
G1
G9

DML
DMU
DQSL
DQSU

RESET

L8

M_A_ZQ3

Should be 240
Ohms +-1%

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

CK
CK
CKE

ZQ

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

J1
L1
J9
L9

E3
F7
F2
F8
H3
H8
G2
H7

M_A_DQ42
M_A_DQ44
M_A_DQ46
M_A_DQ41
M_A_DQ45
M_A_DQ40
M_A_DQ43
M_A_DQ47

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ36
M_A_DQ38
M_A_DQ35
M_A_DQ37
M_A_DQ32
M_A_DQ39
M_A_DQ33
M_A_DQ34

+SMDDR_VREF_DIMM M8
SMDDR_VREF_DQ0 H1

+1.5VSUS

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R697
240/F_4

13

BYTE7_56-63
U26

VREFCA
VREFDQ

BA0
BA1
BA2

BYTE6_48-55

U23
+SMDDR_VREF_DIMM M8
H1
SMDDR_VREF_DQ0

+1.5VSUS

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R323
240/F_4

J1
L1
J9
L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

BYTE5_40-47

BYTE3_24-31

U21

VREFCA
VREFDQ

BYTE4_32-39

U19

+SMDDR_VREF_DIMM
SMDDR_VREF_DQ0

[6,14] SMDDR_VREF_DQ0_M3

*M3@0/J_6

R694

BYTE1_8-15

[4,14] M_A_DQ[63:0]

Checklist 2.0:
M3 has to be no stuff on Chief River

BYTE2_16-23

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_A_BS#0
M_A_BS#1
M_A_BS#2

M2
N8
M3

M_A_CLK0
M_A_CLK0#
M_A_CKE0

J7
K7
K9

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

K1
L2
J3
K3
L3

M_A_DQSP7
M_A_DQSP6

F3
C7
E7
D3

M_A_DQSN7
M_A_DQSN6

DDR3_DRAMRST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

T2
L8

M_A_ZQ4

Should be 240
Ohms +-1%

G3
B7

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

M_A_DQ60
M_A_DQ61
M_A_DQ63
M_A_DQ57
M_A_DQ62
M_A_DQ56
M_A_DQ58
M_A_DQ59

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ53
M_A_DQ55
M_A_DQ52
M_A_DQ50
M_A_DQ49
M_A_DQ54
M_A_DQ48
M_A_DQ51
+1.5VSUS

BA0
BA1
BA2

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSU
DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSL
DQSU

RESET
ZQ

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R724
240/F_4

J1
L1
J9
L9

E3
F7
F2
F8
H3
H8
G2
H7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BYTE0_0-7

[4,14] M_A_DQSP[7:0]

DDR ON BOARD RAM (DDR)

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM

+SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

C244
0.1u/10V_4

C602
0.1u/10V_4

C725
0.1u/10V_4

C703
0.1u/10V_4

C717
0.1u/10V_4

C493
0.1u/10V_4

C720
0.1u/10V_4

C714
0.1u/10V_4

C481
0.1u/10V_4

C715
0.1u/10V_4

C711
0.1u/10V_4

C713
0.1u/10V_4

+1.5VSUS

change to 1K/F_4
+1.5VSUS

R226
1K/F_4

+SMDDR_VREF

+SMDDR_VREF_DIMM

SMDDR_VREF_DQ0_M3 1
C741
1u/6.3V_4

C745
1u/6.3V_4

C278
1u/6.3V_4

C470
1u/6.3V_4

C746
1u/6.3V_4

C653
1u/6.3V_4

C421
1u/6.3V_4

+1.5VSUS

C793
1u/6.3V_4

C687
1u/6.3V_4

C633
1u/6.3V_4

C809
1u/6.3V_4

C785
1u/6.3V_4

C418
1u/6.3V_4

C644
1u/6.3V_4

C667
1u/6.3V_4

C763
10u/6.3V_6

C663
10u/6.3V_6

C283
10u/6.3V_6

C304
10u/6.3V_6

C801
10u/6.3V_6

+ C742
330u/2V_7343

+1.5VSUS

R227

+SMDDR_VREF_DIMM

C661
1u/6.3V_4

C684
1u/6.3V_4

C768
1u/6.3V_4

C398
1u/6.3V_4

C251
1u/6.3V_4

C689
1u/6.3V_4

C436
1u/6.3V_4

C739
1u/6.3V_4

C686
1u/6.3V_4

C665
1u/6.3V_4

C642
1u/6.3V_4

C459
1u/6.3V_4

C772
1u/6.3V_4

C315
1u/6.3V_4

C674
1u/6.3V_4

[4,14,15]

C764
10u/6.3V_6

C314
10u/6.3V_6

C289
10u/6.3V_6

C690
10u/6.3V_6

+SMDDR_VREF

SMDDR_VREF_DQ0

Q21
*AP2302GN

R230
1K/F_4

SPD address= A0 hex (for MD devices)

C431
1u/6.3V_4

C673
1u/6.3V_4

C290
1u/6.3V_4

C789
1u/6.3V_4

C783
1u/6.3V_4

C293
1u/6.3V_4

C252
1u/6.3V_4

C473
1u/6.3V_4

C752
1u/6.3V_4

C675
1u/6.3V_4

C285
1u/6.3V_4

C488
1u/6.3V_4

C685
1u/6.3V_4

C649
1u/6.3V_4

C256
1u/6.3V_4

C294
1u/6.3V_4

C780
10u/6.3V_6

C786
10u/6.3V_6

C735
10u/6.3V_6

C691
10u/6.3V_6

R666
R662

C643
10u/6.3V_6
[9,15,32]
[9,15,32]

+1.5VSUS
C274
1u/6.3V_4

C417
1u/6.3V_4

C771
1u/6.3V_4

C682
1u/6.3V_4

C250
1u/6.3V_4

+1.5VSUS

C781
C767
1u/6.3V_4

C728
1u/6.3V_4

C287
1u/6.3V_4

C639
1u/6.3V_4

C284
1u/6.3V_4

C632
1u/6.3V_4

C646
1u/6.3V_4

C258
1u/6.3V_4

CLK_SCLK
CLK_SDATA
+3V

C432
1u/6.3V_4
C681
10u/6.3V_6

C736
10u/6.3V_6

C723
10u/6.3V_6

C280
10u/6.3V_6

C483
10u/6.3V_6

R321

6
5

CLK_SCLK
CLK_SDATA

*0/J_4

WP =1 : WRITE DISABLE

C688
1u/6.3V_4

*1K/F_4
*1K/F_4

MD0_SA0 R668
MD0_SA1 R664

1K/F_4
1K/F_4

U45

+1.5VSUS

C671
1u/6.3V_4

CHA0

SA1
0

SA0
0

CHA1

CHB0

CHB1

+1.5VSUS
+3V

*0/J_6

DEEPS3_EC

C489
10u/6.3V_6

+1.5VSUS
+1.5VSUS

R214

C223
0.1u/10V_4

C245
0.1u/10V_4

+1.5VSUS

C802
1u/6.3V_4

*0/J_6

CRB Add
R232
1K/F_4

R224
1K/F_4

C420
1u/6.3V_4

C480
0.1u/10V_4

+1.5VSUS

+1.5VSUS

Place these Caps near Memory Down

+1.5VSUS

C710
C712
0.1u/10V_4 0.1u/10V_4

R322
*0/J_4

*150u/6.3V_3528

SCL
SDA
WP

A0
A1
A2
VCC
GND

1
2
3

MD0_SA0
MD0_SA1
+3V

8
4

Quanta Computer Inc.

*M24C02-WMN6TP
C286
*0.1u/10V_4

PROJECT : ZQK
Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

DDR3 MEMORY DOWN X 16

1

Sheet
8

13

of

46

BYTE1_8-15

[4,13] M_A_DQ[63:0]
U43

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

SO-DIMMB SPD Address is 0XA4

SO-DIMMB TS Address is 0X34

BA0
BA1
BA2

J7
K7
K9

[4] M_A_CLK1
[4] M_A_CLK1#
[4] M_A_CKE1

CK
CK
CKE

K1
L2
J3
K3
L3

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_DQSP0
M_A_DQSP1

ODT
CS
RAS
CAS
WE

F3
C7

DQSL
DQSU

E7
D3

M_A_DQSN0
M_A_DQSN1

[4,13,15]

G3
B7

DQSL
DQSU

RESET

L8

ZQ

M_A_ZQ5

Should be 240
Ohms +-1%

DML
DMU

T2

DDR3_DRAMRST#

1
C484
1.6P/50V_4

J1
L1
J9
L9

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ15
M_A_DQ8
M_A_DQ11
M_A_DQ14
M_A_DQ12
M_A_DQ9
M_A_DQ10
M_A_DQ13

+SMDDR_VREF_DIMM M8
H1
SMDDR_VREF_DQ0

+1.5VSUS

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

M_A_CLK1#

R254
30/F_4

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R671
240/F_4
M_A_CLK1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

M2
N8
M3

[4,13] M_A_BS#0
[4,13] M_A_BS#1
[4,13] M_A_BS#2

[4]
[4]
[4,13]
[4,13]
[4,13]

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_A_DQ3
M_A_DQ6
M_A_DQ0
M_A_DQ2
M_A_DQ5
M_A_DQ4
M_A_DQ1
M_A_DQ7

B2
D9
G7
K2
K8
N1
N9
R1
R9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_A_BS#0
M_A_BS#1
M_A_BS#2

M2
N8
M3

M_A_CLK1
M_A_CLK1#
M_A_CKE1

J7
K7
K9

+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

K1
L2
J3
K3
L3

M_A_DQSP2
M_A_DQSP3

F3
C7
E7
D3

M_A_DQSN2
M_A_DQSN3

DDR3_DRAMRST#
M_A_ZQ6

Should be 240
Ohms +-1%

G3
B7

T2
L8

R688
240/F_4

J1
L1
J9
L9

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_A_DQ22
M_A_DQ19
M_A_DQ17
M_A_DQ18
M_A_DQ20
M_A_DQ23
M_A_DQ16
M_A_DQ21

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ25
M_A_DQ28
M_A_DQ27
M_A_DQ30
M_A_DQ31
M_A_DQ29
M_A_DQ26
M_A_DQ24

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE5_40-47

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

B2
D9
G7
K2
K8
N1
N9
R1
R9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_A_BS#0
M_A_BS#1
M_A_BS#2

M2
N8
M3

M_A_CLK1
M_A_CLK1#
M_A_CKE1

J7
K7
K9

+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

K1
L2
J3
K3
L3

M_A_DQSP5
M_A_DQSP4

F3
C7
E7
D3

M_A_DQSN5
M_A_DQSN4

DDR3_DRAMRST#
M_A_ZQ7

Should be 240
Ohms +-1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

BYTE7_56-63

G3
B7

T2
L8

R718
240/F_4

J1
L1
J9
L9

U49

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ

14

BYTE6_48-55

U48
+SMDDR_VREF_DIMM M8
H1
SMDDR_VREF_DQ0

+1.5VSUS

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

BYTE4_32-39

BYTE3_24-31

U46

E3
F7
F2
F8
H3
H8
G2
H7

*M3@0/J_6

[4,13] M_A_A[15:0]

M8
H1

R246

+SMDDR_VREF_DIMM
SMDDR_VREF_DQ0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

M_A_DQ44
M_A_DQ46
M_A_DQ41
M_A_DQ42
M_A_DQ47
M_A_DQ45
M_A_DQ40
M_A_DQ43

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ38
M_A_DQ36
M_A_DQ37
M_A_DQ35
M_A_DQ39
M_A_DQ33
M_A_DQ34
M_A_DQ32

+SMDDR_VREF_DIMM M8
SMDDR_VREF_DQ0 H1

+1.5VSUS

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

B2
D9
G7
K2
K8
N1
N9
R1
R9

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M_A_BS#0
M_A_BS#1
M_A_BS#2

M2
N8
M3

M_A_CLK1
M_A_CLK1#
M_A_CKE1

J7
K7
K9

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

K1
L2
J3
K3
L3

M_A_DQSP7
M_A_DQSP6

F3
C7

VREFCA
VREFDQ

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODT
CS
RAS
CAS
WE

DDR3_DRAMRST#

Should be 240
Ohms +-1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSL
DQSU

T2

RESET

L8

M_A_ZQ8

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSU

G3
B7

M_A_DQSN7
M_A_DQSN6

ZQ

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R765
240/F_4

J1
L1
J9
L9

NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
RAM _DDR3

R253
30/F_4

M_A_DQ61
M_A_DQ63
M_A_DQ57
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ56
M_A_DQ62

D7
C3
C8
C2
A7
A2
B8
A3

M_A_DQ55
M_A_DQ53
M_A_DQ50
M_A_DQ52
M_A_DQ54
M_A_DQ48
M_A_DQ51
M_A_DQ49
+1.5VSUS

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

[4,13] M_A_DQSN[7:0]

Checklist 2.0:
M3 has to be no stuff on Chief River
[6,13] SMDDR_VREF_DQ0_M3

BYTE2_16-23

BYTE0_0-7

[4,13] M_A_DQSP[7:0]

DDR ON BOARD RAM (DDR)

B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSUS

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM

+SMDDR_VREF_DIMM
C

SMDDR_VREF_DQ0

C243
0.1u/10V_4

C716
0.1u/10V_4

C693
0.1u/10V_4

C721
0.1u/10V_4

C726
0.1u/10V_4

C507
0.1u/10V_4

C680
0.1u/10V_4

C249
0.1u/10V_4

C702
0.1u/10V_4

C506
0.1u/10V_4

change to 1K/F_4
+SMDDR_VREF_DIMM
+SMDDR_VREF
R571

*0/J_6

SMDDR_VREF_DQ0_M3 1

C254
C719
0.1u/10V_4 0.1u/10V_4

C603
0.1u/10V_4

CRB Add
[4,13,15]

R562
1K/F_4

+SMDDR_VREF_DIMM

R573
1K/F_4

C724
0.1u/10V_4

C492
0.1u/10V_4

+1.5VSUS

+1.5VSUS

R572
1K/F_4

C733
0.1u/10V_4

Q56
*AP2302GN

+SMDDR_VREF

SMDDR_VREF_DQ0

R563
1K/F_4

R565

*0/J_6

C600
0.1u/10V_4

DEEPS3_EC

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

DDR3 MEMORY DOWN X 16

1

Sheet
8

14

of

46

DDR3 DIMM-A (DDR)

+1.5VSUS

M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_CS#0
M_B_CS#1
M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
M_B_CKE0
M_B_CKE1
M_B_CAS#
M_B_RAS#
M_B_WE#

[9,13,32] CLK_SCLK
[9,13,32] CLK_SDATA

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

DIMM1_SA0
DIMM1_SA1
CLK_SCLK
CLK_SDATA

109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120

[4] M_B_ODT0
[4] M_B_ODT1

11
28
46
63
136
153
170
187
[4] M_B_DQSP[7:0]

12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

[4] M_B_DQSN[7:0]
B

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

PC2100 DDR3 SDRAM SO-DIMM

(204P)

[4] M_B_A[15:0]

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ51
M_B_DQ48
M_B_DQ49
M_B_DQ55
M_B_DQ50
M_B_DQ56
M_B_DQ60
M_B_DQ62
M_B_DQ58
M_B_DQ61
M_B_DQ57
M_B_DQ59
M_B_DQ63

2.48A

199

+3V

77
122
125
198
30

TP80
[4,13,14] DDR3_DRAMRST#
R281

[6] SMDDR_VREF_DQ1_M3
+SMDDR_VREF_DIMM_A

*M3@0/J_6

+SMDDR_VREF_DQ1

15

JDIM1B

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

M_B_DQ[63:0] [4]

JDIM1A

[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]

1
126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

PC2100 DDR3 SDRAM SO-DIMM

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

+0.75V_DDR_VTT

VTT1
VTT2
GND
GND

203
204
205
206

DDR3-DIMM1_H=5.2_RVS

+SMDDR_VREF

Intel M1 solution

+1.5VSUS

+1.5VSUS

20110817 change to 1K/F_4

R296
1K/F_4
R277

SMDDR_VREF_DQ1_M3

DDR3-DIMM1_H=5.2_RVS

+SMDDR_VREF_DQ1

R355

*0/J_6
R350
1K/F_4

Q22
*AP2302GN

R286
1K/F_4

C255
470P/50V_4

C257

C270

0.1u/16V_4

2.2u/6.3V_6

C750
470P/50V_4

C749

C373

0.1u/16V_4

2.2u/6.3V_6

[4,13,14] DEEPS3_EC

+1.5VSUS

20121203
Add 39pF for ESD

+3V

+1.5VSUS
C761
C709

C747

C679

C692

C704

C718

C729

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4

0.1u/16V_4 *150u/6.3V_3528

C740

R400
*10K/J_4

DIMM1_SA0

R406
10K/J_4

CHA0

R401
10K/J_4

+0.75V_DDR_VTT

C478

C476

C495

C511

C513

C512

C494

2.2u/6.3V_6

0.1u/16V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

*10u/6.3V_6

SA1
0

SA0
0

DIMM1_SA1

CHA1

R409
*10K/J_4

CHB0

CHB1

+3V

+SMDDR_VREF_DIMM_A

CRB Add

Place these Caps near SO_DIMM-A

*0/J_6

R353 20110817 change to 1K/F_4

1K/F_4

+0.75V_DDR_VTT

C848
39P/50V_4

C849
39P/50V_4
A

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

DDR3 DIMMA-RSV H=5.2

Date:
5

Monday, January 07, 2013

Sheet
1

15

of

46

1000mA

C171
C183
C158
C147
C154

place near balls

place under BGA
A

+1.05V_GFX

C226

To be placed no further from the GPU C225

than bewteen BGA and Power supply C246

C247
C178
C149
C148

place near balls

place under BGA

EV@22u/6.3V_8
EV@22u/6.3V_8
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@4.7u/6.3V_6
EV@1u/6.3V_4
EV@1u/6.3V_4

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

EV@22u/6.3V_8
EV@22u/6.3V_8
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@4.7u/6.3V_6
EV@1u/6.3V_4
EV@1u/6.3V_4

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

[PEG Interface]

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1378MILS

AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32

1001Remove 3V3MISC's Cap by FAE Nelson suggesLon

PLACE NEAR TO GPU BALLS

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13

PLACE UNDER GPU BALLS

J8
K8
L8
M8

+3V_GFX

L8/M8/K8/J8 0.4MM = 16mils

VDD33_1
VDD33_2
VDD33_3
VDD33_4

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

1001Remove 3V3MISC by FAE Nelson suggesLon

FAEPlease use +3V_GFX to instead 3V3MISC power rail

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_WAKE
PEX_RST_N
PEX_CLKREQ_N
PEX_TERMP

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

PEG_TX8_C
PEG_TX#8_C
PEG_TX9_C
PEG_TX#9_C
PEG_TX10_C
PEG_TX#10_C
PEG_TX11_C
PEG_TX#11_C
PEG_TX12_C
PEG_TX#12_C
PEG_TX13_C
PEG_TX#13_C
PEG_TX14_C
PEG_TX#14_C
PEG_TX15_C
PEG_TX#15_C

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

PEG_RX8_C
PEG_RX#8_C
PEG_RX9_C
PEG_RX#9_C
PEG_RX10_C
PEG_RX#10_C
PEG_RX11_C
PEG_RX#11_C
PEG_RX12_C
PEG_RX#12_C
PEG_RX13_C
PEG_RX#13_C
PEG_RX14_C
PEG_RX#14_C
PEG_RX15_C
PEG_RX#15_C

+3V_GFX

TESTMODE

C629
C628
C611
C612
C627
C626
C610
C609
C624
C625
C608
C607
C623
C622
C605
C606

EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4

PEG_TX8 [2]
PEG_TX#8 [2]
PEG_TX9 [2]
PEG_TX#9 [2]
PEG_TX10 [2]
PEG_TX#10 [2]
PEG_TX11 [2]
PEG_TX#11 [2]
PEG_TX12 [2]
PEG_TX#12 [2]
PEG_TX13 [2]
PEG_TX#13 [2]
PEG_TX14 [2]
PEG_TX#14 [2]
PEG_TX15 [2]
PEG_TX#15 [2]

AJ26
AK26

PEX_PLLVDD

*EV@1u/6.3V_4

PEX_PLL_HVDD
PEX_SVDD_3V3

EV@0.1u/10V_4
EV@0.1u/10V_4
*EV@0.1u/10V_4

3.3V_AUX_NC

PLACE UNDAER GPU BALLS L8/M8

VDD_SENSE
GND_SENSE

+3V_GFX

+3V_GFX

R580
EV@10K/F_4

0816 follow Z09 to isolate CLK_REQ#

PEG_A_CLKREQ# [9]

PU at page 9

Q58
EV@2N7002K

C197
C198
C216
C217
C214
C215
C195
C196
C213
C212
C194
C193
C192
C191
C211
C210

EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4
EV@0.22u/10V_4

PEG_RX8 [2]
PEG_RX#8 [2]
PEG_RX9 [2]
PEG_RX#9 [2]
PEG_RX10 [2]
PEG_RX#10 [2]
PEG_RX11 [2]
PEG_RX#11 [2]
PEG_RX12 [2]
PEG_RX#12 [2]
PEG_RX13 [2]
PEG_RX#13 [2]
PEG_RX14 [2]
PEG_RX#14 [2]
PEG_RX15 [2]
PEG_RX#15 [2]

+3V

C218
EV@0.1u/10V_4

[9,26,27,28,34]
CLK_PCIE_VGAP [9]
CLK_PCIE_VGAN [9]

PEX_TSTCLK
PEX_TSTCLK#

R186

PLTRST#

*EV@200/F_4

PEGX_RST#

PEGX_RST# [19]

[9] DGPU_HOLD_RST#

20120813: EC control PEGX_RST#

U16

R199
EV@100K/F_4

0815 change R53 to 1% tolerance

AJ11
AJ12

PEGX_WAKE
PEGX_RST#

AK12

PEX_CLKREQ#

AP29

PEX_TERMP

R590

EV@2.49K/F_4

TESTMODE

R195

EV@10K/F_4

EV@MC74VHC1G08DFT2G

TP26

0817 RSVD R46 and C49 for GV2 co-layout sDDR3

PEX_RST timing

PEX_PLLVDD : 0.3MM = 12mils (150mA)

AK11
PEX_PLLVDD

R207

EV@0_6

EV@4.7u/6.3V_6

C153
C59
C65

Layout Notes:
Place decoupling CAPs close to GPU

PEX_CLKREQ#

AL13
AK13

PLACE NEAR TO GPU L8/M8

C152

16
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

1001Remove 3V3MISC by FAE Nelson suggesLon

FAEPlease use +3V_GFX to instead 3V3MISC power rail

C144

U35A

AG19
AG21
AG22
AG24
AH21
AH25

2500mA

To be placed no further from the GPU C207

than bewteen BGA and Power supply C208

+1.05V_GFX

Layout Notes:
+1.05_GFX trace width = 250mils

AG26

C185

EV@4.7u/6.3V_6

AH12
AG12

C145

EV@1u/6.3V_4

C163

EV@0.1u/10V_4
PLACE UNDAER BALLS

+1.05V_GFX

I/O 3.3V

Place near BGA

C199
*EV@1u/6.3V_4

PEX_RST
D

P8
C72
C89
C99

L4

EV@0.1u/10V_4
EV@4.7u/6.3V_6
EV@4.7u/6.3V_6

+3V_GFX

AH12/AG12 need 210mA of +3V_GFX

Trise >= 1uS

PLACE NEAR BALLS

Quanta Computer Inc.

L5

EV@N14P_GV2

GPU_VCCP_SENSE [43]
GPU_VSSP_SENSE [43]

Tfail <=500nS

PROJECT : ZQK

8mils width
(0.2MM)

Size

Document Number

Rev
1A

DGPU 1/5 (PEG)

Date:
1

Monday, January 07, 2013

7

Sheet

16
8

of

46

U35B

[21] FBA_CMD[30:0]

TP13

P30
F31
F34
M32
AD31
AL29
AM32
AF34

VMA_DM0
VMA_DM1
VMA_DM2
VMA_DM3
VMA_DM4
VMA_DM5
VMA_DM6
VMA_DM7

[21] VMA_DM[7..0]

DBI

FBA_CMD0 (FBA_CMD25)
FBA_CMD1 (FBA_CMD23) [MEMORY
FBA_CMD2
FBA_CMD3 (FBA_CMD0)
FBA_CMD4 (FBA_CMD10)
FBA_CMD5 (FBA_CMD26)
FBA_CMD6 (FBA_CMD14)
FBA_CMD7
FBA_CMD8 (FBA_CMD1)
FBA_CMD9 (FBA_CMD22)
FBA_CMD10 (FBA_CMD20)
FBA_CMD11 (FBA_CMD24)
FBA_CMD12 (FBA_CMD18)
FBA_CMD13 (FBA_CMD9)
FBA_CMD14 (FBA_CMD29)
FBA_CMD15 (FBA_CMD8)
FBA_CMD16 (FBA_CMD27)
FBA_CMD17 (FBA_CMD15)
FBA_CMD18 (FBA_CMD11)
FBA_CMD19 (FBA_CMD16)
FBA_CMD20 (FBA_CMD28)
FBA_CMD21 (FBA_CMD3)
FBA_CMD22 (FBA_CMD17)
FBA_CMD23 (FBA_CMD5)
FBA_CMD24 (FBA_CMD4)
FBA_CMD25 (FBA_CMD21)
FBA_CMD26 (FBA_CMD6)
FBA_CMD27 (FBA_CMD13)
FBA_CMD28 (FBA_CMD19)
FBA_CMD29 (FBA_CMD12)
FBA_CMD30
FBA_CMD31 (NC)

I/F A]

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

[21] VMA_WDQS[7..0]

EDC
[21] VMA_RDQS[7..0]

VMA_WDQS0
VMA_WDQS1
VMA_WDQS2
VMA_WDQS3
VMA_WDQS4
VMA_WDQS5
VMA_WDQS6
VMA_WDQS7

M31
G31
E33
M33
AE31
AK30
AN33
AF33

VMA_RDQS0
VMA_RDQS1
VMA_RDQS2
VMA_RDQS3
VMA_RDQS4
VMA_RDQS5
VMA_RDQS6
VMA_RDQS7

M30
H30
E34
M34
AF30
AK31
AM34
AF32
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27

+1.5V_GFX

0816 follow DG to place caps

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1378MILS

+1.5V_GFX

PLACE UNDER GPU BALLS

0.1u x 6
stuff x4

1u x 6
stuff x4

4.7u x 6
stuff x4

C55
C53
C32
C54
C58
C136

EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
*EV@0.1u/10V_4
*EV@0.1u/10V_4

C30

EV@1u/6.3V_4

C31

EV@1u/6.3V_4

C51

EV@1u/6.3V_4

C52

EV@1u/6.3V_4

C44

*EV@1u/6.3V_4

C43

*EV@1u/6.3V_4

C581
C119
C60
C134
C96
C57

EV@4.7u/6.3V_6
EV@4.7u/6.3V_6
EV@4.7u/6.3V_6
EV@4.7u/6.3V_6
*EV@4.7u/6.3V_6
*EV@4.7u/6.3V_6

C68
C81
C110
C584

10u x 4
stuff x2

EV@10u/6.3V_6
EV@10u/6.3V_6
*EV@10u/6.3V_6
*EV@10u/6.3V_6

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FBVDDQ_44

FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
(FBA_DEBUG) FBA_DEBUG0
(NC) FBA_DEBUG1
FB_VREF_NC
FBA_CMD_RFU0
FBA_CMD_RFU1
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
RSVD
FB_DLL_AVDD
FBA_PLL_AVDD
FBVDDQ_PROBE
GND_PROBE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND

C125

EV@22u/6.3V_8

C536

*EV@22U/6.3V_8

C537

*EV@22U/6.3V_8

PLACE NEAR TO GPU BALLS

FB_CALTERM_GND

VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
VMA_DQ4
VMA_DQ5
VMA_DQ6
VMA_DQ7
VMA_DQ8
VMA_DQ9
VMA_DQ10
VMA_DQ11
VMA_DQ12
VMA_DQ13
VMA_DQ14
VMA_DQ15
VMA_DQ16
VMA_DQ17
VMA_DQ18
VMA_DQ19
VMA_DQ20
VMA_DQ21
VMA_DQ22
VMA_DQ23
VMA_DQ24
VMA_DQ25
VMA_DQ26
VMA_DQ27
VMA_DQ28
VMA_DQ29
VMA_DQ30
VMA_DQ31
VMA_DQ32
VMA_DQ33
VMA_DQ34
VMA_DQ35
VMA_DQ36
VMA_DQ37
VMA_DQ38
VMA_DQ39
VMA_DQ40
VMA_DQ41
VMA_DQ42
VMA_DQ43
VMA_DQ44
VMA_DQ45
VMA_DQ46
VMA_DQ47
VMA_DQ48
VMA_DQ49
VMA_DQ50
VMA_DQ51
VMA_DQ52
VMA_DQ53
VMA_DQ54
VMA_DQ55
VMA_DQ56
VMA_DQ57
VMA_DQ58
VMA_DQ59
VMA_DQ60
VMA_DQ61
VMA_DQ62
VMA_DQ63

R30
R31
AB31
AC31

VMA_CLK0
VMA_CLK0#
VMA_CLK1
VMA_CLK1#

TP82

FBA_DEBUG
FBA_DEBUG1

[22] VMC_WDQS[7..0]

VMC_WDQS0
VMC_WDQS1
VMC_WDQS2
VMC_WDQS3
VMC_WDQS4
VMC_WDQS5
VMC_WDQS6
VMC_WDQS7

D10
D5
C3
B9
E23
E28
B30
A23

[22] VMC_RDQS[7..0]

VMC_RDQS0
VMC_RDQS1
VMC_RDQS2
VMC_RDQS3
VMC_RDQS4
VMC_RDQS5
VMC_RDQS6
VMC_RDQS7

D9
E4
B2
A9
D22
D28
A30
B23

MEMORY I/F C

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_CLK0
FBC_CLK0_N
FBC_CLK1
FBC_CLK1_N

R76
R154

*EV@60.4/F_4
*EV@60.4/F_4

(FBC_DEBUG) FBB_DEBUG0
(NC) FBB_DEBUG1

+1.5V_GFX

FBB_CMD_RFU0
FBB_CMD_RFU1

TP5

R32
AC32

0815 no stuff follow CRB

FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N

K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N

GC6 connect to EC

E1

FB_CLAMP

K27

+FB_PLLAVDD

FBC_D00
FBC_D01
FBC_D02
FBC_D03
FBC_D04
FBC_D05
FBC_D06
FBC_D07
FBC_D08
FBC_D09
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

VMA_CLK0 [21]
VMA_CLK0# [21]
VMA_CLK1 [21]
VMA_CLK1# [21]

15mils width
R28
AC28
H26

E11
E3
A3
C9
F23
F27
C30
A24

VMC_DM0
VMC_DM1
VMC_DM2
VMC_DM3
VMC_DM4
VMC_DM5
VMC_DM6
VMC_DM7

[22] VMC_DM[7..0]

FBB_CMD0 (FBC_CMD25)
FBB_CMD1 (FBC_CMD23)
FBC_CMD2
FBB_CMD3 (FBC_CMD0)
FBB_CMD4 (FBC_CMD10)
FBB_CMD5 (FBC_CMD26)
FBB_CMD6 (FBC_CMD14)
FBC_CMD7
FBB_CMD8 (FBC_CMD1)
FBB_CMD9 (FBC_CMD22)
FBB_CMD10 (FBC_CMD20)
FBB_CMD11 (FBC_CMD24)
FBB_CMD12 (FBC_CMD18)
FBB_CMD13 (FBC_CMD9)
FBB_CMD14 (FBC_CMD29)
FBB_CMD15 (FBC_CMD8)
FBB_CMD16 (FBC_CMD27)
FBB_CMD17 (FBC_CMD15)
FBB_CMD18 (FBC_CMD11)
FBB_CMD19 (FBC_CMD16)
FBB_CMD20 (FBC_CMD28)
FBB_CMD21 (FBC_CMD3)
FBB_CMD22 (FBC_CMD17)
FBB_CMD23 (FBC_CMD5)
FBB_CMD24(FBC_CMD4)
FBB_CMD25 (FBC_CMD21)
FBB_CMD26 (FBC_CMD6)
FBB_CMD27 (FBC_CMD13)
FBB_CMD28 (FBC_CMD19)
FBB_CMD29 (FBC_CMD12)
FBC_CMD30
FBC_CMD31 (NC)

17

R472

EV@0/J_4

R473

EV@10K/J_4

EC_FB_CLAMP [19,20,34]

FBB_PLL_AVDD

G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

VMC_DQ0
VMC_DQ1
VMC_DQ2
VMC_DQ3
VMC_DQ4
VMC_DQ5
VMC_DQ6
VMC_DQ7
VMC_DQ8
VMC_DQ9
VMC_DQ10
VMC_DQ11
VMC_DQ12
VMC_DQ13
VMC_DQ14
VMC_DQ15
VMC_DQ16
VMC_DQ17
VMC_DQ18
VMC_DQ19
VMC_DQ20
VMC_DQ21
VMC_DQ22
VMC_DQ23
VMC_DQ24
VMC_DQ25
VMC_DQ26
VMC_DQ27
VMC_DQ28
VMC_DQ29
VMC_DQ30
VMC_DQ31
VMC_DQ32
VMC_DQ33
VMC_DQ34
VMC_DQ35
VMC_DQ36
VMC_DQ37
VMC_DQ38
VMC_DQ39
VMC_DQ40
VMC_DQ41
VMC_DQ42
VMC_DQ43
VMC_DQ44
VMC_DQ45
VMC_DQ46
VMC_DQ47
VMC_DQ48
VMC_DQ49
VMC_DQ50
VMC_DQ51
VMC_DQ52
VMC_DQ53
VMC_DQ54
VMC_DQ55
VMC_DQ56
VMC_DQ57
VMC_DQ58
VMC_DQ59
VMC_DQ60
VMC_DQ61
VMC_DQ62
VMC_DQ63

D12
E12
E20
F20

VMC_CLK0
VMC_CLK0#
VMC_CLK1
VMC_CLK1#

G14
G20

FBC_DEBUG
FBC_DEBUG1

C12
C20

FBVDDQ_SENSE_NC

F2

FB_GND_SENSE_NC

C61

D6
D7
C6
B6
F26
E26
A26
A27

EV@10K/F_4

FBA_CMD5

R114

EV@10K/F_4

FBA_CMD18

R544

EV@10K/F_4

FBA_CMD19

R538

EV@10K/F_4

FBC_CMD2

R25

EV@10K/F_4

FBC_CMD3

R26

EV@10K/F_4

FBC_CMD5

R63

EV@10K/F_4

FBC_CMD18

R370

EV@10K/F_4

FBC_CMD19

R407

EV@10K/F_4

0815 confirm with ZQS (sDDR3)

VMA_DQ[63:0]
VMC_DQ[63:0]

VMA_DQ[63:0] [21]
VMC_DQ[63:0] [22]

VMC_CLK0 [22]
VMC_CLK0# [22]
VMC_CLK1 [22]
VMC_CLK1# [22]
R184
R188

*EV@60.4/F_4
*EV@60.4/F_4

+1.5V_GFX

0815 no stuff follow CRB

C

1012(FAE)Reserve +FB_PLLAVDD evan without CH-B

H17 +FB_PLLAVDD

EV@0.1u/10V_4

TP4
TP58

J27

FB_CAL_PD_VDDQ

R84

EV@40.2/F_4

H27

FB_CAL_PU_GND

R77

EV@42.2/F_4

FB_CAL_TERM_GND

R70

H25

EV@10K/F_4

R74

C94

EV@0.1u/10V_4

C6218 close ball K27 35mA

+FB_PLLAVDD

F1

R78

FBA_CMD3

F8
E8
A5
A6
D24
D25
B27
C27

EV@N14P_GV2
U27

FBA_CMD2

L9
C64

EV@PBY160808T-30Y-N_6
EV@22u/6.3V_8

C67
C63

EV@0.1u/10V_4
*EV@0.1u/10V_4

C107 close to ball H17

+1.05V_GFX

PLACE NEAR TO GPU BALLS

PLACE UNDER GPU BALLS
+FB_PLLAVDD = 0.3mm 12mils
U27+H17 62mA

+1.5V_GFX

R1
EV@51.1/F_4 R2

Layout Notes: PLACE CLOSE TO GPU BALLS

EV@N14P_GV2

+1.5V_GFX

C1
C6

EV@22u/6.3V_8

*EV@330u/2.5V_3528

22u x 4
stuff x2

C538

U35C
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

[22] FBC_CMD[30:0]
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

EV@330u/2V_7343

0813
sDDR3
R1=42.2/F
R2=51.1/F

Quanta Computer Inc.

PROJECT : ZQK
Size

RSVD 330u, ZQS have one

Document Number

Rev
1A

DGPU 2/5 (Memory)

Date:
1

Monday, January 07, 2013

17

Sheet
8

of

46

18
U35D

AH8
AG8
AG9
A

AJ8

IFPAB_PLLVDD

[IFPA/B_LVDS]

IFPA_IOVDD
IFPB_IOVDD

IFPAB_RSET

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

AF7
AG7

AF6
AG6
B

AF8
AN2

AB8
AC7
AC8
AD6

IFPC_PLLVDD

IFPC_AUX_I2CW_SCL

[IFPC/D_TMDS]IFPC_AUX_I2CW_SDA_N

IFPD_PLLVDD

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

IFPC_IOVDD
IFPD_IOVDD

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

IFPC_RSET
IFPD_RSET

IFPEF_PLLVDD

[IFPE/F_DP]

IFPE_IOVDD
IFPF_IOVDD
IFPEF_RSET

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

AG10
AP9

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1318MILS

AP8

DACA_VDD

[DACA/B_CRT]

DACA_RED
DACA_GREEN
DACA_BLUE

AN6
AM6
AN3
AP3
AM5
AN5
AK6
AL6
AH6
AJ6

AH9
AJ9
AP5
AP6
AL7
AM7
AM8
AN8
AL8
AK8
AG3
AG2
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
AK3
AK2
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5

AB3
AB4
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
AF3
AF2
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1

AK9
AL10
AL9

DACA_VREF
DACA_HSYNC
DACA_VSYNC

DACA_RSET

I2CA_SCL
I2CA_SDA

AM9
AN9
R4
R5

EV_CRTDCLK
EV_CRTDDAT

R107
R106

EV@2.2K_4
EV@2.2K_4

NV_PLLVDD 0.3MM=12mils 78mA

L14

EV@160808-30Y

NV_PLLVDD

C140
EV@22u/6.3V_8

C137
EV@0.1u/10V_4

PLACE NEAR TO GPU BALLS

AD8

PLLVDD
C548

EV@10p/50V_4

CLK_27M_VGA_2

3
4

+1.05V_GFX

PLACE UNDER GPU BALLS

R481
*EV@1M/J_4

Y2
EV@27MHZ

AE8

SP_PLLVDD

C554

GPU_SP_PLLVDD 0.3MM=12mils
+1.05V_GFX

L15

XTALOUT

AD7 : 41mA

EV@160808-0180P
C168

EV@10p/50V_4

1
2

AE8 : 71mA

SP_VID_PLLVDD

AD7

VID_PLLVDD

[XTAL IN]

C165
C164

C138

XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN

H3
H2
J4
H1

CLK_27M_VGA_2
XTALOUT
R79
EV@10K/F_4
R492
EV@10K/F_4

Quanta Computer Inc.

EV@N14P_GV2
EV@22u/6.3V_8

EV@4.7u/6.3V_6

PLACE NEAR TO GPU BALLS

1

EV@0.1u/10V_4
EV@0.1u/10V_4

PROJECT : ZQK
Size

Document Number

Date:

Monday, January 07, 2013

PLACE UNDER GPU BALLS

Rev
1A

DGPU 3/5 (Display)

3

Sheet

18

of
8

46

Logical Strap Bit Mapping

PU-VDD
PD
4.99K
10K
15K
20K
24.9K
30.1K
34.8K
45.3K

U35E

[MIOA]

1000
1001
1010
1011
1100
1101
1110
1111

0000
0001
0010
0011
0100
0101
0110
0111

Logical
Strapping Bit3

Logical
Strapping Bit2

ROM_SO

FB_1

FB_0

SMB_ALT_ADDR

VGA_DEVICE

1000

ROM_SCLK

PCI_DEVIDE[4]

SUB_VENDOR

PCI_DEVID[5]

PEX_PLL_EN_TERM

1292

RAMCFG[2]

RAMCFG[3]

Logical
Strapping Bit1

Logical
Strapping Bit0

RAMCFG[1]

RAMCFG[0]

XXXX

USER[3]

USER[2]

USER[1]

USER[0]

1111

STRAP1

3GIO_PADCFG[3]

3GIO_PADCFG[2]

3GIO_PADCFG[1]

3GIO_PADCFG[0]

0110

STRAP2

PCI_DEVID[3]

PCI_DEVID[2]

PCI_DEVID[1]

PCI_DEVID[0]

0010

STRAP3

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

0000

STRAP4

RESERVED

PCIE SPEED
CHANGE GEN3

PCIE_MAX SPEED

DP_PLL_VDD33

0111

19

STRAP3
Optimus ---> 4.99k PD
Discrete only ---> 15K PD

STRAP0

ROM_SI

Resistor P/N
4.99K---> CS24992FB26
10K ---> CS31002FB26
15K ---> CS31502FB24
20K ---> CS32002FB29
24.9K---> CS32492FB16
30.1K---> CS33012FB18
34.8K---> CS33482FB22
45.3K---> CS34532FB18

+3V_GFX
+3V_GFX

1001Remove 3V3MISC by FAE Nelson suggesLon

FAEPlease use +3V_GFX to instead 3V3MISC power rail
R500
EV-D@45.3K/F_4

+3V_GFX

[MIOB]

VGPU_PSI

R100

EV@10K/F_4

VGA_OVT#

R512

EV@10K/F_4

JTAG_TMS

R593

*EV@10K/F_4

JTAG_TDI

R578

*EV@10K/F_4

GPIO12_ACIN

R142

EV@10K/F_4

GPU_ALERT#

R513

EV@10K/F_4

JTAG_TCK

R594

*EV@10K/F_4

JTAG_TRST#

R579

EV@10K/F_4

R61
*EV-D@4.99K/F_4

R58
EV-D@4.99K/F_4

R72
EV-D@10K/F_4

R69
*EV-D@10K/F_4

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

R52
EV-D@4.99K/F_4

ROM_SI
ROM_SO
ROM_SCLK
R64
*EV-D@15K/F_4

R502
*EV-D@10K/F_4

R50
*EV-D@4.99K/F_4

R51
EV-D@45.3K/F_4

R80
*EV-D@34.8K/F_4

R86
EV-D@15K/F_4

R53
*EV-D@34.8K/F_4

R65
EV-D@4.99K/F_4

R497
*EV-D@10K/F_4

R496
EV-D@45.3K/F_4

0817FB_CLAMP have PD, EC programing to avoid leakage

0928 FAE NelsonAdd a MOS to avoid power leakage issue
1

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#

AM10
AP11
AM11
AP12
AN11
R7
R6

R118
R119

EV@2.2K_4
EV@2.2K_4

N13P_SCL
N13P_SDA

R121
R120

EV@2.2K_4
EV@2.2K_4

R2
DGPU_EDIDCLK
DGPU_EDIDDATA R3
GFx_SCL
GFx_SDA

JTAG_TCK
JTAG_TMS [MISC_GPIO/I2C/JTAG/THER]
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA

T4
T3

I2CS_SCL
I2CS_SDA

K4
K3

THERMDP
THERMDN

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1

R90

EV@0/J_4

EC_FB_CLAMP

A.ROM_SI - 10K pull down

B.ROM_SO - 10K pull down
F.STRAP 3 - 10k pull down
MicronMT41K256M16HA-107G:E (QPN = AKD5PGSTL05)
strap= 0xD =(0x1101)
STRAP 3&2&0 =10K Pull high
STRAP 1= 10K Pull down

pin 2 connect to +3V_GFX power rail

[17,20,34]

Q14
EV@2N7002K

+3V_GFX
R127
LCD_BL_PWM
LCD_VCC
LCD_BLEN
RSVD
3DVision
VGA_OVT#
GPU_ALERT#

EV@0/J_4

FB_CLAMP_REQ#_R

R111

VGPU_PWMVID

GPIO12_ACIN
VGPU_PSI
HPD_A
HPD_C
FRM_LCK
HPD_D
HPD_E
HPD_F or HDP_B

VGPU_PSI

EV@10K/F_4

[43]

FB_CLAMP_TGL_REQ#

Q13
*EV@2N7002K

TP63
TP65
TP67
TP66
TP64

N14M-GE device ID is 0x1140

N14M-GE is use binary strap setting

N14P-GT device ID=0x0FE4

1.ROM_SCLK =15K pull down
2.STRAP2= 25k pull down
3.STRAP4=45K pull down

FB_CLAMP_MON

A.ROM_SI - Memeory strap

B.ROM_SO - 5K pull high
D.STRAP 0 - 45k pull high
E.STRAP 1 GV2- 45K pull down
GT - 5K pull down
F.STRAP 3 - 5k pull down
C2.For N14P-GV2+SDDR3 sku
N14P-GV2 QS device ID=0x1292 'This is QS device ID
1.ROM_SCLK =5K pull high
2.STRAP2= 15k pull down
3.STRAP4=45 pull down 'For N14P-GV2 QS

R101

[34]

0928 FAE NelsonPlease add 10k pull up to +3V

on FB_CLAMP_REQ# signal also

0816 EC programing GPI

*EV@10K/F_4

[43]

+3V
+3V_GFX

RSVD
RSVD

PSI stuff 10k at GPU side ready, remove power page of pu 10k
GPIO20/21 available on N14P-GV2

R3
40.2K

N14M-GE/GL

NC

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

J2
J7
J6
J5
J3

EV-D@40.2K/F_4 J1

R501

ROM_SCLK
ROM_CS_N
ROM_SI
ROM_SO

[MISC2_ROM]

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

BUFRST_N
CEC

+3V_GFX

Q47

ROM_SI
ROM_SO

L2
L3

GPIO12 HW throttle
over power protect
0817 CEC is NC for GK107

2
GPU_ALERT#

+3V_GFX

PEGX_RST# [16]

PEGX_RST#

[9,34]

GPIO9 for ADPS circuit to infrom EC

NV dGPU VPS Alert

*EV@MC74VHC1G08DFT2G

GPU_THAL#

2ND_MBCLK

Mfr. PN

Freq.

GPU

AKD5PGSTL05

MT41K256M16HA-107G:E

900MHz

N14P-GT1 & GV2

Hynix

0110

AKD5MGWTW17

900MHz

N14P-GT

H5TQ2G63DFR-11C

R136
EV@10K/F_4

GFx_SCL

Quanta Computer Inc.

[43]
[9,34]

0815 RSVD VGPU TALERT#

to throttle GPU power

2ND_MBDATA

EC/S5

0816 dGPU_ALT# = EC control

1

R128
EV@10K/F_4

Q18

U14
EV@0/J_4

*EV@0_4

0816 dGPU_OTP# = EC control

Q PN

0001

4
R189

R786

Strap

EV@0/J_4

*EV@0_4

Vender
Micron

+3V_GFX

[34]

GPIO12 AC detect
AC high
DC low

[34]

Q50
EV@2N7002K

1
R194
R516

dGPU_OPP#

Q16
EV@2N7002K

+3V_GFX
dGPU_ALT#

1001Remove 3V3MISC by FAE Nelson suggesLon

FAEPlease use +3V_GFX to instead 3V3MISC power rail

0816 dGPU_OPP# = EC control

GPIO12_ACIN

EV@N14P_GV2

dGPU_OTP# [34]

EV@2N7002K
2

VGA_OVT#

ROM_SCLK

SMBus (VGA)

MULTISTRAP_REF_GND

R3
GPIO8 VGA thrmtrip# => inform EC
over temperature protect

H4
H6
H5
H7

N14x others

PROJECT : ZQK

GFx_SDA

VGA/+3V_GFX

EV@2N7002DW
5

Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

DGPU 4/5 (MIO/GPIO)

6

Sheet
8

19

of

46

20

PLACE UNDER GPU BALLS

+VGPU_CORE
U35G

for meet Power down sequence

for +3V_GFX
+VGPU_CORE

D3

EV@RB500V-40

GND_OPT_1

+3V_GFX
+1.5V_GFX

D2

GND_OPT_2

*EV@RB500V-40

C90
C98
C91
C108
C97
C116
C107
C115

C596
EV@330u/2V_7343

Power request ESR

x 8 population x 4

EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
*EV@0.1u/10V_4
*EV@0.1u/10V_4
*EV@0.1u/10V_4
*EV@0.1u/10V_4

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1378MILS
A

PLACE UNDER GPU BALLS

+VGPU_CORE

4.7uF
C102

x 15 population x10

C100

C117

C129

EV@4.7u/6.3V_6

C103

C88

EV@4.7u/6.3V_6

EV@4.7u/6.3V_6

C69

EV@4.7u/6.3V_6

EV@4.7u/6.3V_6

EV@4.7u/6.3V_6

EV@4.7u/6.3V_6

+VGPU_CORE

C83

C104

C113

EV@4.7u/6.3V_6

C121

C101

*EV@4.7u/6.3V_6

C122

C133

*EV@4.7u/6.3V_6

EV@4.7u/6.3V_6

*EV@4.7u/6.3V_6

*EV@4.7u/6.3V_6

*EV@4.7u/6.3V_6

PLACE NEAR TO GPU BALLS

47u x1 22u x7
4.7u x6
330u x1
stuff x 1 stuff x 5 RSVD by DG

+VGPU_CORE

C617
C128

C599

C597

EV@47u/6.3V_8
EV@330u/2.5V_3528

C132

+VGPU_CORE

C111

EV@4.7u/25V_8

C112

C588

EV@4.7u/25V_8

EV@22u/6.3V_8

EV@4.7u/25V_8

EV@4.7u/25V_8

EV@4.7u/25V_8

0817 RSVD more NVVDD caps by NV DG

C92

C93

C74

C73

C592

C124

C127

*EV@22u/6.3V_8

*EV@22u/6.3V_8

*EV@22u/6.3V_8

*EV@22u/6.3V_8

*EV@22u/6.3V_8

*EV@22u/6.3V_8

*EV@4.7u/25V_8

DGPU_PGOK-1
+3V_GFX

+1.05V_GFX

DGPU_POK2

R187

R140
EV@4.7K/J_4

+3V

EV@4.7K/J_4
C175
*EV@1000P/50V_4

R161
EV@4.7K/J_4
DGPU_POK_Q

+1.5V_GFX

DGPU_POK4

R167

DGPU_PWROK [10]

C146
*EV@1000P/50V_4

R147
EV@100K/F_4

2
R176
*EV@0_4

EV@4.7K/J_4

C16

Q20
EV@MMBT3904-7-F

Q19
EV@MMBT3904-7-F

C123
EV@1000P/50V_4

Q15
EV@DTC144EUA

W32

0814 POWER GD

20120914: H/W Add for HWPG_1.5VGFX

20121018: Circuit combination

+3V

+3V_GFX

+3V

R59
EV@4.7K/J_4

0816 GC6 need system 3V to control FBVDDQ

5
2

VGPU_PWRGD

DGPU_POK_Q

R43
EV@4.7K/J_4
HWPG_1.5VGFX

C87
*EV@0.1u/10V_4
HWPG_1.5VGFX

+3V

1.05V_GFX_EN [42]

Q5
EV@DTC144EUA

R49
EV@100K/F_4

PU at page 43

connect to EC

EV@N14P_GV2

20120911: D6002 no stuff when GC6 support.

U12

C82

EV@4.7u/6.3V_6

EV@N14P_GV2

0.1uF
+

[GPU VDD]

U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

+VGPU_CORE

XVDD_001
XVDD_002
XVDD_003
XVDD_004
XVDD_005
XVDD_006
XVDD_007
XVDD_008
XVDD_009
XVDD_010
XVDD_011
XVDD_012
XVDD_013
XVDD_014
XVDD_015
XVDD_016
XVDD_017
XVDD_018
XVDD_019
XVDD_020
XVDD_021
XVDD_022
XVDD_023
XVDD_024
XVDD_025
XVDD_026
XVDD_027
XVDD_028
XVDD_029
XVDD_030
XVDD_031
XVDD_032
XVDD_033
XVDD_034
XVDD_035
XVDD_036
XVDD_037
XVDD_038

[GPU GND]

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11

VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020
VDD_021
VDD_022
VDD_023
VDD_024
VDD_025
VDD_026
VDD_027
VDD_028
VDD_029
VDD_030
VDD_031
VDD_032
VDD_033
VDD_034
VDD_035
VDD_036
VDD_037
VDD_038
VDD_039
VDD_040
VDD_041
VDD_042
VDD_043
VDD_044
VDD_045
VDD_046
VDD_047
VDD_048
VDD_049
VDD_050
VDD_051
VDD_052
VDD_053
VDD_054
VDD_055
VDD_056
VDD_057
VDD_058
VDD_059
VDD_060
VDD_061
VDD_062
VDD_063
VDD_064
VDD_065
VDD_066
VDD_067
VDD_068
VDD_069
VDD_070
VDD_071
VDD_072

GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200

U35F

AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y18
Y17
Y20
Y22

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100

+VGPU_CORE

A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7

EV@MC74VHC1G08DFT2G

C49
EV@1000p/50V_4

C71
*EV@0_4

EV@0.1u/10V_4

R103

EC_FB_CLAMP

[42] FBVDDQ_EN

[17,19,34]

R82

EV@0/J_4

VGPU_PWRGD [43]

R87

*EV@0_4

DGPU_VRON

Quanta Computer Inc.

[10,43]

PROJECT : ZQK

R83
EV@100K/F_4

VGPU_PWRGD_R

U11

EV@74AHC1G32GW

C70

*EV@0.1u/10V_4
Size

Document Number

Rev
1A

DGPU 5/5 (Power/Ground)

Date:
1

Monday, January 07, 2013

7

Sheet

20
8

of

46

21

Micron 900MHz 2G AKD5LZWTW02

[17] VMA_DQ[63..0]
[17] VMA_DM[7..0]
[17] VMA_WDQS[7..0]
[17] VMA_RDQS[7..0]

CHANNEL A: 1024MB DDR3

VRAM1

[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

[17] FBA_CMD12
[17] FBA_CMD27
[17] FBA_CMD26

[17] VMA_CLK0
[17] VMA_CLK0#
[17] FBA_CMD3

[17]
[17]
[17]
[17]
[17]

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

[17] FBA_CMD5

VREFC_VMA1
VREFD_VMA1

M8
H1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_CMD12
FBA_CMD27
FBA_CMD26

M2
N8
M3

VMA_CLK0
VMA_CLK0#
FBA_CMD3

J7
K7
K9

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

K1
L2
J3
K3
L3

VMA_WDQS0
VMA_RDQS0

F3
G3

VMA_DM0
VMA_DM1

E7
D3

VMA_WDQS1
VMA_RDQS1

C7
B7

FBA_CMD5

T2
L8

VMA_ZQ1

BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSL
DML
DMU
DQSU
DQSU

RESET
ZQ

R73
EV@243/F_4
J1
L1
J9
L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

Should be 240
Ohms +-1%

VRAM3

VREFCA
VREFDQ

NC#J1
NC#L1
NC#J9
NC#L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

VMA_DQ2
VMA_DQ7
VMA_DQ1
VMA_DQ4
VMA_DQ3
VMA_DQ6
VMA_DQ0
VMA_DQ5

VREFC_VMA1
VREFD_VMA1

M8
H1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

D7
C3
C8
C2
A7
A2
B8
A3

VMA_DQ8
VMA_DQ12
VMA_DQ11
VMA_DQ14
VMA_DQ9
VMA_DQ13
VMA_DQ10
VMA_DQ15

FBA_CMD12
FBA_CMD27
FBA_CMD26

M2
N8
M3

VMA_CLK0
VMA_CLK0#
FBA_CMD3

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

K1
L2
J3
K3
L3

VMA_WDQS2
VMA_RDQS2

F3
G3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMA_DM2
VMA_DM3

E7
D3

VMA_WDQS3
VMA_RDQS3

C7
B7

FBA_CMD5

T2

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_GFX

BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE

DML
DMU
DQSU
DQSU

RESET
ZQ

R498
EV@243/F_4
J1
L1
J9
L9

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

NC#J1
NC#L1
NC#J9
NC#L9

VMA_DQ30
VMA_DQ24
VMA_DQ28
VMA_DQ25
VMA_DQ29
VMA_DQ27
VMA_DQ31
VMA_DQ26

B2
D9
G7
K2
K8
N1
N9
R1
R9

[17] VMA_CLK1
[17] VMA_CLK1#
[17] FBA_CMD19

+1.5V_GFX
A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSL

VMA_DQ20
VMA_DQ16
VMA_DQ21
VMA_DQ18
VMA_DQ23
VMA_DQ17
VMA_DQ22
VMA_DQ19

D7
C3
C8
C2
A7
A2
B8
A3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

Should be 240
Ohms +-1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

E3
F7
F2
F8
H3
H8
G2
H7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

L8

VMA_ZQ2

VRAM2

VREFCA
VREFDQ

[17] FBA_CMD18
[17] FBA_CMD16

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

M8
H1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_CMD12
FBA_CMD27
FBA_CMD26

M2
N8
M3

VMA_CLK1
VMA_CLK1#
FBA_CMD19

J7
K7
K9

FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13

K1
L2
J3
K3
L3

VMA_WDQS4
VMA_RDQS4

F3
G3

VMA_DM4
VMA_DM5

E7
D3

VMA_WDQS5
VMA_RDQS5

C7
B7

FBA_CMD5

T2
L8

VMA_ZQ3

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

+1.5V_GFX

BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSL
DML
DMU
DQSU
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

VMA_DQ36
VMA_DQ34
VMA_DQ38
VMA_DQ35
VMA_DQ39
VMA_DQ32
VMA_DQ37
VMA_DQ33

D7
C3
C8
C2
A7
A2
B8
A3

VMA_DQ47
VMA_DQ40
VMA_DQ46
VMA_DQ43
VMA_DQ45
VMA_DQ42
VMA_DQ44
VMA_DQ41

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_CMD12
FBA_CMD27
FBA_CMD26

M2
N8
M3

VMA_CLK1
VMA_CLK1#
FBA_CMD19

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13

K1
L2
J3
K3
L3

VMA_WDQS7
VMA_RDQS7

F3
G3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMA_DM7
VMA_DM6

E7
D3

VMA_WDQS6
VMA_RDQS6

C7
B7

FBA_CMD5

T2

+1.5V_GFX

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

M8
H1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VREFC_VMA3
VREFD_VMA3

VMA_ZQ4

L8

+1.5V_GFX

[17] FBA_CMD17

R85
EV@1.33K/F_4

FBA_CMD17

TP11

FBA_CMD1

TP6

VREFCA
VREFDQ

BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSL
DML
DMU
DQSU
DQSU

RESET
ZQ

R534
EV@243/F_4
J1
L1
J9
L9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

Should be 240
Ohms +-1%

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

[17] FBA_CMD1
VMA_CLK0

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

R533
EV@243/F_4
J1
L1
J9
L9

VRAM4

VREFCA
VREFDQ

Should be 240
Ohms +-1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

VREFC_VMA3
VREFD_VMA3

NC#J1
NC#L1
NC#J9
NC#L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

VMA_DQ61
VMA_DQ59
VMA_DQ63
VMA_DQ58
VMA_DQ60
VMA_DQ57
VMA_DQ62
VMA_DQ56

D7
C3
C8
C2
A7
A2
B8
A3

VMA_DQ55
VMA_DQ49
VMA_DQ54
VMA_DQ48
VMA_DQ52
VMA_DQ50
VMA_DQ53
VMA_DQ51

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

+1.5V_GFX

+1.5V_GFX

10/14 modify

R60
EV@1.33K/F_4

R156
EV@1.33K/F_4

R171
EV@1.33K/F_4

VMA_CLK1

R489
EV@162/F_4
VREFC_VMA1

VREFD_VMA1

R542
EV@162/F_4

VMA_CLK0#

Fermi : Change to 160 ohm

1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

VREFC_VMA3

VMA_CLK1#

C75
R88

R48
EV@0.1u/10V_4

EV@1.33K/F_4

C42
EV@0.1u/10V_4

R160

Fermi : Change to 160 ohm

1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

EV@1.33K/F_4

VREFD_VMA3

C135
EV@0.1u/10V_4

EV@1.33K/F_4

R175

C162
EV@0.1u/10V_4

EV@1.33K/F_4

+1.5V_GFX
+1.5V_GFX

+1.5V_GFX
+1.5V_GFX
C615
C541
C573
C542

EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4

C177
C613
C614
C24
C233
C29

EV@10u/6.3V_6
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4

EV@10u/6.3V_6

C572

C27
C550
C580

EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4

C533

EV@10u/6.3V_6

C84

EV@10u/6.3V_6
EV@10u/6.3V_6

EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4

EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4

C540

C25
C556
C170
C232

C21
C234
C547

C593
C552
C575

EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4

C26
C577

EV@10u/6.3V_6

+1.5V_GFX

C231

EV@0.1u/10V_4
EV@0.1u/10V_4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

NN13P-LP DDR3 VRAM 1/2

Date:
5

Monday, January 07, 2013

Sheet
1

21

of

46

[17]
[17]
[17]
[17]

VMC_DQ[63..0]
VMC_DM[7..0]
VMC_WDQS[7..0]
VMC_RDQS[7..0]

[17]
D
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

[17]
[17]
[17]

FBC_CMD12
FBC_CMD27
FBC_CMD26

[17]
[17]
[17]

VMC_CLK0
VMC_CLK0#
FBC_CMD3

[17]
C
[17]
[17]
[17]
[17]

[17]

FBC_CMD2
FBC_CMD0
FBC_CMD30
FBC_CMD15
FBC_CMD13

FBC_CMD5

M8
H1

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBC_CMD12
FBC_CMD27
FBC_CMD26

M2
N8
M3

VMC_CLK0
VMC_CLK0#
FBC_CMD3

J7
K7
K9

FBC_CMD2
FBC_CMD0
FBC_CMD30
FBC_CMD15
FBC_CMD13

K1
L2
J3
K3
L3

VMC_WDQS0
VMC_RDQS0

F3
G3

VMC_DM0
VMC_DM1

E7
D3

VMC_WDQS1
VMC_RDQS1

C7
B7

FBC_CMD5

T2
L8

VMC_ZQ1

VRAM6

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSL
DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSU
DQSU

RESET
ZQ

Should be 240
Ohms +-1%

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R94
EV@243/F_4
J1
L1
J9
L9

NC#J1
NC#L1
NC#J9
NC#L9

E3
F7
F2
F8
H3
H8
G2
H7

VMC_DQ3
VMC_DQ4
VMC_DQ0
VMC_DQ6
VMC_DQ1
VMC_DQ7
VMC_DQ2
VMC_DQ5

VREFC_VMC1
VREFD_VMC1

M8
H1

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

D7
C3
C8
C2
A7
A2
B8
A3

VMC_DQ8
VMC_DQ12
VMC_DQ9
VMC_DQ14
VMC_DQ10
VMC_DQ13
VMC_DQ11
VMC_DQ15

FBC_CMD12
FBC_CMD27
FBC_CMD26

M2
N8
M3

VMC_CLK0
VMC_CLK0#
FBC_CMD3

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBC_CMD2
FBC_CMD0
FBC_CMD30
FBC_CMD15
FBC_CMD13

K1
L2
J3
K3
L3

VMC_WDQS3
VMC_RDQS3

F3
G3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMC_DM3
VMC_DM2

E7
D3

VMC_WDQS2
VMC_RDQS2

C7
B7

FBC_CMD5

T2

B2
D9
G7
K2
K8
N1
N9
R1
R9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5V_GFX

VMC_ZQ2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSL
DML
DMU
DQSU
DQSU

RESET

L8

ZQ

Should be 240
Ohms +-1%
R598
EV@243/F_4
J1
L1
J9
L9

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

VRAM7

VREFCA
VREFDQ

BA0
BA1
BA2

NC#J1
NC#L1
NC#J9
NC#L9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

VMC_DQ27
VMC_DQ31
VMC_DQ25
VMC_DQ28
VMC_DQ24
VMC_DQ30
VMC_DQ26
VMC_DQ29

D7
C3
C8
C2
A7
A2
B8
A3

VMC_DQ17
VMC_DQ22
VMC_DQ18
VMC_DQ23
VMC_DQ19
VMC_DQ21
VMC_DQ16
VMC_DQ20

B2
D9
G7
K2
K8
N1
N9
R1
R9

[17] VMC_CLK1
[17] VMC_CLK1#
[17] FBC_CMD19

+1.5V_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

[17] FBC_CMD18
[17] FBC_CMD16

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VREFC_VMC3
VREFD_VMC3

M8
H1

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBC_CMD12
FBC_CMD27
FBC_CMD26

M2
N8
M3

VMC_CLK1
VMC_CLK1#
FBC_CMD19

J7
K7
K9

FBC_CMD18
FBC_CMD16
FBC_CMD30
FBC_CMD15
FBC_CMD13

K1
L2
J3
K3
L3

VMC_WDQS4
VMC_RDQS4

F3
G3

VMC_DM4
VMC_DM5

E7
D3

VMC_WDQS5
VMC_RDQS5

C7
B7

FBC_CMD5

T2

VMC_ZQ3

+1.5V_GFX

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSL
DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSU
DQSU

RESET
ZQ

J1
L1
J9
L9

NC#J1
NC#L1
NC#J9
NC#L9

VMC_DQ38
VMC_DQ32
VMC_DQ36
VMC_DQ35
VMC_DQ39
VMC_DQ34
VMC_DQ37
VMC_DQ33

VREFC_VMC3
VREFD_VMC3

M8
H1

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

D7
C3
C8
C2
A7
A2
B8
A3

VMC_DQ44
VMC_DQ40
VMC_DQ46
VMC_DQ42
VMC_DQ45
VMC_DQ43
VMC_DQ47
VMC_DQ41

FBC_CMD12
FBC_CMD27
FBC_CMD26

M2
N8
M3

VMC_CLK1
VMC_CLK1#
FBC_CMD19

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBC_CMD18
FBC_CMD16
FBC_CMD30
FBC_CMD15
FBC_CMD13

K1
L2
J3
K3
L3

VMC_WDQS7
VMC_RDQS7

F3
G3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VMC_DM7
VMC_DM6

E7
D3

VMC_WDQS6
VMC_RDQS6

C7
B7

FBC_CMD5

T2

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R446
EV@243/F_4

E3
F7
F2
F8
H3
H8
G2
H7

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

Should be 240
Ohms +-1%

B1
B9
D1
D8
E2
E8
F9
G1
G9

VMC_ZQ4

L8

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

DQSL
DQSL
DML
DMU

VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

DQSU
DQSU

RESET
ZQ

Should be 240
Ohms +-1%

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

R641
EV@243/F_4
J1
L1
J9
L9

NC#J1
NC#L1
NC#J9
NC#L9

+1.5V_GFX

R33
EV@1.33K/F_4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

VMC_DQ60
VMC_DQ57
VMC_DQ63
VMC_DQ58
VMC_DQ61
VMC_DQ59
VMC_DQ62
VMC_DQ56

D7
C3
C8
C2
A7
A2
B8
A3

VMC_DQ52
VMC_DQ49
VMC_DQ55
VMC_DQ51
VMC_DQ54
VMC_DQ50
VMC_DQ53
VMC_DQ48

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

+1.5V_GFX

R519
EV@1.33K/F_4

+1.5V_GFX

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

VMC_CLK1

R245
EV@162/F_4

22

VRAM8

VREFCA
VREFDQ

L8

96-BALL
SDRAM DDR3
EV@VRAM _DDR3

VMC_CLK0

HYNIX 900MHz 1G AKD5LZWTW02

HYNIX 900MHz 2G AKD5MGWTW16

CHANNEL B: 1024MB DDR3

VRAM5
VREFC_VMC1
VREFD_VMC1

+1.5V_GFX

R503
EV@1.33K/F_4

R251
EV@1.33K/F_4

R18
EV@162/F_4
VREFC_VMC1

VREFD_VMC1

VREFC_VMC3

VMC_CLK0#

VREFD_VMC3

VMC_CLK1#

Fermi : Change to 160 ohm

1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

R588

C834
EV@0.1u/10V_4

EV@1.33K/F_4

R31

Fermi : Change to 160 ohm

1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

C282
EV@0.1u/10V_4

EV@1.33K/F_4

R451

C829
EV@0.1u/10V_4

EV@1.33K/F_4

C828
EV@0.1u/10V_4

R332
EV@1.33K/F_4

+1.5V_GFX
C19
C825

+1.5V_GFX
C795
C833
C827
C826

EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4

EV@10u/6.3V_6
EV@10u/6.3V_6

C22

EV@1u/10V_4

C839
C56
C830

EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4

+1.5V_GFX
C836
C230
C229
C831
C819
C486
C837
C832

[17]

+1.5V_GFX
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4
EV@0.1u/10V_4

C835
C838
C319
C817
C62
C471
C472
C487

[17]

EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4
EV@1u/10V_4

FBC_CMD17
FBC_CMD1

FBC_CMD17

TP113

FBC_CMD1

TP110

Quanta Computer Inc.

+1.5VSUS
+

C840

PROJECT : ZQK

*EV@330u/2.5V_3528

1107
Reserve 330uF for 8VRAM power routing

Size

Rev
1A

N13P-LP DDR3 VRAM 2/2

Date:

Document Number
Sheet

Monday, January 07, 2013

1

22

of

45

Layout Notes:
Place near Pin13 and Pin14

mini DP ML (DPP)

23

+3V
R805

SW@0/J_6

+5V
C534
SW@10u/6.3V_6

C527
SW@0.1u/10V_4

C23
SW@0.1u/10V_4

*10K/J_4
*10K/J_4

USB2_SEL

Q45
5
3

[7] DP_TXP2
[7] DP_TXN2

4
+3V

*10K/J_4
*10K/J_4

[9] USB30_TX3+
[9] USB30_TX3-

USB3_SEL

DP_TXP2_C
DP_TXN2_C

48
47

SW@0.1u/10V_4
SW@0.1u/10V_4

USB30_TX3+_C
USB30_TX3-_C

44
43

C544
C543

0.1u/10V_4
0.1u/10V_4

DP_TXP3_C
DP_TXN3_C

46
45

[7] DP_TXP3
[7] DP_TXN3

SW@2N7002DW
C821
1u/6.3V_4

R793
SW@100K/F_4

+3V
R67
R54

*10K/J_4
*10K/J_4

42
41

[9] USB30_RX3+
[9] USB30_RX3-

USB2_MUX_DIS

USB3_SEL

Q46
5

SW@10K/J_4

R835

2
R779

SW@0_4

*10K/J_4
*10K/J_4

USB3_MUX_DIS

SW@0/J_4
SW@0/J_4

35
36

FCH_USB2_P0_R
FCH_USB2_N0_R

37
38
12

USB2_SEL

C0P
C0N

32
34
LB_CHARGE_OFF
SW@0/J_4 LB_CHG_DELAY1#
TP2

ESD Protect (EMC)

R788

[7] DP_HPD_Q

17

DP_HPD_OUT

SW@0/J_4

21
22
23

A1P
A1N

5
6

INT_DPTX3P
INT_DPTX3N

+5V

C1P
C1N

Q39
3

SS_SEL_IN

SS_SEL
ADM
ADP

BDP
BDM

10
11

MODE_LED
HPD_IN

HS_SEL_IN

HS_SEL

AUX_N

HS_OE#_IN
SS_OE#_IN/NC

HS_SEL_OUT
SS_SEL_OUT

HS_OE#_OUT
SS_OE#_OUT

CONFIG_2
CONFIG_1

CHRG_OFF
CHRG_DELAY
SLEEP

CONFIG_1_PU
CONFIG_2_PU
SYS_COM_REQ

to DP_HPD_C

15
16

DP_HPD_C

18

DP_AUXN_R R456

R781

+3V
+3V

SW@10K/J_4
DP_AUXN

SW@100K/J_4

PAD

10
9
7
6

10
9

INT_DPTX2N
INT_DPTX2P

7
6

INT_DPTX3P
INT_DPTX3N

56
55
54
51
50
49
24

1
2
GND_3/8
4
5

19
20

USB2_SEL
USB3_SEL

28
29

CONFIG_2P
CONFIG_1P

26
27

CONFIG_PU
Dongle_POWEREN#

25

R780

30
31

Connect to HS_SEL_IN(pin12)
Connect to SS_SEL_IN(pin7)
R32
R42

+3V

Q9
SW@AO3409

SW@3.3K/J_4
SW@3.3K/J_4
2

CONFIG_PU

SW@0/J_4

SYS_COM_REQ [8]

HPD_OUT
RST
TEST

DP_HPD

100/J_4

R21
1M/J_4

CONFIG_2CNN
CONFIG_1CNN

net name change

CDP
CDM

R20

2N7002K
1
*0/J_4

2
R450

U2
1
2
3
4
5

INT_DPTX3P
INT_DPTX3N

INT_DPTX2P
INT_DPTX2N

B1P
B1N

NC6
NC5
NC4
NC3
NC2
NC1
NC0

57

INT_DPTX2N
INT_DPTX2P

2
3

R789
SW@100K/F_4

9
8

USB2_MUX_DIS
USB3_MUX_DIS

SW@2N7002DW

R777

A0P
A0N

CONFIG_PU

Q68
SW@2N7002DW
4

R68
R55

R56
R57

[9] USBP2+
[9] USBP2-

SW@5.1M/J_4

[9,26] SMB_PCH_CLK

CONFIG_1P
CONFIG_2P
4
+3V

R791
SW@100K/F_4

CONFIG_2P

DP HPD (DPP)

B0P
B0N

GND
GND
GND

R790

U7

SYS_COM_REQ
R792
SW@10K/J_4

0.1u/10V_4
0.1u/10V_4

C40
C39

C17
SW@0.1u/10V_4

SW@0_4 6

R778

[9,26] SMB_PCH_DAT

R447
R24

C546
C545

C528
SW@0.1u/10V_4

R66

+3V

Q10
SW@AO3409

CONFIG_1P

C15
SW@0.1u/10V_4

C16
SW@0.1u/10V_4

SW@10K/J_4

53
39
33

R787

C529
SW@0.1u/10V_4

VCC
VCC
VCC/NC
VCC/NC

R23
R22

VCC
VCC

R75
SW@1M/J_4

14
13

+3V
R41
SW@1M/J_4

52
40
4
1

SEL/OE# polarity Control

SW@47K/J_4

TP3
C38
SW@2200p/50V_4

SW@(X)HD3SS2521_NB

MINI DP connector (DPP)

*RClamp0524P

CN4
CONFIG_1P

U29
1
2
3
4
5

DP_AUXN
DP_AUXP
CONFIG_2CNN
CONFIG_1CNN

1
2
GND_3/8
4
5

10
9

10
9

DP_AUXN
DP_AUXP

7
6

CONFIG_2CNN
CONFIG_1CNN

R774
INT_DPTX0N
INT_DPTX0P

4
1

C8
C7

0.1u/10V_4 INT_DPTX0P
0.1u/10V_4 INT_DPTX0N

C9
C10

0.1u/10V_4 INT_DPTX1P
0.1u/10V_4 INT_DPTX1N

1
2
3
4
5

1
2
GND_3/8
4
5

Layout Notes:
Place decoupling CAPs close to Connector

3
2

10
9
7
6

10
9

INT_DPTX0P
INT_DPTX0N

7
6

INT_DPTX1P
INT_DPTX1N

R776

CONFIG_2CNN

R785

NSW@5.1M/J_4

DP_HPD_Q

R783

NSW@0_4

LB_PWR_RTN

R784

NSW@1M/J_4

DP_HPD
INT_DPTX0P_R
CONFIG_1CNN
INT_DPTX0N_R
CONFIG_2CNN

3
2

INT_DPTX0N_R
INT_DPTX0P_R

DP_HPD_C

0/J_4

DP_TXP2_C
DP_TXN2_C

R468
R467

NSW@0_4
NSW@0_4

DP_TXP2_CR
DP_TXN2_CR

R460
R459

NSW@0_4 INT_DPTX2P
NSW@0_4 INT_DPTX2N

DP_TXP3_C
DP_TXN3_C

R466
R465

NSW@0_4
NSW@0_4

DP_TXP3_CR
DP_TXN3_CR

R458
R457

NSW@0_4 INT_DPTX3P
NSW@0_4 INT_DPTX3N

INT_DPTX1P_R
INT_DPTX3P
INT_DPTX1N_R
INT_DPTX3N

L35
INT_DPTX1N
INT_DPTX1P

4
1

4
1

3
2

3
2

INT_DPTX1N_R
INT_DPTX1P_R

*DLW21HN900SQ2L_C
R775
0/J_4

*RClamp0524P

4
1

FCH_USB2_N0_R

C813 SW@2200p/50V_4

CONFIG_2CNN_C

C815 SW@2200p/50V_4

+3V

INT_DPTX2P
DP_AUXP
INT_DPTX2N
DP_AUXN

CONFIG_2CNN

C814 SW@2200p/50V_4

CONFIG_1CNN_C

C816 SW@2200p/50V_4

LB_PWR_RTN
LB_PWR_CNN

Q69
3

FCH_USB2_P0_R

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

CONFIG_1CNN

NSW@0_4

*DLW21HN900SQ2L_C
R773
0/J_4

U1

[7] DP_TXP1
[7] DP_TXN1

R782

L34

7
6

*RClamp0524P

[7] DP_TXP0
[7] DP_TXN0

0/J_4

CONFIG_1CNN

Close to DP connector

IN

OUT
GND

1
2

NSW@AP2331SA-7

C522
0.1u/10V_4

C822
10u/6.3V_6

C823
0.1u/10V_4

C824
10u/6.3V_6

GND
HPD
LANE0_P
CONFIG1
LANE0_N
CONFIG2
GND
GND
LANE1_P
LANE3_P
LANE1_N
LANE3_N
GND
GND
LANE2_P
AUX_CH_P
LANE2_N
AUX_CH_N
GND
DP_PWR

SHELL1
SHELL2
SHELL3
SHELL4

21
22
23
24
B

mDP

30mil

500mA (Max.)

+5V

LB_PWR_RTN
+5V

6
Q48
SW@FDMC4435BZ

D35
SMAJ20A

R34
SW@100K/J_4

SW@2N7002DW

DDPC_CTRLCLK [7]

LB_PWR_RTN_M
R499

Q7
SW@FDMC4435BZ
LB_PWR_CNN_M

+3V

R62
1M/F_4

R528
SW@20K/J_4

+3V
+3V

DP_AUXP

R800
SW@2K/F_4
C578
SW@0.1u/10V_4

Q42
5

*100K/F_4

C555 0.1u/10V_4

[7] INT_DP_AUXDP

C551 0.1u/10V_4

INT_DP_AUXDN_C 4

2
2
2

R479

1
Q53
SW@ME2N7002E
R541
SW@100K/F_4

*100K/F_4
2N7002DW

DP_CAD

R488
SW@10K/F_4

1
2
3

Q12
SW@ME2N7002E

LB_CHARGE_OFF

SW@NL17SZ04DFT2G

U36
SW@TC7SH08FU

Quanta Computer Inc.

Behavior

Low

DP signal (AC couple)

High

TMDS signal (DC couple)

SW@2K/F_4

Dongle_POWEREN#

PROJECT : ZQK
Size

Document Number

Rev
1A

Mini DP
Date:

R801

LB_CHARGE_OFF

DP_AUX_EN

6
1

INT_DP_AUXDP_C 1

R799
SW@100K/F_4

U37
5

R490

C579 SW@0.1u/10V_4

+3V
[7] INT_DP_AUXDN

R71
SW@20K/F_4

+3V

2N7002DW

CONFIG_1P

R494
2.2K/J_4

100K/F_4

Q6
SW@FDMC4435BZ

*SW@100K/F_4

2N7002DW

R475

Q49
SW@FDMC4435BZ
3
2
1

Q43
5

D36
SMAJ20A

+3V

LB_PWR_RTN

1
2
3

DP_DDI_EN
DP_AUX_EN

3
2

R493
10K/F_4

1
2
3

R491
10K/F_4

LB_PWR_CNN

5
2

DP_AUXN

4
4

[7] DDPC_CTRLDAT

3
2
1

R476
NSW@100K/F_4

+3V

2.2K/J_4

Q44
Dongle_POWEREN#

Q41
R495

+3V

20121018
Follow Intel DG to exchange pin1/6 of Q41

mDP AUX (DPP)

Monday, January 07, 2013

1

Sheet

23

of

46

6
4

R244

0/J_4
R243

LCDVCC

IN

OUT

IN

GND

ON/OFF

GND

LCDVCC1

R583

C242

C248

C620

C630

*0.1u/10V_4

*2.2u/6.3V_6

0.1u/10V_4

0.01u/25V_4

22u/6.3V_8

R319

0/J_4

+3VPCU

R313
*100K_4

eDP
MAX 4 lane signals

R314
10K/J_4

TPL@0_6 TP_PWR

0.1u/10V_4
0.1u/10V_4

EDP_TXP2_C
EDP_TXN2_C

[2] EDP_TXP1
[2] EDP_TXN1

C264
C265

0.1u/10V_4
0.1u/10V_4

EDP_TXP1_C
EDP_TXN1_C

C266
C267

0.1u/10V_4
0.1u/10V_4

C268
C269

0.1u/10V_4
0.1u/10V_4

EDP_TXP0_C
EDP_TXN0_C
R305
100K/J_4
eDP_AUXP_C
eDP_AUXN_C
R306
100K/J_4
USBP8+_R
USBP8-_R

+3V
0/J_4

USBP3+_R
USBP3-_R
TP_GND

L18

3
1

[2] EDP_HPD

C262
C263

R241

CCD

2
4

*0/J_4
LVDS_BRIGHT
BL_ON
EDP_HPD

[2] EDP_TXP2
[2] EDP_TXN2

BL_ON

Q25
2N7002DW

R794

CCD_PWR

EDP_TXP3_C
EDP_TXN3_C

[2] EDP_AUXP
[2] EDP_AUXN

D10
RB500V-40

0_6

R311

0.1u/10V_4
0.1u/10V_4

[2] EDP_TXP0
[2] EDP_TXN0

LID#,EC intrnal PU

BL#
R312
100K/J_4

R295

+5V

C260
C261

[2] EDP_TXP3
[2] EDP_TXN3

LID# [31,34]

[7] INT_LVDS_BLON

+3V

[34] COLOR_ENG
Layout Notes:
Place decoupling CAPs close to Connector

R320
10K/J_4

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

LCDVCC

LCDVCC

C604

AP2821KTR-G1

+3V

LCD_VIN

0_6
0_6

0/J_8

eDP Backlight Control (LDS)

24

CN8
R316
R315

VIN

100K/J_4

eDP (LDS)

1st: AL002821000 (BCD)

2nd: AL003512000 (ANC)
U18

1u/6.3V_4

[7] INT_LVDS_DIGON

+3V

C227

4
1

[9] USBP8+
[9] USBP8-

EC_FPBACK# [34]

4
1

3
2

3
2

*DLW21HN900SQ2L_C
R233
0/J_4

Q24
DTC144EUA

R234

R309
TPL@0_6

G_6

eDP Power (LDS)

G_5

G_4

G_1

G_0

CVS5402M1RA-NH

TPL@0/J_4

L19

Touch Panel

4
1

[9] USBP3+
[9] USBP3-

4
1

3
2

3
2

Reserve for GND noise

TP_INT

*TPL@DLW21HN900SQ2L_C
R235
TPL@0/J_4

[9,10] BOARD_ID4

Inform BIOS that it is touch panel or not

C

CCD_PWR

From PCH

[7] INT_LVDS_BRIGHT

TP_PWR

C276

C272

C271

C275

*10p/50V_4

1000p/50V_4

4.7u/25V_8

1000p/50V_4

+3V

+3V_S5
R318

TPL@1000p/50V_4

+3V
D

R610
*TPL@10K/J_4

+3V_S5
C281
*0.1u/10V_4

R317
*100K/J_4

TP_INT_PCH

[10] TP_INT_PCH

R639
*TPL@10K/J_4

1001
Un-stu 0.1uF to prevent backlight
flicker issue when reduce brightness

1
Q59
TPL@2N7002K

C277

*TPL@10p/50V_4

0/J_4
LVDS_BRIGHT

C273

Touch Panel interrupt signal

1016Exchange Q59 pin 1 & 3 direction to prevent leakage

eDP Brightness Control (LDS)

D

VIN

Quanta Computer Inc.

+3V

PROJECT : ZQK
TP_INT

Size

Document Number

Rev
1A

eDP/CAMERA/LID
Date:

Monday, January 07, 2013

7

Sheet

24
8

of

46

HDMI Cost Reduced level shift (HDM)

HDMI connector (HDM)

INT_HDMITX1N_C
INT_HDMITX1P_C

C12
C11

0.1u/10V_4
0.1u/10V_4

INT_HDMITX0N_C
INT_HDMITX0P_C

C13
C14

0.1u/10V_4
0.1u/10V_4

INT_HDMICLK+_C
INT_HDMICLK-_C

Layout Notes:
Place decoupling CAPs close to Connector

INT_HDMITX2N_C
INT_HDMITX1P_C
INT_HDMITX1N_C
INT_HDMITX0P_C
INT_HDMITX0N_C
INT_HDMICLK+_C

R15

R14

R12

R13

R443

R444

HDMI_DDCCLK_MB
HDMI_DDCDATA_MB

INT_HDMICLK-_C

[7] INT_HDMICLK+
[7] INT_HDMICLK-

0.1u/10V_4
0.1u/10V_4

[7] INT_HDMITX0N
[7] INT_HDMITX0P

C526
C525

[7] INT_HDMITX1N
[7] INT_HDMITX1P

INT_HDMITX2N_C
INT_HDMITX2P_C

0.1u/10V_4
0.1u/10V_4

[7] INT_HDMITX2N
[7] INT_HDMITX2P

C524
C523

R441

R442

HDMI_5V
+5V

680/J_4 680/J_4 680/J_4 680/J_4 680/J_4 680/J_4 680/J_4 680/J_4

HDMI_MB_HP

Q3
OUT
GND

RV1
*5V/30V/0.2p_4

AP2331SA-7
C2
*220p/50V_4

2N7002K
R19
*100K/F_4

23
21

ABA-HDM-022-P05

1
2

+3V

0/J_4 HP_DET_CN

20
22

R17
20K/J_4

Q1
C

IN

R11

SHELL1
D2+SHELL3
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0CK+
CK Shield
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL4
SHELL2

25

CN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

INT_HDMITX2P_C

D1
*5V/30V/0.2p_4

C4

C3
*1000p/50V_4

*1000p/50V_4

HDMI DDC (HDM)

EMI (EMC)

+5V

+3V

HDMI-detect (HDM)

D20
RB500V-40

+3V

INT_HDMITX2P_C

[7] HDMI_DDCCLK_SW

0/J_4

Q38
BSN20

HDMI_DDCCLK_COM

*100/F_4

R439
2.2K/J_4

+3V
B

INT_HDMITX2N_C
HDMI_DDCCLK_MB

INT_HDMITX1P_C

Follow CRB 1.0 change to 2.2K

R436

+5V

*100/F_4
INT_HDMITX1N_C

+3V

R16
1M/J_4

INT_HDMITX0P_C

D19
RB500V-40

R9

+3V

*100/F_4

R470

R435
R463
2.2K/J_4

Q4

[7] HDMI_HP

3 HDMI_MB_HP

INT_HDMITX0N_C
2N7002K

R469

[7] HDMI_DDCDATA_SW

0/J_4 HDMI_DDCDATA_COM

Q37
R462
2.2K/J_4

INT_HDMICLK+_C

BSN20
3

R438
2.2K/J_4

R10
HDMI_DDCDATA_MB

*100/F_4
INT_HDMICLK-_C
A

Follow CRB 1.0 change to 2.2K

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

HDMI
Date:
5

Monday, January 07, 2013

Sheet
1

25

of

46

mSATA Redriver (HDD)

Q63
+3VPCU

[9] CLK_PCIE_WLAN
[9] CLK_PCIE_WLAN#

*RD@4.7K/J_4

CLK_PCIE_WLAN_REQ#_R
Chip test mode enable, internally pulled down at ~150K
L: Normal operation
H: Test mode enable
For SATA/SAS PHY test, this pin should be pulled to High

+1.5V

PCIE_WAKE#_R

RD_POWER

+3V

R827

PS8@0/J_4

R838

ASM@0/J_4

LTS_AAA-PCI-092-P05

Note:
REXT can be left open or connected to VDD with default
swing setting

R839

ASM@0/J_4

RD@0.01u/25V_4
RD@0.01u/25V_4

1
2
3
4
5

SATA_TXP1_C
SATA_TXN1_C

SATA_RXN1_C
SATA_RXP1_C

A_INp
A_INn
GND
B_OUTn
B_OUTp

6
7
8
9
10

RD@0.01u/25V_4
RD@0.01u/25V_4

R771

R721

USBP10+ [9]
USBP10- [9]

C773
10u/6.3V_6

WLAN_CLK_SDATA
WLAN_CLK_SCLK
+1.5V_Mini1_VDD
+WL_VDD
RF_EN [34]

+WL_VDD

0/J_8

R704

*0/J_4

R1 PLTRST#

R701

0/J_4

R2 IOAC_PCIERST#

R706

*0/J_4

R3

C787
0.1u/10V_4

C762
*0.1u/10V_4

C707
*0.1u/10V_4

20120221 add R1 for PLTRST#.

20120216 add R2/R3 un-stuff for iRST reserve.
IOAC_PCIERST#

[28,34]

PCIERST# [28,34]
+1.5V_Mini1_VDD

16
14
12
10
8
6
4
2

500mA for +1.5V

+1.5V

R692

*0/J_8

+1.5V_Mini1_VDD
C784
*1000p/50V_4

+WL_VDD

C766
*0.1u/10V_4

C722
*10u/6.3V_6

ASM@4.7K/J_4

B_PRE0
A_PRE0
I2C_EN

R840

C855
C860
RD@0.1u/10V_4

C861
PS8@0.01u/25V_4

Leakage circuit (MPC)

LAYOUT NOTE:
CLOSE TO CONNECTOR

20120105 Change power plant for leakage issue.

+3V_S5

+WL_VDD

0/J_8
C811

C520
0.1u/10V_4

C521

rating = 1000mA @ 128G

0.1u/10V_4

2N7002DW

S5

R361
4.7K/J_4

[9,23] SMB_PCH_DAT

[9,23] SMB_PCH_CLK

R358
4.7K/J_4

IOAC

WLAN_CLK_SDATA

2
+3V_SATA

A_OUTp
A_OUTn
GND
B_INn
B_INp

15
14
13
12
11

SATA_TXP1_PS R828
SATA_TXN1_PS R829

RD@0/J_4 SATA_TXP1_PS_R
RD@0/J_4 SATA_TXN1_PS_R

SATA_RXN1_PSR830

RD@0/J_4 SATA_RXN1_PS_R

SATA_RXP1_PS R831

RD@0/J_4 SATA_RXP1_PS_R

H=4.95mm

RD@PS8521A/ASM1466

R813

ASM@4.7K/J_4

R434
R433

0/J_4
0/J_4

SATA_TXP1_PS_R
SATA_TXN1_PS_R

C854 0.01u/25V_4
C853 0.01u/25V_4

SATA_TXP1_PS_C
SATA_TXN1_PS_C

SATA_RXN1_PS_R
SATA_RXP1_PS_R

C852 0.01u/25V_4
C851 0.01u/25V_4

SATA_RXN1_PS_C
SATA_RXP1_PS_C

RD_POWER

R841
ASM@2K/F_4

*PS8@1u/6.3V_4

R819
R820

NRD@0/J_4
NRD@0/J_4

SATA_TXP1_R R823
SATA_TXN1_R R824

NRD@0/J_4
NRD@0/J_4

SATA_TXP1_PS_R
SATA_TXN1_PS_R

SATA_RXN1
SATA_RXP1

R821
R822

NRD@0/J_4
NRD@0/J_4

SATA_RXN1_R R825
SATA_RXP1_R R826

NRD@0/J_4
NRD@0/J_4

SATA_RXN1_PS_R
SATA_RXP1_PS_R

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

SATA_TXP1
SATA_TXN1

Reserved
Reserved
Reserved
Reserved
GND
+3.3Vaux
+3.3Vaux
GND
GND
SATA_Tp0
SATA_Tn0
GND
GND
SATA_Rn0
SATA_Rp0
GND
UIM_C4
UIM_C8
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#

+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND

53

LTS_AAA-PCI-092-P05

UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

20120105 Change power plant for leakage issue.

+3V_S5

2N7002DW

S5

5
4

[9] CLK_PCIE_WLAN_REQ#

+WL_VDD

R341
4.7K/J_4

R348
4.7K/J_4

IOAC

CLK_PCIE_WLAN_REQ#_R

2
1

[34] WAKE_SRC_1

PCIE_WAKE#_R

Debug
A_LFRAME#_R
A_LAD3_R
A_LAD2_R
A_LAD1_R
A_LAD0_R

R432
R431
R430
R429
R428

Q28

0/J_4
0/J_4
0/J_4
0/J_4
0/J_4

LPC_LFRAME# [8,27,34]
LPC_LAD3 [8,27,34]
LPC_LAD2 [8,27,34]
LPC_LAD1 [8,27,34]
LPC_LAD0 [8,27,34]

R342

*0/J_4

R347

*0/J_4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

Mini Card/mSATA
1

WLAN_CLK_SCLK

Q30

CN22

Debug

[9,16,27,28,34] PLTRST#
[9] CLK_LPC_DEBUG

Close to connector
RD_POWER

C867
ASM@10u/6.3V_6

+WL_VDD
+3V_WLAN

10u/6.3V_6

VDD
EN
B_PRE0
A_PRE0
I2C_EN#

C865
C863

[8] SATA_RXN1
[8] SATA_RXP1

WLAN_OFF [34]

+3V_SATA

+3V

RD_POWER

REXT
A_PRE1
TEST
B_PRE1
VDD

U51

Closed to ASM1466 Power Pin

C862
C864

Mini card +3V power disable

TP41

20
19
18
17
16

ASM@0.1u/10V_4
ASM@0.1u/10V_4
ASM@0.1u/10V_4
ASM@0.1u/10V_4

REXT
A_PRE1
TEST
B_PRE1

*PS8@4.99K/F_4

[8] SATA_TXP1
[8] SATA_TXN1

High

+1.5V_Mini1_VDD

mSATA (HDD)

R812

RD_POWER

UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V

20120217 reserve R648 PU 100k.

+WL_VDD

Mini card +3V power enable

LAYOUT NOTE:
CLOSE TO CONNECTOR

RD_POWER

C868
C869
C870
C871

GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#

GND

R814

15
13
11
9
7
5
3
1

GND

TEST

[9] PCIE_RX8+
[9] PCIE_RX8-

Pre-emphasis level setting for Channel B,

3.3V tolerant. Internally pulled down at
~150K
[B_PRE1, B_PRE0] ==
00: no pre-emphasis
01: 2dB pre-emphasis is selected
10: 3.5dB pre-emphasis is selected
11: 5dB pre-emphasis is selected

*ASM@0/J_4

0.1u/10V_4 PCIE_TX8+_C
0.1u/10V_4 PCIE_TX8-_C

GND

*RD@4.7K/J_4
*RD@4.7K/J_4

C769
C765

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

Low

54

R843

R816
R815

[9] PCIE_TX8+
[9] PCIE_TX8-

+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND

GND

B_PRE0
B_PRE1

+WL_VDD
Layout Notes:
Place decoupling CAPs close to Connector

Reserved
Reserved
Reserved
Reserved
GND
+3.3Vaux
+3.3Vaux
GND
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8

26

20111122 change to PMOS

54

*ASM@0/J_4

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

0/J_4
*0/J_4 CL_RST1#_WLAN
*0/J_4 CL_DATA1_WLAN
*0/J_4 CL_CLK1_WLAN

[34] IOAC_LANPWR#

53

R842

Pre-emphasis level setting for Channel A,

3.3V tolerant. Internally pulled down at
~150K
[A_PRE1, A_PRE0] ==
00: no pre-emphasis
01: 2dB pre-emphasis is selected
10: 3.5dB pre-emphasis is selected
11: 5dB pre-emphasis is selected

*RD@4.7K/J_4
*RD@4.7K/J_4

R708
*100K/J_4

CN13
R737
R732
R730
R727

[34] BT_POWERON
[9] CL_RST1#
[9] CL_DATA1
[9] CL_CLK1

AO3413

Check LED signal. (active high or low)

H=5.2mm

RD_POWER

R818
R817

MINI-CARD WLAN(MPC)
+3.3V: 1000mA
+3.3Vaux:330mA
+1.5V:500mA

A_PRE0
A_PRE1

Sheet

26
8

of

46

MAIN SATA HDD (HDD)

TPM (TPM)

27

CN11

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

R352

+5V_HDD

0_8
C732

+5V
19

*100u/6.3V_1206

C388

C358

C359

C386

C357

10u/6.3V_6

*0.1u/25V_4

*0.1u/25V_4

0.01u/25V_4

0.01u/25V_4

CN17
R410

[7,34] CLKRUN#
[9,16,26,28,34] PLTRST#

+5V_HDD

+3V_S5
+3V

Layout Notes:
Place decoupling CAPs close to Connector
SATA_RXP0_C
SATA_RXN0_C

C694
C683

0.01u/25V_4
0.01u/25V_4

SATA_TXN0_C
SATA_TXP0_C

C677
C676

0.01u/25V_4
0.01u/25V_4

[8,34] SERIRQ
[7] LPCPD#
[8,26,34] LPC_LAD0
[8,26,34] LPC_LAD1
[8,26,34] LPC_LFRAME#
[9] PCLK_TPM

SATA_RXP0 [8]
SATA_RXN0 [8]

C794
R412
R411

R408
C508

SATA_TXN0 [8]
SATA_TXP0 [8]

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

TPM@0/J_4

TPM@0.1u/10V_4
TPM@0/J_4
TPM@0/J_4

SERIRQ_R
LPCPD#_R

TPM@0/J_4 PCLK_TPM_C
TPM@10p/50V_4

[8,26,34] LPC_LAD2
[8,26,34] LPC_LAD3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

TPM@TPM_CONN

SATA_HDD

3/5VPCU reset switch (CLG)

SW3
3/5V_SW
3
1

SYS_SHDN#
C812
0.1u/16V_4

D33
*14V/38V/100P_4
2

[3,36,41]

2
4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

SATA-HDD/ TPM
Date:
1

Monday, January 07, 2013

Sheet
4

27

of

46

R336

+3V_S5

Q26
+3VPCU

VDD33

10p/50V_4

VDD10

2
1

VDD33
VDD33

R797
CARD_3V3

[29] CARD_3V3

0/J_6

C866
0.1u/10V_4

R45

0/J_4

TP37

4
1

MDI1+
MDI1-

4
1

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

RTL8411BA-CG

MX+
MXMCT
MCT

4
1

X-TX0P
X-TX0N

4
1

3
2

3
2

RJ45-TX0+
RJ45-TX0-

HCMC0805-371MFS
R29
*0/J_4

U8

3
2

3
2

C20

R484

(1.5A) 70 mils

REGOUT
VDDREG
VDDREG
ENSWREG_H
SDA/SPIDI
LED3/SPIDO
SCL/LED_CR
DVDD10
LANWAKEB
DVDD33
ISOLATEB
PERSTB
CLKREQB
SD_WP/MS_D1/xD_WP#
MS_BS/xD_CLE
VDD33/18

TD+
TDTCT
TCT

6
5
3
4

L6
TX1P_R
TX1N_R

REGOUT
ENSWREG R337
0/J_4
SDA/SPIDI
TP38
LED3/SPIDO/EEDO_NC
TP40
SCL/LED_CR_NC
TP39

4
1

MDI3MDI3+

VDD33

3
2

R486

R343
15K/F_4

3
2

3
2

RJ45-TX1+
RJ45-TX1-

HCMC0805-371MFS
R27
*0/J_4

R452

3
2

1
2
8
7

TX3N_R
TX3P_R

0/J_4

TD+
TDTCT
TCT

*0/J_4

L22
6
5
3
4

MX+
MXMCT
MCT

4
1

X-TX3N
X-TX3P

4
1

3
2

3
2

RJ45-TX3RJ45-TX3+

HCMC0805-371MFS
R453
*0/J_4

U31
6
5
3
4

L25
4
1

MDI2MDI2+

VDD33/18

4
1

TRANSFORMER

R345
1K/J_4

CLK_PCIE_LAN_REQ#_Q
SP12

U30

4
1

*0/J_4

L1
4
1

X-TX1P
X-TX1N

0.01u/25V_4

*HCMC0805-371MFS
R485
0/J_4

VDD10
PCIE_LAN_WAKE#_Q
R798
0/J_6
VDD33
ISOLATEB

R28
1
2
8
7

MCT
MCT
MX+
MX-

0/J_4

L24

+3V

VDDREG

TCT
TCT
TD+
TD-

TRANSFORMER

*HCMC0805-371MFS
R44
0/J_4

4
1

3
2

3
2

TX2N_R
TX2P_R

TCT
TCT
TD+
TD-

R454
1
2
8
7

MCT
MCT
MX+
MX-

L23
4
1

X-TX2N
X-TX2P

TRANSFORMER

*HCMC0805-371MFS
R487
0/J_4

*0/J_4

TERM0
4
1

3
2

3
2

RJ45-TX2RJ45-TX2+

HCMC0805-371MFS
R455
*0/J_4
R471
75/F_8
C

[26,34] PCIERST#
[9,16,26,27,34] PLTRST#

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

[26,34]

SP5
SP6
SP7
SP8
SP9
SP10

IOAC_PCIERST#

PCIE_RXN3_C
PCIE_RXP3_C

R802

*0/J_4

R796

*0/J_4

R795

0/J_4

TERM9
C558
C557
C560
C559
C46
C45
C48
C47

C385
C384

0.1u/10V_4
0.1u/10V_4

C383
C382

0.1u/10V_4
0.1u/10V_4

PCIE_RXN3_LAN [9]
PCIE_RXP3_LAN [9]

EVDD10
PCIE_TXN3_C
PCIE_TXP3_C

Leakage circuit (LAN)

28

*0/J_4

L2
6
5
3
4

TRANSFORMER

10/31 modify

For Support DC IOAC .

SP12
SP13

3
2

1
2
8
7

TX0P_R
TX0N_R

10K/J_4

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
MIDP2
MDIN2
AVDD10
MDIP3
MDIN3
AVDD33
DVDD33
Card_3V3
SD_D7/xD_RDY
SD_D6/MS_INS#/xD_RE#
SD_D5/xD_CE#

SP5
SP6
SP7
SP8
SP9
SP10

TP81

4
1

Power source mode:

Pin45 :Pull-up VDD33 for SWR mode
Pull-down for LDO mde

SD_D4/xD_WE#
SD_D1/MS_CLK/xD_D6
SD_D0/MS_D7/xD_D5
SD_CLK/MS_D3/xD_D4
SD_CMD/MS_D6/xD_D3
SD_D3/MS_D2/xD_D2
SD_D2/xD_D7
GND
HSIP
HSIN
REFCLK_P
REFCLK_N
EVDD10
HSOP
HSON
GND

MDI3+
MDI3-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

R30
U9

3
2

*HCMC0805-371MFS
R46
0/J_4

VDD33/18

*0/J_4

LED0/SPICSB
GPO_NC
R331
LED1/SPICLK/EESK

GND

0/J_4

L7

AVDD33
AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
AVDD33
XD_CD#
MS_D0/xD_D1
MS_D4/xD_D0
SD_CD#/MS_D5/xD_ALE
VDD33/18
DVDD10
LED0/SPICSB
GPO
LED1/SPISCK

4
3

MDI1+
MDI1MDI2+
MDI2-

VDD10

R47
4
1

If use RTL8411BAR, unstuff R330

SP13
R330

LAN_RESET

LAN_XTAL2

VDD10

SP12
SP13

50 mils

VDD33-18

U22
65

MDI0+
MDI0-

[29]
[29]

40 mils

VDDREG

VDD33

LAN_XTALI

SP5
SP6
SP7
SP8
SP9
SP10

VDD33

0/J_6

MDI0+
MDI0-

Y1
25MHz_XTAL

[29]
[29]
[29]
[29]
[29]
[29]

0/J_6

R333

LAN_XTALI
LAN_XTAL2

VDD10
2.49K/F_4

R329
C306

R334

LANPWR#

X'tal 25MHz

[34]

10p/50V_4
R335
*1M/J_4

AO3413

1
R324
*100K_4

C307

Transformer (LAN)

(1.5A) 60 mils

*0/J_8

CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_TXN3_LAN
PCIE_TXP3_LAN

[9]
[9]
[9]
[9]

*6.8P/50V_4
*6.8P/50V_4
*6.8P/50V_4
*6.8P/50V_4
*6.8P/50V_4
*6.8P/50V_4
*6.8P/50V_4
*6.8P/50V_4

MDI3+
MDI3MDI2+
MDI2MDI1+
MDI1MDI0+
MDI0-

R448
D22
C535
*SUG@BS201N
*SUG@1M_8

220p/3KV_1808

LAN/Card reader (LAN)

Reserver for EMI

Layout Notes:
Place decoupling CAPs close to LAN Chip

+3V
+3V +3V_S5

VDD33

RJ45 CONNECTOR (LAN)

R349
10K/J_4

S0

CN1
5

CLK_PCIE_LAN_REQ#_Q

R340

2N7002DW

10K/J_4

S5

1016
Exchange Q29 pin 3 & 4 to prevent leakage issue

S5
[7] PCIE_LAN_WAKE#
[34] LAN_WAKE#

R803

*0/J_4

R804

0/J_4

*0/J_4

R346

*0/J_4

RJ45-TX0+
RJ45-TX0RJ45-TX1+
RJ45-TX2+
RJ45-TX2RJ45-TX1RJ45-TX3+
RJ45-TX3-

PCIE_LAN_WAKE#_Q

PCU

Q29
R351

1012
LAN request pin power domain need to sync with ISOLATEB pin

CLK_PCIE_LAN_REQ# [9]

1
2
3
4
5
6
7
8

10

9
10

0+
01+
2+
213+
3-

11
12

11
12

RJ45

10 mils

VDD33

Power-on Strapping

1012
Change choke from 2.2uH to 4.7uH by FAE

VDD33/18

SURGE (LAN)

VDD10
SDA/SPIDI

R338

1.5K/F_4
C371

C352

*4.7u/6.3V_6 0.1u/10V_4

Place close to pin 33

Close to Chip

VDD33

C303

REGOUT

C302

*4.7u/6.3V_6 *0.1u/10V_4

VDDREG

U10

4.7uH/680mA

(1.5A) 60 mils

C301
4.7u/6.3V_6

MDI1MDI1+
MDI0MDI0+

C300
0.1u/10V_4

Place close to pin 53

1
2
3
4

1
2
3
4

EVDD10

40 mils

(1.5A) 60 mils VDD10

C310
C309
0.1u/10V_4

C343
C351
0.1u/10V_4

0.1u/10V_4

C317
4.7u/6.3V_6

RJ45-TX1RJ45-TX1+
RJ45-TX0RJ45-TX0+

1
2
3
4

1
2
3
4

8
7
6
5

8
7
6
5

*SUG@UCLAMP2512T.TCT

30 mils

U34
0/J_6

0.1u/10V_4

U3
8
7
6
5

Place Close pins-- 48

R356
C313
C341
0.1u/10V_4

8
7
6
5

*SUG@UCLAMP2512T.TCT

If use RTL8411BAR, unstuff C303/C302

Max current is 1400mA

keep routing trace at least 50 mil

L20

C318
0.1u/10V_4

C311
C312
0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

C316
C727
0.1u/10V_4

C330
0.1u/10V_4

C390

0.1u/10V_4

C381
0.1u/10V_4

1u/6.3V_4

MDI3MDI3+
MDI2MDI2+

1
2
3
4

1
2
3
4

8
7
6
5

U28
8
7
6
5

RJ45-TX3RJ45-TX3+
RJ45-TX2RJ45-TX2+

*SUG@UCLAMP2512T.TCT

1
2
3
4

1
2
3
4

8
7
6
5

8
7
6
5

*SUG@UCLAMP2512T.TCT

Quanta Computer Inc.

PROJECT : ZQK
Size

Place Close to LAN chip, for VDD33 pins-- 11, 12, 39, 58, 63, 64

Place connect to Pin46/47

Place Close to LAN chip, for VDD33 pins-- 3, 8, 41, 52, 61

Close to Pin29

Rev
1A

LAN-RTL8411/CARD READER
Date:

Document Number

Monday, January 07, 2013

1

Sheet

28

of

46

SD-CARD

CN12

SD_WP
SD_CD#

MS_INS#
MS_CLK
MS_D7
MS_D3
MS_D6
MS_D2
MS_BS
MS_D1
MS_D5
MS_D4
MS_D0

xD_RDY
xD_RE#
xD_CE#
xD_WE#
xD_D6
xD_D5
xD_D4
xD_D3
xD_D2
xD_D7
xD_CLE
xD_WP#
xD_ALE
xD_D0
xD_D1
xD_CD#

[28]
[28]
[28]
[28]

SP5
SP6
SP7
SP8

[28] SP9
[28] SP10
[28] SP12
[28] SP13
[28] CARD_3V3

SP5=SD_D1=MS_CLK=XD_D6
SP6=SD_D0=MS_D7=XD_D5
SP7=SD_CLK=MS_D3=xD_D4
SP8=SD_CMD=MS_D6=xD_D3

R685
R687

0/J_4
0/J_4

SP9=SD_D3=MS_D2=XD_D2
SP10=SD_D2=XD_D7

R703

0/J_4

SP12=SD_WP=MS_D1=XD_WP#

R690

0/J_4

SP13=SD_CD#=MS_D5=XD_ALE

11
10
9
8
7
6
5
4
3
2
1

SP13=SD_CD#=MS_D5=XD_ALE
SP12=SD_WP=MS_D1=XD_WP#
SP10=SD_D2=XD_D7
SP5=SD_D1=MS_CLK=XD_D6
SP6=SD_D0=MS_D7=XD_D5
SP7=SD_CLK=MS_D3=xD_D4
CARD_3V3
SP8=SD_CMD=MS_D6=xD_D3
SP9=SD_D3=MS_D2=XD_D2

CARD/DET
W/P
DATA2
DATA1
DATA0
VSS2
CLK
VDD
VSS1
CMD
CD/DATA3

CARD_3V3

GND

SD_D7
SD_D6
SD_D5
SD_D4
SD_D1
SD_D0
SD_CLK
SD_CMD
SD_D3
SD_D2

0/J_4
0/J_4
0/J_4
0/J_4

GND

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16

R699
R700
R698
R689

12

Share Pin

29

SD/MMC CARD READER (MMC)

13

CARD READER CONNECTOR (MMC)

10 mils
CARD_3V3
C708
4.7u/6.3V_6

EMI
SP5=SD_D1=MS_CLK=XD_D6

Place close to connector

SP7=SD_CLK=MS_D3=xD_D4
3

C751

C734

*6P/50V_4

*6P/50V_4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

CARD READER CONNECTOR

Date:
A

Monday, January 07, 2013

Sheet
E

29

of

46

Codec (ADO)

HEADPHONE/Mic combo (AMP)

+5VA

30

EAPD#
R769

20120910: ALC3225 has a internal MOSFET

HP-L

*10K_4

HP

HP-R

22K/F_4

C776
10u/6.3V_6

C796
C797
2.2u/6.3V_6

Need check AMP

PD PIN level

C456
0.1u/10V_4

MIC2-VREFO
*10u/6.3V_6

C434

+1.5V

0_6 +3VCPVDD

2.2u/6.3V_6

C429

MIC2-L

2.2u/6.3V_6

C424

R729
2.2K/J_4

MIC2_MIC

ADOGND
D

R369

1K/J_4

COMBO_MIC

ADOGND
R807

R806

C464

*0/J_4

0/J_4

close to pin 27

10u/6.3V_6

R731
22K/F_4

ADOGND
+5VA

D11
*14V/38V/100P_4

20121009: FAE Vic request to change 0 ohm to 1K ohm

C433
C782
0.1u/10V_4

R733

MIC2-R

Place next to pin 28

2.2u/6.3V_6

ADOGND

+3V

R726

MIC2-VREFO

R371
*10K_4

COMBO_MICJD

ANALOG

ADOGND

Combo Jack

ADOGND

+
2.2u/6.3V_6

47

PD#

48

COMBO_MICJD

49

DIGITAL

GND

JDREF
Sense B
Sense A

R366

0_6

+3VDVDD

0/J_6

HPL_SYS

HP-R

R392

56/F_4

HP-R-1

R402

0/J_6

HPR_SYS

R_SPK2

D12
*14V/38V/100P_4

7
SIT_2SJ3052-005111F

D17
*14V/38V/100P_4

D16
*14V/38V/100P_4

22

ADOGND

21
ADOGND

ADOGND

ADOGND

20
19
18

MIC2-R

17

MIC2-L

combo MIC

15

R399

20K/F_4

close to pin 15

ADOGND

14
13

SENSEA

R398

Internal Speaker (AMP)

39.2K/F_4

Output Gain Table

+5V

Pin1 - Pin6: DGND

Pin7 - Pin12: AGND
Thermal Pad: DGND

16

R768

C804
0.1u/10V_4

0_6 +5V_AMP

C808
10u/6.3V_6

HPOUT_JD

close to U5001
U27

close to pin 13

ANALOG
R_SPK2

PCBEEP dont coupling any signals if possible

8/17 separate PCBEEP to Digital from Realtek suggestion

C510

1u/16V_6

R415

0_6

C509

1u/16V_6

C461

L_SPK2

1u/35V_6 BEEP_1

R393

47K/J_4

C426
10u/6.3V_6

C466

BEEP_2
D14

RB500V-40

D13

RB500V-40

R394
4.7K/J_4

100p/50V_4

C479

1u/16V_6

R404

0_6

9
7

EAPD#

1.6Vrms
PCBEEP

20121205: FAE Vic request to change 47 ohm to 56 ohm

SPK-2

ALC3225

C791
10u/6.3V_6

2
5
6

L_SPK2

23

close to pin 7
C430
0.1u/10V_4

R382

24

DIGITAL
+3V

HP-L-1

26

27

28

29

25
AVSS1

AVDD1

LDO1-CAP

VREF

31

32

33

34

30

MIC2-VREFO

MIC1-VREFO-R

MIC1-VREFO-L

HP-OUT-L

HP-OUT-R

CPVEE

35

SPDIFO/GPIO2

Spilt by DGND

Place next to pin 46

36

PDB

56/F_4

1u/16V_6 10

C490

INPUT-R
PD#
INPUT-L

R2

R3

R4

NC

NC

11dB

NC

NC

14dB

NC

NC

19dB

NC

NC

25dB

OUT-LN
OUT-LP

6
5

R403
*0/J_6

R414
*0/J_6

PCBEEP_EC [34]

*100p/50V_4

BYP

+5VA

Gain (Differential)

2
1

R767
*0/J_4

L_SPK2L_SPK2+
G1
G2

G1
G2

11
12

PCH_AZ_CODEC_RST#

D34

DMIC

R380

PCH_AZ_CODEC_SYNC
0_6

DMIC_CLK

C452

C448

0.1u/10V_4

10u/6.3V_6

R418

R405
0/J_4

C442

R381

33/J_4

R4
ADOGND

[8]

*22K/F_4

Layout Note:
Place very close to U5001

+3V

PCH_AZ_CODEC_SDIN0

R_SPK2+
R_SPK2L_SPK2L_SPK2+

[8]

R425
R424
R421
R420

PCH_AZ_CODEC_SDOUT

[8]

20120928
Follow ME & PDC pin define

40mil for each signal

C501
[8]

Layout Note:
Place very close to U5001

ADOGND

0_6
0_6
0_6
0_6

*22p/50V_4
PCH_AZ_CODEC_BITCLK

R764
0/J_4

R3

C810
2.2u/6.3V_6

*20K/F_4

R770

Place next to pin 9

ACZ_SDIN0_R

R2

<20121018>Add D34 for ESD

DMIC_DATA
+3VDVDDIO

ADOGND

[8]

R766
*0/J_4

R1

G1
G2

Place next to pin 1

5.5V/25V/410P_4

R_SPK2+
R_SPK2-

SPKR [8]

ALC1001-CGT
C460

R1

+5VA

OUT-RP
OUT-RN

GND

0.1u/10V_4

R383

13

C427

10u/6.3V_6

HP-L

3
4

C423

PVDD2

10u/6.3V_6

PVDD1
PVDD2

C412

10u/6.3V_6 0.1u/10V_4

MONO-OUT

PCBEEP

C415

46

+5VPVDD2

SPK-R+

12

+5V

0_6

MIC2-L

RESET#

R363

SPK-R-

SYNC

Place next to pin 41

MIC2-R

11

45

MIC1-L

SPK-L-

DVDD-IO

44

R_SPK+

MIC1-R

SPK-L+

R_SPK-

SPK-1

PVDD1

10

43

SDATA-IN

42

L_SPK-

LINE2-L

LINE1-L

L_SPK+

0.1u/10V_4

0.1u/10V_4

4
3
1

HPOUT_JD

LINE2-R

LDO3-CAP

C422

10u/6.3V_6

C477

ADOGND

LINE1-R

BIT-CLK

+5VPVDD1
C419

C469

Place next to pin 26

AVDD2

0_6

C413

10u/6.3V_6 0.1u/10V_4

ADOGND

LDO2-CAP

SDATA-OUT

C416

41

AVSS2

R359

+5V

40

ANALOG

DVSS

39

ADOGND

CBP

38

GPIO1/DMIC-CLK

37
C778
10u/6.3V_6

Place next to pin 40

CBN

CPVDD

ADOGND

C428
0.1u/10V_4

GPIO0/DMIC-DATA

ADOGND

U25

DVDD

+1.5VAVDD2

C425
10u/6.3V_6

CN15

DIGITAL

Layout Note:
Place close to Codec

R364
0_6

C500

C497

C496

*68p/50V_4 *68p/50V_4 *68p/50V_4 *68p/50V_4

R_SPK+ R427
R_SPK- R426
L_SPK- R423
L_SPK+ R422

0_6
0_6
0_6
0_6

CN21
R_SPK+_2
R_SPK-_2
L_SPK-_2
L_SPK+_2
R_SPK+_1
R_SPK-_1
L_SPK-_1
L_SPK+_1

L_SPK+_2
L_SPK-_2
L_SPK+_1
L_SPK-_1
R_SPK-_2
R_SPK+_2
R_SPK-_1
R_SPK+_1

1
2
3
4
5
6
7
8

9
10
SPK CN

C503

C502

C499

C498

*68p/50V_4 *68p/50V_4 *68p/50V_4 *68p/50V_4

INT DMIC (AMP)

Mute(ADO)
+5VA
UPB201209T-310Y-N/6A/31ohm_8

0/J_4
0/J_4
0/J_4
*0/J_4
*1000p/50V_4
*1000p/50V_4

+3V

R725
*10K/J_4

ADOGND

AGND plane

PD#

0V : Power down Class D SPK amplifer

3.3V : Power up Class D SPK amplifer
D32

RB500V-40

AMP_MUTE#

D31

RB500V-40 PCH_AZ_CODEC_RST#

Tied at one point only under

the codec or near the codec

AMP_MUTE# [34]

4
3
62
51
DMIC

DMIC_DATA_R

D15

R417

0/J_4

DMIC_DATA

R416

0/J_4

DMIC_CLK

C482
*22p/50V_4

TVS/6pF_4

DMIC_CLK_R
D18

C505
*22p/50V_4

DGND plane

+3V

CN19

L21

*0/J_4

R716
R763
R360
R419
C788
C803

+5V

R772

Power(ADO)

TVS/6pF_4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

REALTEK ALC3225
Date:
5

Monday, January 07, 2013

1

Sheet

30

of

46

USB3.0 (USB)

+5VPCU

2012-06-15
Active High:
1st: AL002820003 (BCD)
2nd: AL007534001 (Promate)
3rd: AL002511002 (DDS)

+5V_S5 -> +5VPCU for battery

mode can charger when enter S4/S5
C37

1u/6.3V_4

Name

U6

IN1
IN2

4
1

USB_BC_EN

8
7
6

OUT3
OUT2
OUT1

USBPWR0

2
3

EN
GND
OC#

C18
470P/50V_4

USB data

31

CB SELCDP FuncionFuncion

State

Max Current

YES

S0~S3

500mA

Apple Device
500mA

DCP autodetect with mouse/keyboard wakeup

CDP

YES

S0~S3

1500mA

500mA

S0 charging with SDP only

NO

S4~S5

1800mA

1800mA

S0 charging with CDP or SDP only (depending on external device)

C530
0.1u/10V_4

CH@: Default stuff

AP2820AMMTR-G1

SDP
DCP,Auto

C539
100u/6.3V_1206

USB Charger to 3.0 (USB)

[9] USB_OC0#
U4

1
2
3

USBP0-_R
USBP0+_R

GND
2
3

6
5
4

6
5
4

CN3

1
2
3
4
5
6
7
8
9

*RClamp0582N
USBP0-_R
USBP0+_R
U5

USB3_TXN1_R
USB3_TXP1_R

1
2
3
4
5

1
2
GND_3/8
4
5

10
9
7
6

10
9

USB3_RXN1_R
USB3_RXP1_R

7
6

USB3_TXN1_R
USB3_TXP1_R

1
2
3
4
5
6
7
8
9

VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+

R40

4
1

4
1

3
2

USBP0-_R
USBP0+_R

R35

CEN
CB1
DM
TDM
DP
TDP
SELCDP VDD
Thermal Pad

R483
R482

AUSB0006-P001A

[34]

8
7
6
5
9

USBP0- [9]
USBP0+ [9]

C28

CH@0.1u/10V_4

C41

*CH@10u/6.3V_6

*NCH@0_4
*NCH@0_4

Pull high CDP/SDP autodetect.

Pull Low SDP only.

*DLW21HN900SQ2L_C
R39
0/J_4

USB_CHG_MODE

CH@SLG55584A

R478
*CH@4.7K_4

0/J_4

3
2

MAINON [34,37,38,41]

CH@0_4

U32

1
2
3
4

BC_CEN
USBP0-_C
USBP0+_C

R477
CH@4.7K_4

L5
USBP0-_C
USBP0+_C

*CH@0_4

R461

+5VPCU

13
12
11
10

*RClamp0524P

R464

+5VPCU

13
12
11
10

USB3_RXN1_R
USB3_RXP1_R

System status(CB)
> Hi: S0 Charging with CDP/SDP.
> Lo: S3,DCP autodetect.

USB 3.0 Connector

USBPWR0

0/J_4

+3VPCU

L3

Layout Notes:
Place close to L6008

C34
*1.6P/50V_4

USB3_RXN1_R
USB3_RXP1_R

R480

CEN:SLG55584A----pull up
SLG55584----pull low

C33
*1.6P/50V_4

[34]

R37
L4
[9] USB30_TX1[9] USB30_TX1+

2
3

2
3

C35
C36

0.1u/10V_4
0.1u/10V_4

USB3_TXN1_C
USB3_TXP1_C

Layout Notes:
Place decoupling CAPs close to Connector

1
4

1
4

2
3

*CH@0.1u/10V_4

USB_BC_EN

USB_CHG_EN

USB_CHG_EN

U33
CH@TC7SH08FU

R474

*NCH@0_4

USB3_TXN1_R
USB3_TXP1_R

*DLW21HN900SQ2L_C
R38
0/J_4
C531
*1.6P/50V_4

C532
*1.6P/50V_4

Layout Notes:
Place close to L6009

USBP0-_R

RV3 1

2 *5V/30V/0.2p_4

USBP0+_R

RV2 1

2 *5V/30V/0.2p_4

USB3_RXN1_R RV4 1

2 *5V/30V/0.2p_4

USB3_RXP1_R RV5 1

2 *5V/30V/0.2p_4

USB3_TXN1_R RV6 1

2 *5V/30V/0.2p_4

USB3_TXP1_R RV7 1

2 *5V/30V/0.2p_4

I/O board (USB)

B

+5V_S5
C189

1u/6.3V_4
U17

USB2.0 (USB)

2
3

+5V_S5
C291

1u/6.3V_4

Active Low:
1st: AL007534000 (Promate)
2nd: AL002820001 (BCD)
3rd: AL002501000 (DDS)

IN1
IN2

4
1

[34] USBON#

OUT3
OUT2
OUT1

EN#
GND
OC#

8
7
6

CN7
USBP4

AP2820CMMTR-G1

C222
0.1u/10V_4

USBP4-_R
USBP4+_R

U20
USB_OC0#

C50
1000p/50V_4

[34] NBSWON#
[24,34]
LID#
C292
100u/6.3V_1206

D9

5
OC#
AP2820CMMTR-G1

*5V/30V/0.2p_4
R217

4
1

[9] USBP4+
[9] USBP4-

1
2
3
4

1
4

D5
*5V/30V/0.2p_4

2
USBP1+_CN
1
2 3
USBP1-_CN
4
3
*DLW21HN900SQ2L_C
R113
0/J_4

USBP1-_CN
USBP1+_CN

D4
*5V/30V/0.2p_4

VDD
DD+
GND1

4
1

3
2

3
2

USBP4+_R
USBP4-_R

GND6
GND5
GND7
GND8

6
5
7
8

Quanta Computer Inc.

USB2.0

PROJECT : ZQK

0/J_4

USB/B CONN
+3VPCU

*DLW21HN900SQ2L_C
R211
0/J_4

CN6

L11

0/J_4

1 13
2 14
3
4
5
6
7
8
9
10
11
12

L17

USB_OC0#

R112

OUT3
OUT2
OUT1

EN#
GND

USBP1

IN1
IN2

4
1

USBON#

8
7
6

2
3

[9] USBP1+
[9] USBP1-

C553

BC_CEN

Battery Status, EC GPO control it.

> Hi: S0 and S3~S5 Battery over 30%
> Lo: S3~S5/ Battery under 30%

0/J_4

2
3

CH@47K_4

1
4

*DLW21HN900SQ2L_C
R36
0/J_4

1
4

[9] USB30_RX1[9] USB30_RX1+

Size

Rev
1A

INT&EXT USB
Date:

Document Number

Monday, January 07, 2013

Sheet
1

31

of

46

K/B (KBC)
CN18
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0

28
27

20121005 SWAP keyboard pin-define

KB_CONN

7
5
3
1
CP1
7
5
3
1
CP2
7
5
3
1
CP3
7
5
3
1
CP6
7
5
3
1
CP4
7
5
3
1
CP5

8
6
4
2
*100p/50Vx4
8
6
4
2
*100p/50Vx4
8
6
4
2
*100p/50Vx4
8
6
4
2
*100p/50Vx4
8
6
4
2
*100p/50Vx4
8
6
4
2
*100p/50Vx4

MX5
MX4
MX3
MX2

C515
C514

*100p/50V_4
*100p/50V_4

MX1
MX0

32

TOUCHPAD BOARD CONN (TPD)

MY1
MY0
MX7
MX6

+3V

R391

0/J_4

+5V

R397

*0/J_4

MY5
MY4
MY3
MY2

R389
10K/J_4

+3V

L32

0_6

+5V

L33

*0/J_6
C798
0.1u/10V_4

R390
10K/J_4

[34] TPCLK
[34] TPDATA

MY9
MY8
MY7
MY6

R757
R756

[9,10] BOARD_ID2
C475
*0.01u/16V_4

+TPVDD
TPCLK_R
TPDATA_R

0/J_4
0/J_4
[9,13,15] CLK_SDATA
[9,13,15] CLK_SCLK

MY13
MY12
MY11
MY10

0/J_4 CLK_SDATA_R
CLK_SCLK_R
0/J_4
TP_INT#_D
R837
*0/J_4

Pin8 of SYNAPTICS and ELAN are NC pin

C474
*0.01u/16V_4

MY17
MY16
MY15
MY14

CN16

50mil
R759
R758

1
2
3
4
5
6
7
8

9
10
TP CN

+3V

[9] SMBALERT#

Q36
*2N7002K

+3VPCU

MX7
MX6
MX5
MX4

RP2
10
9
8
7
6

10K_10P8R
1 MX0
2 MX1
3 MX2
4 MX3
5

KB_BL LED (KBC)

FAN1 For CPU (THM)

+5V

+3V

+5V

+3V

R339
1K/J_4

+5V

R695

10K/J_4
[34]

R691
0/J_8

10K/J_4

CN10

FANSIG1

+5V_FAN1

+5V

R696

*KBL@2.2u/10V_6

C504
R413
KBL@10K/J_4

[34]

CPUFAN1

Q34
KBL@AO3413

FAN_PWM_CN1

Q27
MMBT3904-7-F_200MA

4
3
2
1

6
5

FAN1

30mil

KEY_BL_EN

2
Q35
KBL@DTC144EUA

+5V_KB

R760

FAN2 For GPU (THM)

KBL@0/J_4 +5V_KB_R

C465

C799

KBL@4.7u/6.3V_6

KBL@0.01u/25V_4

CN20

+5V

+3V

[34]

1
2
3
4

+5V

+3V

5
6
R445
1K/J_4

KBL@KB_backlight

R437

R440

10K/J_4

10K/J_4

R449
0/J_8

CN5

FANSIG2

+5V_FAN2

[34]

[34]

CPUFAN2

3
Q2
MMBT3904-7-F_200MA

FAN_PWM_CN2

4
3
2
1

6
5

Quanta Computer Inc.

FAN2

30mil

PROJECT : ZQK
Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

KB/TP/FAN
5

Sheet
1

32

of

46

LED(UIF)

33

HOLE(OTH)

+3V_S5 +3VPCU

150/J_4

2
1

LED1

BATTERY LED

HOLE5
*hg-c236d118p2
7
6
8
5
9
4

Amber
*1M_4

R8

*1M_4

+3VPCU

HOLE6
*HG-TE382X675BC236D118NPTPB
7
6
8
5
9
4

1
2
3

Battery

R7

HOLE9
*hg-c236d118p2
7
6
8
5
9
4

HOLE17
*hg-te394x315be394x313d244p2
5
4

HOLE22
*hg-e394x325d165p2
5
4

3
2

100/J_4

R1

HOLE21
*hg-c236d118p2
7
6
8
5
9
4

[34] SUSLED#

R2

1
2
3

[34] PWRLED#

1
2
3

Blue

HOLE11
*hg-c236d118p2
7
6
8
5
9
4

1
2
3

HOLE1
*hg-c236d118p2
7
6
8
5
9
4

+3V_S5

*1M_4

*1M_4

R5

1
2
3

R6

1
2
3

Power LED

+3VPCU

Blue
[34] BATLED1#

R3

100/J_4

R4

150/J_4

LED2

BATT Enable short pad

HOLE13
*h-te236x236bc236d165p2

BATTERY LED

Amber

SW2

3
4

HOLE19
*h-te236x236bc236d158p2

2
1

Lid Switch

[34] BATLED0#

Stitching cap (EMC)

BATT_EN#

C805
*0.1u/25V_4

VIN

C259
*0.1u/25V_4

HOLE3
*hg-c276d118p2
7
6
8
5
9
4

C800
*0.1u/25V_4

HOLE12
*hg-c276d118p2
7
6
8
5
9
4

+5VPCU

+VCC_GFX

+1.05V_VTT

+1.05V_VTT

+1.05V_VTT

HOLE4
FBAJ2005010

HOLE23
*HG-C236D118P2
7
6
8
5
9
4

+VCC_GFX
+1.05V_VTT

HOLE8
*HG-C236D118P2
7
6
8
5
9
4

1
2
3

C807
*0.1u/25V_4

VIN

C491
*0.1u/25V_4

VIN

1
2
3

C806
*0.1u/25V_4

VIN

1
2
3

VIN

1
2
3

VIN

[35]

+1.05V_VTT

VIN

+1.05V_VTT
HOLE7
FBAJ2003010

HOLE10
FBAJ2003010

HOLE14
HOLE15
HOLE16
*H-TC150BC217D150P2 *H-TC150BC217D150P2 *H-TC150BC217D150P2

HOLE18
FBAJ2005010

HOLE20
*h-c91d91n

C818

+VGPU_CORE
+5VPCU

+5VPCU

+5V_S5

*1000p/50V_4

C228
*0.1u/25V_4

C576
*0.1u/25V_4

C5
*0.1u/25V_4

C549
*0.1u/25V_4

C659
*0.1u/25V_4

C235
*0.1u/25V_4

C790
*0.1u/25V_4

+VGPU_CORE

+5VPCU

+1.05V_VTT
PAD1
*spad-e858x1268
C820

C205
*0.1u/25V_4

C308
*0.1u/25V_4

C288
*0.1u/25V_4

*1000p/50V_4

1
2
3
4
5
6

C305
*0.1u/25V_4

+5V_S5
+1.05V_VTT

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

LED/ Hole
Date:
5

Monday, January 07, 2013

Sheet
1

33

of

46

L16
BLM11A05S/0.2A/120ohm_6

39P/50V_4

C174

0.1u/10V_4

+3VPCU_EC
C220

0.1u/10V_4

C80

0.1u/10V_4

C114

C95

0.1u/10V_4

0.1u/10V_4

C221

0.1u/10V_4

+3V

R126

0_6

AC@0_4

LANPWR# [28]
USB_CHG_MODE [31]
USB_CHG_EN [31]
CLKRUN# [7,27]

+3V_EC

WRST#

[10]
[37]
[37]

SIO_RCIN#
+0.75V_ON
R834

SUSON

SM BUS

PS2CLK0/TMB0/CEC/GPF0(Up)
PS2DAT0/TMB1/GPF1(Up)
PS2CLK2/WUI20/GPF4(Up)
PS2DAT2/WUI21/GPF5(Up)

119
123

R832
CLK_PCI_EC

CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(Dn)

PWM0/GPA0(Up)
PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
PWM4/GPA4(Up)
PWM5/GPA5(Up)

IT8587

CIR

100K/J_4

[35]

D/C#

105
101
102
103

[8] PCH_SPI_CLK_EC
[8] SPI_CS0#_UR_ME
[8] PCH_SPI_SI_EC
[8] PCH_SPI_SO_EC

[33]

56
57
32

[32] MY16
[32] MY17
BATLED1#
+3VPCU_EC

R134

10K_4

[4] EC_DRAMRST_CNTRL
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]

PCH_SPI_SI_EC
PCH_SPI_SO_EC
R527
*10K_4

R526
*10K_4

36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
EC_PECR_R

MBCLK [35]
MBDATA [35]
2ND_MBCLK
[9,19]
2ND_MBDATA [9,19]
43_4
EC_PECI
EC_FPBACK# [24]

R96

85
86
89
90

R102
R92

4.7K_4
4.7K_4

2ND_MBCLK
2ND_MBDATA

R98
R97

4.7K_4
4.7K_4

+3V_S5
[3,10]

WLAN_OFF [26]
USBON# [31]
TPCLK [32]
TPDATA [32]

24
25
28
29
30
31

PWRLED# [33]
ME_WR#
[8]
SUSLED# [33]
BATLED0# [33]
[32]
CPUFAN1
[32]
CPUFAN2

ADC0/GPI0(X)
ADC1/GPI1(X)
ADC2/GPI2(X)
ADC3/GPI3(X)
ADC4/WUI28/GPI4(X)

KSO16/SMOSI/GPC3(Dn)
KSO17/SMISO/GPC5(Dn)
PWM6/SSCK/GPA6(Up)
SSCE0#/GPG2(X)
SSCE1#/GPG0(X)

[32]
[32]

FANSIG1
FANSIG2

120
124

ACIN [35]
TEMP_MBAT

[35]

125
18
21

NBSWON# [31]
SUSB# [7]
SUSC# [7]

112

66
67
68
69
70

[3,35,40]

Q52

PROCHOT_EC
[7]

PCH_RSMRST#

R525

RF_EN
ICMNT
C76

10u/6.3V_6

2N7002K

[26]
[35]

ECAGND
APWROK

Input only

[7]

TP114
dGPU_ALT#

[19]

A/D D/A

SPI ENABLE

TACH2/GPJ0(X)
GPJ1(X)
DAC2/TACH0B/GPJ2(X)
DAC3/TACH1B/GPJ3(X)

KSO0/PD0
KSO1/PD1
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15

47
48

100K_4

76
77
78
79

dGPU_OTP# [19]
EC_FB_CLAMP [17,19,20]
PCH_SUSWARN# [7]
PCH_SUSACK# [7]

KBMX

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

CK32KE/GPJ7
CK32K/GPJ6

IOAC_PCIERST#
VRON [40]

+3V

HWPG(KBC)

[26,28]

R523

CLOCK
R833
IT8587E/EX

C109

SM Bus 2

RB500V-40

D27

*RB500V-40

D26

*RB500V-40

D29

*RB500V-40

D23

*RB500V-40

D25

*BAS316

10K/J_4
HWPG

[41] HWPG_1.8V

SM BUS ARRANGEMENT TABLE

SM Bus 1

D28
[39] HWPG_VCCSA

[38,39] HWPG_VTT

0.1u/10V_4

L13
BLM11A05S/0.2A/120ohm_6

For test only

2
128

100K/J_4
ECAGND

[32]
[32]
[32]
[32]
[32]
[32]
[32]
[32]

WAKE UP

RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn)

EXTERNAL SERIAL FLASH

58
59
60
61
62
63
64
65

Layout Notes:
Place Series Resistors close to ITE8587

100
106

FSCK/GPG7
FSCE#/GPG3
FMOSI/GPG4
FMISO/GPG5

PWRSW/GPE4(Up)
RI1#/WUI0/GPD0(Up)
RI2#/WUI1/GPD1(Up)

VCORE

HWPG

[19] FB_CLAMP_TGL_REQ#
[30] PCBEEP_EC

Please do not place any

pull-up resistor
on GPG0, GPG2, and GPG6
(Reserved
hardware strapping).

110
111
115
116
117
118

+3VPCU

MBCLK
MBDATA

H_PROCHOT#

ADC5/DCD1#/WUI29/GPI5(X)
ADC6/DSR1#/WUI30/GPI6(X) UART port
ADC7/CTS1#/WUI31/GPI7(X)
RTS1#/WUI5/GPE5(Dn)
PWM7/RIG1#/GPA7(Up)
DTR1#/SBUSY/GPG1/ID7(Dn)
CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn)

12

71
72
73
35
34
107
95
94

AVSS

SLP_SUS#
LAN_WAKE#

TMRI0/WUI2/GPC4(Dn)
TMRI1/WUI3/GPC6(Dn)

75

[7,11]
[28]

DPWROK

VSS
VSS
VSS
VSS
VSS

[7]

VSS

TP7

C118
*10p/50V_4

TACH0A/GPD6(Dn)
TACH1A/TMA1/GPD7(Dn)

*22_4

PWM
DAC4/DCD0#/GPJ4(X)
DSR0#/GPG6(X)
GINT/CTS0#/GPD5(Up)
PS2DAT1/RTS0#/GPF3(Up)
DAC5/RIG0#/GPJ5(X)
PS2CLK1/DTR0#/GPF2(Up)
TXD/SOUT0/GPB1(Up)
RXD/SIN0/GPB0(Up)

27
49
91
113
122

[31,37,38,41]
MAINON
[26] BT_POWERON
[7] PWROK_EC
[32] KEY_BL_EN
[30] AMP_MUTE#
[24] COLOR_ENG

R150

KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7

80
104
33
88
81
87
109
108

*10K_4

GPIO

100K/J_4

PROCHOT_EC

R95

SM BUS PU(KBC)

99
98
97
96
93

19
20

84
83
82

127
VSTBY

3
74

GA20/GPB5(X)
SERIRQ/GPM6(X)
ECSMI#/GPD4(Up)
ECSCI#/GPD3(Up) LPC
WRST#
KBRST#/GPB6(X)
PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT

SMCLK0/GPB3(X)
SMDAT0/GPB4(X)
SMCLK1/GPC1(X)
SMDAT1/GPC2(X)
PECI/SMCLK2/WUI22/GPF6(Up)
SMDAT2/WUI23/GPF7(Up)

PS/2

[10] SIO_A20GATE
[8,27]
SERIRQ
[10] SIO_EXT_SMI#
[10] SIO_EXT_SCI#

LPCPD#/WUI6/GPE6(Dn)

WUI42/GPH6/ID6(Dn)
WUI41/GPH5/ID5(Dn)
WUI40/GPH4/ID4(Dn)
WUI19/GPH3/ID3(Dn)
CLKRUN#/WUI16/GPH0/ID0(Dn)

2
C126
1U/6.3V_4

126
5
15
23
14
4
16

L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)

D7
SDMK0340L-7-F

17

LID#

LAD0/GPM0(X)
LAD1/GPM1(X)
LAD2/GPM2(X)
LAD3/GPM3(X)
LPCRST#/WUI4/GPD2(Up)
LPCCLK/GPM4(X)
LFRAME#/GPM5(X)

EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)

[24,31]

R168
100K_4

10
9
8
7
22
13
6

[8,26,27] LPC_LAD0
[8,26,27] LPC_LAD1
[8,26,27] LPC_LAD2
[8,26,27] LPC_LAD3
[9,16,26,27,28]
PLTRST#
[9] CLK_PCI_EC
[8,26,27] LPC_LFRAME#

VCC
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

U15

VBAT
AVCC

0.1u/10V_4

11
26
50
92
114
121

C106

+3VPCU

10K_4

+3V_GFX
dGPU_OPP#

S5_ON [36,41]
IOAC_LANPWR# [26]
WAKE_SRC_1 [26]

0.1u/10V_4
R517

R177

DNBSWON# [7]
SB_ACDC [35]
dGPU_OPP# [19]

dGPU_OPP#
C79

S5_ON

12 mils
+3V_RTC

12 mils
C850

+3VPCU

+3VPCU

ECAGND

2.2_6
2

1008
Change Power rail from +3VPCU to +3VPCU_EC

+3VPCU_ECPLL L10
+3VPCU_EC
BLM11A05S/0.2A/120ohm_6
C78
(For PLL Power)
0.1u/10V_4

C150
0.1u/10V_4

+3VPCU_EC and +3V_RTC

minimum trace width 12mils.
R223
1

EC(KBC)

+A3VPCU

Battery

[37] HWPG_1.5V
[36] SYS_HWPG

PCH/VGA

[7,40] GFX_PWRGD

+3V

iRST
20120217 reserve iRST function.

SW1
C66
*0.1u/10V_4

2
1

NBSWON#

3
4
5
6

IOAC_PCIERST#

2
4

Power Switch

1
3

[3,9] PCI_PLTRST#

R110
*100K/J_4

PCIERST# [26,28]

U13
*TC7SH08FU

Quanta Computer Inc.

R109
*100K/J_4

PROJECT : ZQK
Size

Document Number

Rev
1A

KBC IT8587
Date:
5

Monday, January 07, 2013

Sheet
1

34

of

46

VA2
VA1

PQ9
AOL1413

PR43
220K_4

24737_ACN

PC28
0.1u/50V_6

1
2
3

35
5

PR46
0_4

PC29
0.1u/50V_6

Power conn

PQ12
AOL1413

VIN

1
2
3
4

PR45
0.01/F_0612

PD1
SBR1045SP5-13
1

1
2
3

CN9

PD7
SMAJ20A

PC67
0.1u/50V_6

PC71
2200p/50V_6

PR105
33K/F_4

24737_ACP

PC31
2200p/50V_6
PD2
1N4148WS

PR41
220K_4

recommend 200mA at least.

PR44
0_4
PR104
10K_4

D/C# [34]
PR42
0_4

PC30
0.1u/50V_6

PQ8
IMD2AT108

2
PQ13
2N7002K

24737_ACP
24737_ACN
PR110
0_6

PR152
63.4K/F_4

PC99
0.1u/50V_6

PC98
0.1u/50V_6

24737_VCC

[34]

ACDET

REGN

16

24737_REGN

PC25
0.1u/25V_4
PR114
20_1206

ACIN

20

PD3
RB500V-40

VCC

PR116
0_6

PC89
0.47u/25V_6

BTST

17

PC174
2200p/50V_6

24737_BST
PC84
47n/50V_6

HIDRV
PHASE

PQ4
2N7002DW

+3VPCU

PC192
0.1u/50V_6

PGND
11

24737_BM#
PC122
*100p/50V_4

PR139
*10K_4

24737_CMPOUT

10

BATT_EN#

TEMP_MBAT

24737_CMPIN 4

PR115
100_4

SRN

12

PR75
0_4

24737_SRP
PC66
*680p/50V_6

PC48
PC55
PC52
2200p/50V_6 10u/25V_1206 10u/25V_1206

24737_SRN

24737_SRN
PR135
7.5_6

PC115
0.1u/25V_4

For battery reverse

+3V
PR156
100K/F_4

PC114
0.01u/25V_4

PR127
100_4
24737_BM# 2

H_PROCHOT# [3,34,40]

Pin10 ILIM=0.793V
Rsr = 0.01ohm

[34] ICMNT

MBDATA [34]

PR140
*0_4

PQ52
*2N7002K

REGN MAX voltage 6.5V

V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
=0.793V for 3.965A current limit

PR224
*100K_4

PR148
1.62K/F_4

MBCLK [34]
A

24737_SRP

PC92
47p/50V_4

3
PR134
*0_4

PR143
*100K_4

PR157
*100K_4

+3VPCU
PC86
*47p/50V_4

CMPIN

TEMP_MBAT [34]

PR129
1M_4

13

PR72
0_4

PC111
0.1u/25V_4

GND
GND
GND
GND
GND

PR130
100_4

BAT-V

21
22
23
24
25

8
7
6
5
4
3
2
10 1

PR85
*4.7_6

PC116
0.1u/25V_4

ILIM

IOUT

PQ47
MDV1595S
PR131
10_6

CMPOUT

50458-00801-V01

24737_ILIM

14

BAT-V

PR158
316K/F_4

24737_DL

BM#

SRP

PJ1

15

SCL

PR155
0_4

PR141
10K_4

PR76
0.01/F_0612
PL10
6.8uH_7X7X3

LCDRV
9

24737_LX

PU9
BQ24737RGRR

SDA

PR154
0_4
MBCLK

19

PQ46
MDV1528
4

BATT_EN#

[33] BATT_EN#

24737_DH

ACOK#

PR26
0_4
MBDATA

18

3
2
1

[34] SB_ACDC

[7] ACPRESENT
PR25
*0_4

PC72
4.7u/25V_8

PR32
100K_4

3
2
1

PR31
100K_4

VIN
PC85
1u/16V_6

ACN

24737_ACDET 6

ACP

PR153
10K/F_4

+3VPCU

PR33
*10K_4

PC96
0.1u/50V_6

PC112
68n/10V_4

24737_CMPOUT

PU6

2
TEMP_MBAT

CH1
VN
CH2

CH4
VP
CH3

6
5
4

MBDATA

PC113
100p/50V_4

+3VPCU

PQ51
2N7002K

Quanta Computer Inc.

MBCLK

PROJECT : ZQK

*IP4223-CZ6
Add ESD diode base on EC FAE suggestion

Size

Limit set on 60W/3.16A

4

Rev
1A

Charger(BQ24737RGRR)
Date:

Document Number

Sheet

Monday, January 07, 2013

1

35

of

46

MAIND

SYS_SHDN#

MAIND [5,37,41]

SYS_SHDN#

36

[3,27,41]

PR123
0_6
VL

+3VPCU

3V_LDO
PR230
10K/F_4

[34] SYS_HWPG

PD4
1PS302

PC110
0.1u/50V_6

+15V

+5V_S5

VIN

4.7u/6.3V_6

PC95

0.1u/25V_4
PC93

51225_VIN

12

3
2
1

PL14
2.2uH_7X7X3

VREG3

PQ50
MDV1595S

21
4

+
PC176
0.1u/50V_6

PC88
*680p/50V_6

RDSon=14mohm

PC181
220u/6.3V_6X4.2

PR122
10K/F_4

9/10 change

L(ripple current)
=(9-3.3)*3.3/(2.2u*0.355M*9)
~2.676A
Iocp=9-(2.676/2)=7.66A
Vth=(7.66A*14mOhm)+1mV=108.27mV
R(Ilim)=(108.27mV*8)/10uA
=86.614K
B

+5VPCU

+5VPCU

+3VPCU

PR97
*1M_6

MAIND

MAIND 4

S5D

PQ56
MDV1528Q

2
+5V_S5

PQ14
2N7002K
PC68
*2.2n/50V_4

PQ15
2N7002K

PQ19
MDV1528Q

PQ18
AO3404

3
2
1

PQ39
MDV1528Q

TDC : 1.5A
PEAK : 2A
Width : 80mil

+5V

TDC : 2.5A
PEAK : 3.4A
Width : 100mil

+3V

TDC : 1.7A
PEAK : 2.3A
Width : 80mil

+3V_S5

TDC : 1.2A
PEAK : 1.6A
Width : 50mil

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

SYSTEM 5V/3V (TPS51225)

Date:

PR125
6.49K/F_4
PR117
*4.7_6

22
3
2
1

GND

GND

51225_FB2

0.1u/50V_6

23

GND

GND

CS2

51225_DL2

1/F_6

3
2
1

PR93
1M_6

3
2
PQ17
2N7002K

10/11 change

11

PC82

+3VPCU

PR103
22_8

51225_SW2

PR118
0_6

PR126
22_8

PR108
1M_6

PR112

PC125
0.1u/50V_6

S5D

PQ16
2N7002K

51225_VBST2

OCP:9A

3
2
1

PR120
1M_6

51225_DH2

10/15 change

+3V_S5

10

+15V_ALWP
PR162
22_8

VREG5

2
PD5
1PS302

VIN

SYS_SHDN#

PR147
0_6

PC124
0.1u/50V_6

+15V

[34,41] S5_ON

GND

L(ripple current)
=(9-5)*5/(2.2u*0.3M*9)
=3.367A
Iocp=10-(3.367/2)=8.32A
Vth=(8.32A*14mOhm)+1mV=117.43mV
R(Ilim)=(117.43mV*8)/10uA
=93.944K

VO1

PC109
0.1u/50V_6

OCP:10A

GND

24

RDSon=14mohm

PC184
*680p/50V_6

VFB1
CS1

VFB2

51225_FB1

DRVL2

DRVL1

51225_CS2

15

PU8
TPS51225RUKR

SW 1

86.6K/F_4

51225_DL1

SW 2

PR227

18

1
2
3
PR138
10K/F_4

51225_SW1

VBST1

VCLK

1/F_6

14

PC193
0.1u/50V_6

9/10 change

17

EN2

VBST2

PQ54
MDV1595S

PR236
*4.7_6

51225_VBST1

+3VPCU

+3VPCU
3.3 Volt +/- 5%
TDC : 5.5A
PEAK : 7.5A
OCP : 9A
Width : 220mil

DRVH1

19

16

PC81
4.7u/25V_8

PQ48
MDV1528

DRVH2

51225_CS1

0.1u/50V_6

PR133
15K/F_4

51225_DH1
PR146

PC177
2200p/50V_6

EN1

51225_VCLK

PC108

PGOOD

20

97.6K/F_4

51225_EN1

PR232

1
2
3

VIN

13
4

PQ55
MDV1528

PL16
2.2uH_7X7X3

PC191
220u/6.3V_6X4.2

PR221
*100K/F_4

25

PR113
0_4

+5VPCU
5 Volt +/- 5%
TDC : 7A
PEAK : 9A
OCP : 10A
Width : 280mil

+5VPCU

PR144
0_4

PC187
2200p/50V_6

26

PC121
4.7u/25V_8

10u/6.3V_6

PC183
47u/25V_6X4.5

PC97

SYS_SHDN#
+

VIN

VIN

Monday, January 07, 2013

Sheet
1

36

of

46

TDC : 0.75A
PEAK : 1A
Width : 40mil

TDC : 0.38A
PEAK : 0.5A
Width : 20mil

37

+0.75V_DDR_VTT

PC64
10u/6.3V_6
D

PC65
10u/6.3V_6
D

+SMDDR_VREF

Close to IC
Greater than or equal 40mil

PC56
0.22u/10V_4
+5VPCU

[34] HWPG_1.5V

PC63
10u/6.3V_6

PC57
1u/10V_4
VIN

PGOOD

V5IN

PQ45
RJK03J6DPA

12

+1.5VSUS
1.5 Volt +/- 5%
TDC : 14A
PEAK : 18A
OCP : 20A
Width : 560mil

VLDOIN

3
VTT

1
VTTSNS

21

4
VTTGND

20

VTTREF

PAD

PR92
100K/F_4

PAD

22

+3V

TRIP

DRVL

VREF=1.8V

PAD
REF

26

REFIN

10/11 change

PGND

51216_SW

11

PC59
0.1u/50V_6

1
2
3

13

4
PC168
2200p/50V_4

PC61
4.7u/25V_8

PC60
4.7u/25V_8

+1.5VSUS
PL13
0.36uH_10X10X4

18

SW

15

51216_DRVH
PR86
2_6
51216_VBST

51216_DRVL

PR198
*4.7_6
10

4
+

1
2
3

51216_TRIP

MODE

GND

PR204
52.3K/F_4

VBST

PU5
TPS51216RUKR

14

PQ44
RJK03K5DPA

51216_MODE 19

PR205
200K/F_4

S5

PAD

16

23

51216_S5

PAD

PR94
0_4

DRVH

24

[34] SUSON

S3

PAD

17

25

51216_S3

VDDQSNS

PR96
*0_4

[31,34,38,41] MAINON

PC156
0.1u/50V_6

PC154
*680p/50V_6

+
PC165
330u/2.5V_6X4.2

PC173
330u/2.5V_6X4.2

51216_REFIN

51216_REF
PC54
0.1u/10V_4

PR91
0_6

+1.5VSUS

RDSon=4.3mohm

PR203
10K/F_4

Close to output cap

[34] +0.75V_ON
2

[5,36,41] MAIND

51216_S3

PR81
69.8K/F_4
PR89
*0_4

PC53
0.01u/25V_4

51216_S5

OCP=20A
L ripple current
=(19-1.5)*1.5/(0.36u*400k*19)
=9.594A
Vtrip=20-(9.594/2)*4.3mohm
=0.065372V
Rlimit=0.065372/10uA*8=52.297Kohm

Mode

Frequency

Discharge mode

200K

400K

Tracking Discharge

100K

300K

Tracking Discharge

S3

S5

S0

S3 (mainon off)

+1.5V

TDC : 0.38A
PEAK : 0.5A
Width : 20mil

+1.5VSUS

REF

VTT

ON

ON

ON

ON

ON

OFF

Quanta Computer Inc.

PROJECT : ZQK
Size

S4/S5

OFF

OFF

Document Number

Rev
1A

DDR 1.5V(TPS51216)

OFF
Date:

PQ41
AO3404

PR95
0_4

Monday, January 07, 2013

Sheet
1

37

of

46

38

VIN

PC129
2200p/50V_4

D1
D1
D1
51219_SW

10

51219_DL

Close to output cap

G1
9

S1/D2
8

PL6
0.68uH_7X7X3
51219_SW

G2

S2
S2
S2

7
6
5

1n/50V_4

1n/50V_4
PC19

PR173
*11K/F_4

+1.05V_VTT
1

PR4
*4.7_6

PR17
*100_4

+
PC132
0.1u/50V_6

PC134
330u/2V_7343

FDMS3660S
PC5
*680p/50V_6

51219_VSNS

51219_GSNS

51219_REFIN

PR18
10_4

PR14
0_4

PR15
10_4

PC13

PR172
0_4

+1.05V
1.05 Volt +/- 2%
TDC : 14A
PEAK : 17A
OCP : 20A
Width : 560mil

PQ25

PC11
0.1u/25V_6

12

PC17
0.01u/16V_4

PR170
*10K/F_4
0.01u/25V_4

OCP=20A
L ripple current
=(19-1.05)*1.5/(0.68u*500k*19)
=2.918A
Vtrip=20-(2.918/2)*4.3mohm
=0.07972V
Rlimit = 0.07972/10uA*8=63.781Kohm

PC10
0.1u/10V_4

PC131
4.7u/25V_8

RDSon 4.3mOhm

PC12

+3V_S5

PR10
2_6

13

PR9
0_6

VREF=2V
51219_REF

11

GND

COMP

PR175
64.9K/F_4

PC133
4.7u/25V_8

17
PAD

18
PAD

19
PAD

20

PGND
VREF

PR171
1K/F_4

DL

TRIP

PC14
1u/6.3V_4

PAD

MODE

PC8
*0.1u/10V_4

SW

51219_TRIP 6

BST
PU2
TPS51219RTER

V5

VSNS

51219_MODE 15

EN

51219_DH

DH

GSNS

51219_V5

PGOOD

PR169
0_4

14

REFIN

[31,34,37,41] MAINON

51219_EN

16

[34,39] HWPG_VTT

PAD

22

PR176
10_6

PAD

PR11
100K_4

21

+5V_S5

+3V

VCCP_SENSE [5]
VSSP_SENSE [5]
PR12
0_4

RC filter is for improve

Jitter performance.

PR13
*100_4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

+1.05V (TPS51219)
Date:
5

Monday, January 07, 2013

Sheet
1

38

of

46

39

+3V

PC166
0.1u/10V_4

PC167
10u/10V_8

PC58
10u/10V_8

+5V_S5
+VCCSA

19

PC169
0.1u/50V_6

PR208
1K_4

PR82
*33K/F_4

VOUT

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

51461_SW

PC50

PC49

PC51

PR202
100/F_4

SLEW
4

VREF

COMP

SW

AGND

10

PR201
0_4

51461_SLEW

PR209
1K_4

VID1

51461_MODE 6

25

SW

15

[5] VCCSA_VID1

SW

VID0

51461_VREF

14

[5] VCCSA_VID0

PR199 4.99K/F_4
3

PC170
*0.1u/10V_4

GND

PR210
0_4

PU12
TPS51463

EN

13

51461_EN

[34,38] HWPG_VTT

MODE

16

HWPG_VCCSA

PC158

SW

10u/6.3V_6

PGOOD

PL11
0.47uH_7X7X3
11

PC159

SW

51461_BST

10u/6.3V_6

V5FILT

12

PC160

BST

0.1u/50V_6

PGND

20

21

22

23

V5DRV

PGND

17

PGND

51461_FILT

VIN

18

PC172
1u/6.3V_4

VIN

PR211
0_6

PC161

PR90
*100K_4

VIN

24

+3V

[34]

+VCCSA
0.9 Volt +/- 2%
TDC : 3A
PEAK : 4A
Width : 120mil

PC171
2.2u/6.3V_6

51461_VOUT

VCCSA_SENSE [5]

PR200
*10K/F_4

PC164
0.01u/16V_4

PC162
0.22u/10V_4
PR84

0_6

PR87

0_6

PC163
3.3n/50V_4

VID0
A

VID1

+VCCSA

0.9V

0.85V

0.775V

0.75V

Quanta Computer Inc.

PROJECT : ZQK
Size

default 0.9V

Document Number

Rev
1A

VCCSA(TPS51463)
Date:
5

Monday, January 07, 2013

Sheet
1

39

of

46

40

+VCC_CORE
PR109
2.2/F_6

21

PR240
0_4

PAD

51650_CBST1

45

51650_CSW1

44

51650_CDL1

PR128
0_6

51650_CDH1

46

PC90
4.7u/6.3V_6

51650_V5DRV

47

PR102
10/F_6

51650_V5

43

1
2

PC178
2200p/50V_4

PC62
330u/2V_7343

0_4

PC155
0.1u/10V_4

PC157
10u/6.3V_6

PC80
4.7u/25V_8

+VCC_CORE
TDC : 16A
PEAK : 33A
OCP : 40A
Width : 1320mil

PR207
28.7K/F_4

PC69
*0.1u/25V_4

PC79
2.2u/6.3V_4

48

+VCC_CORE

VCORE Load Line :

2.9mV/A

Close with
phase1 inductor
for faster response

41
40
39
38
42

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65

CPWM3
36

49

GPWM2
35

PR137
10K/F_4

51650_CTHERM

PC76
0.1u/10V_4

51650_CCSP1

1
CTHERM

51650_CCSN1

CCSP1

CCSN1

7
CCSP2

CCSN2
GPWM1

GTHERM

PGND

51650_VBAT

PR206
100K/F_4_4250NTC

6.65K/F_4

51650_CCOMP

8
CCSP3

CCSN3

PC78
22n/16V_4

47p/50V_4

PR99

51650_CVFB

10
CCOMP

51650_CGFB

11

PR244
*10_4

34

PC105
*330p/50V_4

32

51650_GVFB

+VCC_GFX
B

51650_GPWM1

VDIO

51650_GTHERM

ALERT

GCSN2

20

CDH2

31

VR_SVID_DATA

VCLK
GCSP2

[5] VR_SVID_DATA

CBST2

30

19

CSW2

VR_HOT

GCSP1

VR_SVID_ALERT#

CDL2

29

[5] VR_SVID_ALERT#

CDL1

GPGOOD

26

PC175
1u/6.3V_4

PU7
TPS51650RSLR

51650_GCSP1

18

CSW1

GCSN1

VR_SVID_CLK

[5] VR_SVID_CLK

PC94
43p/50V_4

V3R3

CPGOOD

23

*0_4

CBST1

28

PR231

GSKIP

VR_ON

17

H_PROCHOT#

CDH1

37

DCR=1mOhm

TPAD1
TPAD2
TPAD3
TPAD4
TPAD5
TPAD6
TPAD7
TPAD8
TPAD9
TPAD10
TPAD11
TPAD12
TPAD13
TPAD14
TPAD15
TPAD16

16

0_4

GFX_PWRGD

12

GF-IMAX

15
51650_VRON

V5DRV

51650_GCSN1

33

CVFB

14
51650_GSKIP#

VBAT
V5

SLEW

GCOMP

[7,34]

51650_CCSN1
+5V_S5

GOCP-R

GGFB

24

GVFB

22

51650_GF-IMAX

27

13

51650_SLEW

CF-IMAX

25

51650_GOCP-R

[3,7] IMVP_PWRGD

[3,34,35]

COCP-R

51650_GGFB

PR216
*100K/F_4

PR235
1.91K/F_4

PR111
1.91K/F_4

PR223
*499/F_4

+3V_S5

VREF

2
51650_CF-IMAX

CGFB

PR107

Close to the
VR side.

+3V_S5

PC180
1u/6.3V_4

[34] VRON

PC70
*0.1u/25V_4

51650_VREF

PR218
75K/F_4

PR217
30K/F_4

PR220
75K/F_4

PR226
20K/F_4

PR228
30.1K/F_4

PR229
100K/F_4

51650_COCP-R

PC75

PR214
52.3K/F_4

PR213
200K/F_4

PR98
4.7K/F_4

PR225
*22.6K/F_4

PR132
200K/F_4

PR136
*0_4

51650_CCSP1

PR83

51650_VREF
51650_VREF

+3V

PC77
2200p/50V_6

S2
S2
S2
7
6
5

51650_VREF

+1.05V_VTT

PL12
0.24uH_7X7X4
1
2

PC91
15u/25V_7343

PQ49
FDMS3660S

8 G2

51650_CDL1

Close to the
CPU side.

51650_CSW1

16.9K/F_4

S1/D2
PC73
*0.01u/50V_4

2
1 G1

51650_CDH1
PR77
*10_4

PR88

0_4

PR215
187K/F_4

PR78

Parallel

PC182
4.7u/25V_8

[5] VSS_SENSE
D

PC83
0.22u/25V_6
51650_CSW1

PR101
2.2_6

0_4

PC179
0.1u/50V_6

PR79

D1
D1
D1

[5] VCC_SENSE

51650_CBST1

PC74
*330p/50V_4

PR80
*10_4

VIN

PR222
0_6
B

+3V
PC103
0.1u/10V_4

[5] VCC_AXG_SENSE
[5] VSS_AXG_SENSE

AXG
VIN

8
7
6
5
9
10
11

51650_CDL3

51650_GTHERM

51650_CTHERM

PC107
*0.1u/25V_4

VR_SVID_DATA

1
2

PC186
2200p/50V_4

PC118
4.7u/25V_8

+VCC_GFX

PR150

PR212
100K/F_4_4250NTC
51650_GCSN1
PR237
*0_4

VR_ON PU to 5V for test mode

Place NTC close to the

GFX_CORE Hot-Spot.

PC106
*0.1u/25V_4

Place NTC close to the

VCORE Hot-Spot.
Close to the
VR side.

Close with
AXG inductor

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

+VCC_CORE/+VGFX (TPS51650)
Date:

+VCC_GFX
TDC : 21.5A
PEAK : 33A
OCP : 38A
Width : 1320mil
GFX_CORE Load Line :
-3.9mV/A for GT2

PR234
*191K/F_4

PR233
100K/F_4_4250NTC

PR242
100K/F_4_4250NTC

VR_SVID_CLK
PC100
22n/16V_4

PR219
100K/F_4

DCR=1mOhm

PR241
26.1K/F_4

51650_GCSP1

PR100
15.8K/F_4

VR_SVID_ALERT#

51650_VRON

PC119
2200p/50V_6

7
6
5
+3V

PL15
0.24uH_7X7X4
2

PC123
330u/2V_7343

8 G2

PC190
10u/6.3V_6

PQ53
FDMS3660S

PR238
*0_4

PR142
15.8K/F_4

51650_CSW3

0_4

PC189
0.1u/10V_4

S1/D2

S2
S2
S2

1.7V
Thermal shutdown
setting 104C

1 G1

PR151

+5V_S5
PC120
1u/10V_4

TPS51601DRBR

Close to VR

PR121
*75/F_4

PR124
130/F_4

PR119
54.9/F_4

PR106
*0_4

PC87
0.1u/10V_4

+1.05V_VTT

PC101
15u/25V_7343

51650_CDH3
51650_CSW3

51650_VREF
+5V_S5

DRVH
SW
VDD
DRVL
PAD
PAD
PAD

14.3K/F_4

BST
SKIP
PWM
GND
PAD
PAD
PAD

51650_VREF

1
2
3
4
12
13
14

PR149
2.2_6

51650_GSKIP#
51650_GPWM1

D1
D1
D1

PU10

Close to the
CPU side.

PC117
4.7u/25V_8

PC188
0.22u/25V_6

PC185
0.1u/50V_6

51650_CBST3

5.49K/F_4

PR239
2.2/F_6

PR145

PC104
*0.01u/50V_4
PR245
*10_4

100p/50V_4

PR243
0_4

PC102

Parallel

Monday, January 07, 2013

Sheet
1

40

of

46

41

10/11 change

+1.8V
1.8 Volt +/- 5%
TDC : 0.9A
PEAK : 1.22A
Width : 40mil

+3VPCU

PC22
0.1u/25V_4
PU3

TPS54318RTER

VIN

PH

VIN

PH

VIN

PH

16
1

PR19
*100K/F_4

[34]
[31,34,37,38]

2
14

HWPG_1.8V

15

MAINON

PR21
0_4

8
PC20
1000p/50V_4

PR20
10K/F_4

BOOT

EN

VSNS

COMP

GND

RT/CLK

GND

SS

AGND

10
11

PL1
1uH_7X7X3

PC18
*100p/50V_4

PR178
121K/F_4

12
PR16

13
6

0_6

PR22
100K/F_4

PC15
0.1u/50V_6

3
4

R1

54318_VSNS

V0=0.8*(R1+R2)/R2

22
21
20
19
18
17

PR181
100K/F_4

PW RGD

PAD
PAD
PAD
PAD
PAD
PAD

PC24
10u/6.3V_6

+3V

+1.8V

PC16
0.01u/25V_4

PR23
78.7K/F_4

PC6
0.1u/25V_4

PC9
10u/6.3V_6

PC7
10u/6.3V_6

R2

PC21
1200p/50V_4

VIN

PD6
DA2J10100L

PR184
1M_6

Thermal protection

PQ31
AO3409

S5_ON 2

[34,36] S5_ON

PR183
0_6

PQ32
DTC144EUA
B

VL
SYS_SHDN#

[3,27,36]
VIN

PR185
200K_6

3
PC142
0.1u/50V_6

MAIND

MAINON

PR160
1M_4

PR186
200K/F_4

PR163
*100K/F_6

PQ21
2N7002K

PQ20
2N7002K

MAIND [5,36,37]

MAINON_G

PQ22
2N7002K

PQ23
2N7002K

PC126
*2200p/50V_4

PQ24
2N7002K

[3,5] MAINON_G

PQ34
2N7002K

PU11A
BA10393F

PR166
1M_4

PR165
22_8

2
PQ33
2N7002K

PR164
22_8

+15V

PR159
22_8

+1.5V

S5_ON

PR161
1M_4

+5V

+3V

2.469V

PR189
10K_6_NTC

PC141
0.1u/50V_6

PR188
1.74K/F_4

PR187
200K/F_4

VL

10/11 change

LM393_PIN2

5
6

PU11B
BA10393F

Quanta Computer Inc.

PROJECT : ZQK

For EC control thermal protection (output 3.3V)

Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

+1.8V/Discharge/Thermal
5

Sheet
1

41

of

46

42

10/1 Change
+1.5V_GFX

PR57
1M_4

+1.5VSUS

+15V

PR190
22_8

PR40
1M_4

VIN

PQ36
RJK03K5DPA

dGPU_D2

1
2
3

PR64
0_4
2

2
PC143
*2.2n/50V_4

PQ10
2N7002K

PR59
100K_4

PQ35
2N7002K

PQ11
PDTC143TT

+1.5V_GFX
TDC : 4.43A
PEAK : 5.9A
Width : 180mil

PC35
*1u/10V_4

[20] FBVDDQ_EN

+1.5V_GFX

PR60
1M_4

10/5 Reserve switching power for +1.5V_GFX

OCP=7.5A
L ripple current
=(19-1.5)*1.5/(2.2u*290k*19)
=2.165A
Vtrip=7.5-(2.165/2)*14mohm
=0.0898V
Rlimit=0.0898/10uA*8=71.873Kohm

+1.05V_GFX

PR37
1M_4

+1.05V_VTT

+15V

PR39
22_8

VIN

PR38
1M_4
dGPU_D1

PQ3
MDV1528Q
3
2
1

PR34
0_4

PR36
1M_4

PR35
100K_4

PQ6
2N7002K

+1.05V_GFX

PC27
*2.2n/50V_4

+1.05V_GFX
TDC : 2.3A
PEAK : 3A
Width : 100mil

PC26
*1u/10V_4

PQ7
2N7002K
1

PQ5
PDTC143TT

[20] 1.05V_GFX_EN

+3VPCU
+3V_GFX

PR177
1M_4

+15V

PR182
22_8

PR24
1M_4

10/1 Change

PQ30
2N7002K

PQ29
2N7002K

PQ1
2N7002K

PQ2
AO3404

+3V_GFX

PC23
*2.2n/50V_4

1
PR174
100K_4

PR180
1M_4

[9] DGPU_PWR_EN

dGPU_D

PR179
0_4

VIN

+3V_GFX
TDC : 0.76A
PEAK : 1A
Width : 40mil

PC135
*1u/10V_4

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

+VGPU_CORE(UP1642PQAG)
Date:
5

Monday, January 07, 2013

Sheet
1

42

of

46

+3V

43

+5V_S5

PHASE1

PSI

DSBL/ISEN1

PGOOD

LGATE1

1642_ISEN1

23

1642_LGATE1

17
18

1642_UGATE2
PR66
2.2/F_6
1642_BOOT2

19

1642_PHASE2

1642_REFIN

1642_COMP

12

1642_FB

11
10

BOOT2

REFADJ

PHASE2

REFIN

TALERT#/ISEN2

COMP

LGATE2

FB

GND/PW M3

FBRTN

TSNS/ISEN3

PC45
0.22u/25V_6

PR74
10K/F_4

14

GPU_THAL#

20

1642_LGATE2

22
13

G1

S1/D2

1642_PHASE2
PL9

G2

FDMS3660S

RDSon 2.2mohm

1642_TSNS

DRC=0.78mohm
+VGPU_CORE

0.36uH_10X10X4

Add 3 GND VIAs

for thermal pad

PR58
0_4

C1
1

PR195
10K_4

PR56
18K/F_4

R4

PC145
2700p/50V_4

R6
PQ40
2N7002K

PC39
PR63
4700p/25V_4 16.2K/F_4

R3

PC44
*0.1u/25V_4

PR192
5.1K/F_4

PR49
2K/F_4

PR51
20K/F_4

VREF

PR73
2.2_6

UGATE2

D1
D1
D1

1642_REFADJ

VID

S2
S2
S2

PQ42

7
6
5

1642_VREF

2
VIN

PAD

R1

25

PC36
1u/6.3V_4

PR50
20K/F_4

R2

1642_VID

PC41
330u/2V_7343

15

RDSon 2.2mohm

PC144
10u/6.3V_6

1642_PHASE1

FDMS3660S

PC34
1000p/50V_6

1642_BOOT1

24

16

EN

7
6
5

10K_4

1642_PGOOD

BOOT1

1642_UGATE1

PC146
0.1u/10V_4

S2
S2
S2
1642_PSI

PVCC

+VGPU_CORE
1 Volt +/- 5%
TDC : 45A
PEAK : 58A
OCP : 70A
Width : 1800mil

PC149
330u/2V_7343

0_4

PC153
10u/6.3V_6

[19] VGPU_PWMVID

PR52

UGATE1

+VGPU_CORE

PC42
4.7u/25V_8

0_4

DRC=0.78mohm

PC152
0.1u/10V_4

PR70

21

1642_EN

TON

0.36uH_10X10X4

PC150
4.7u/25V_8

[20] VGPU_PWRGD

PC46
15u/25V_3528

PR55
2.2_6

PC40
*0.1u/25V_4

PC37
0.1u/25V_4

PR194
100K_4
C

1642_PVCC

PR67

*1K/F_4
0_4

PR191

PR47

91642_PHASE1
PL8

G2

+3V
1642_TON

[19] VGPU_PSI

G1
S1/D2

PU4
UP1642RQAG

PC148
4.7u/25V_8

PR54
10K/F_4

PC38
4.7u/25V_8

PC33
0.22u/25V_6

+3V_S5

PC147
0.1u/50V_6

[10,20] DGPU_VRON

D1
D1
D1

PR196
66.5K/F_4

PR53
2.2/F_6

PC151
0.1u/50V_6

0_4

PQ37

PC47
1000p/50V_6

PR48

PR62
2.2_6

PR193
*10K_4

VIN

R5

1642_FBRTN

+3V
+VGPU_CORE

PR68
10K/F_4
GPU_THAL#

PC43
33p/50V_4
PR28
*100_4

PR27
0_4

1642_PVCC
PR61
1K/F_4
1642_VREF

1642_TSNS

1642_FBRTN

[16] GPU_VSSP_SENSE
PR29
0_4

1642_ISEN1
PR71
15.8K/F_4

GPU_VCCP_SENSE_R

[16] GPU_VCCP_SENSE

GPU_THAL# [19]

PR69
10K/F_4

PR197
100K/F_4_4250NTC
PR30
*100_4

PR65
*1.33K/F_4

Place NTC close to the

VGPU Hot-Spot.

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Rev
1A

+VGPU_CORE(UP1642PQAG)
Date:
5

Monday, January 07, 2013

Sheet
1

43

of

46

44

DGPU_PWROK

GPIO17

+3VPCU

MOSFET
GPIO3

+3V_GFX

DGPU_PWR_EN

+1.5V_VRAM

PCH
+VGPU_CORE

VIN

GPIO35

DGPU_VRON

MOSFET
+1.5VSUS

PWM
uP1642PQAG

+1.5V_GFX
+1.05V_GFX

+1.05V_VTT

VGPU_PWRGD
EC_FB_CLAMP

FBVDDQ_EN

HWPG_1.5VGFX

MOSFET
1.05V_GFX_EN

Power Sequence
B

+3V_GFX
+VGPU_CORE
+1.5V_GFX
IFPx_IOVDD (+1.05V_GFX)
PEX_VDD (+1.05V_GFX)
A

All rails must be powered off within 10 ms from the first rail powering off.

Quanta Computer Inc.

PROJECT : ZQK
Size

Document Number

Date:

Monday, January 07, 2013

Rev
1A

Power Sequence
5

Sheet
1

44

of

46

39
SLP_S3#(SUSB#):
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components
when system transitions to S3, S4, or S5 states.

4
NBSWON#
5

+5VPCU

S5_ON
(S5D)

PQ39

2
1

VIN

BATT Charger
PU9

+3VPCU

MOS

+3VPCU

AC Adapter

6
+3V_S5
D

PQ18

Always System power

Regulator

Battery

+5V_S5

MOS

SLP_S4#(SUSC#):
S4 Sleep Power plane control - Assertion of SLP_S4# shuts power off to non-critical components
when system transitions to S4 or S5 state.

30ms

+5VPCU

7
PCH_RSMRST#

PU8
10

RSMRST#

8
DNBSWON#

3
SUSON(SUSD)
13

PWRBTN#

SUSC#

SLP_S4#

MAINON(MAIND)

EC
16
+3VPCU

MAIND

SUSB#

SLP_S3#

19

+3V

MDV1528Q-PQ19

VRON

22
23

PCH

PWROK_EC
SYS_PWROK
+5VPCU

MAIND

SYS_PWROK

+5V

MDV1528Q-PQ56
C

100ms

MAIND

+1.5VSUS

+1.5V

AO3404-PQ41

+3VPCU

MAINON

14
+1.8V

VR-PU3
PROCPWRGD

VIN

MAINON

PLTRST#

+1.05V_VTT

VR-PU2
HWPG_VTT
VIN

Regulator
PU2

+VCCSA 17

24

25

H_PWRGOOD

SYS_HWPG

PCI_PLTRST#

18
15

HWPG_1.8V
21

+VCC_CORE

19

VIN

VRON
(From EC)

15

20

VR-PU7

HWPG_VTT

HWPG

+VCC_GFX

UNCOREPWRGOOD

HWPG_VCCSA

RESET#

IMVP_PWRGD
HWPG_1.5V

CPU
21

IMVP_PWRGD

VIN

SUSON

12

MAINON
Regulator
PU5

+0.75V_DDR_VTT
+SMDDR_VREF
+1.5VSUS
11
Quanta Computer Inc.
PROJECT : ZQK
Size

Document Number

Rev
1A

power sequence block diagram

Date:
5

Monday, January 07, 2013

1

Sheet

45

of

46

Model

Date

CHANGE LIST
1.Change C774 from 0.1uF to 39pF for ESD

1203

2.Add C841~C850 39pF for ESD

3.Change U19,U21,U23,U26,U43,U46,U48,U49 PN from AKD5JGST404 to AKD5JGST407
1.Change LED1/LED2 PNBEB00028ZA0FPled19-123-y2st1d-c30-2t-4p

1205

2.Change R383/R392 from 47 ohm to 56 ohm

1206

1.Change SW2 PN DHPATE2CK03FPsw-ate-2ck-v-tr-4p

1.Delete PL2/PL3/PL4/PL5

1210

2.Add RTC charge circiut and modify CN14 PN and FP (DFHS02FS032/ml1220-smt)

3.Update CN4 FP to "dp-adis0022-p001a-20p-smt"
1.Add mSATA re-driver circuit

1211
1212

2.Change CN22 PN & FP as same as CN13

1.Modify Hole4 FP to H-TC197BC142D142P2
2.Change mSATA redriver power rail to +1.5V

1213

1.Add R828~R831 for co-layout

2.Add N14M-GE binary strap setting information

1214

1.Change USB DB power to 4 pins

2.Change CN4 PN to DFTD20FR001
1.Update Hole6/Hole17/Hole22 FP
2.Add C866 by FAE suggestion

3.Change C706 from 10uF to 4.7uF

1217

4.Add pull down 100K by EC-Anda command (R832/R833/R834)

5.Change TEMP_MBAT fromPJ1 pin 5 to pin 6 (BATT_EN#) , then pin 6 is NC pin
6.Un stuff PR96
7.Add R835 and change R785 to 5.1M ohm
8.Mark R746 to NSW@ due to pin18 of U7 has internal +3V

1219

ZQK

1.SUSLED# power from +3V_S5 to +3V_PCU (for Deep S3)

2.Change eDP connector CN8 PN and FP (DFHS40FS095 / gs12401-1011-40p-r-nh-smt)

1220

1.Add net PCH_SUSWARN# connect to Pin78 of EC (GPJ2)

2.Add net PCH_SUSACK# connect to Pin79 of EC (GPJ3)

1221
1224

1.Change PR191 PU voltage from +3V to +3V_S5

1.Unstuff PR28/PR30
2.Reserve R837

1225

1.Change PU4 PN from AL001642000 to AL001642001

1226

1.Change U15 PN from AJ085870F03 to AJ085870F04

1228

1.Co-layout mSATA re-driver IC-U51 (PS8521A & ASM1466)

1.Unstuff PR191 (Already PU on HW side)

0102

2.Reserve R842/R843

0103

1.SWAP EC pinBATLED1# change to pin32 ; ME_WR# change to pin25

0104

1.Change U38 PN from AJ0QPRG0T03 to AJSLJ8C0T05

0107

1.Update Hole6/Hole17 FP
2.Update Pad1 PN to FBZRK011010
3.Update Hole4 PN to FBAJ2005010

Quanta Computer Inc.

Document Number

Rev
1A

Change list
Date:

Monday, January 07, 2013

Sheet
5

PROJECT MODEL :

DOC NO.

PROJECT : ZQK
Size

46

of

ZQK

PART NUMBER:

APPROVED BY:

DATE:

DRAWING BY:

REVISON:

46
4