Introduction
Fig 3.1 Circuit structure for the HOA CMOS driver-receiver ASF-LC, with Vddh =1.0 V,
Vbus=2 V, Vtn=0.21 V, and |Vtp|=0.25 V.
In this circuit the driver is designed using a source
follower. The receiver may be a simple inverter or
level converter circuit. PMOS conducts when at point
X1 when the value is zero, and the above PMOS is
always on as it is connected to ground, and this
Fig 3.2 Circuit structure for the low-high offset symmetric (LHOS) CMOS driver-receiver
DDCDB, with Vdd =1.0 V, Vtn =0.21 V and Vtp=0.25 V
Fig 3.3 Circuit structure for the LHOS CMOS driver-receiver version I (MJ-SIB), with
Vddh =1.0 V, Vtn=0.21 V, and |Vtp|=0.25 V.
Driver circuit
When the input is fed to the inverter, it increases the
fan-out so as to drive three other gates i.e NOR,
NAND and NOT gates. The logic gates connected
before the DDC topology helps maintaining the input
signal within the stable limits. The condition can be
explained as follows: inmj=0, MU11 is ON and
hence the drain and gate of MU10 are at equal
Fig 3.4 Circuit structure for the LHOS CMOS driver-receiver version II (MJDB), with
Vdd=1.0 V, Vtn=0.21 V, and |Vtp|=0.25 V.
4. RESULTS
HOA
PI Model
Split R- model
Values
Delay
Power
Power-
Delay
Power
Power-
of R
(n sec)
Results
Delay
(n sec)
Results
Delay
(m W)
Product
(m W)
Product
(K )
1
58.1
4.280
(p W)
248.668
15
2.196
(p W)
32.940
69.9
2.846
198.935
14.2
3.826
54.329
10
89
8.840
786.760
31.3
7.326
229.303
15
109.7
7.707
845.457
Waveform distorted
20
Waveform distorted
Waveform distorted
25
Waveform distorted
Waveform distorted
30
Waveform distorted
Waveform distorted
DDCD
37.2
1.034
38.464
31.7
0.295
9.351
36.6
1.244
45.530
32
1.239
39.648
10
39
1.149
44.811
32.5
0.647
21.027
15
45.1
1.659
74.820
33
0.894
29.502
20
47.3
1.805
85.376
33.5
0.946
31.691
25
48
1.994
95.712
34
1.174
39.916
30
50
2.005
100.12
34.4
1.293
44.447
MJ SIB
1
7.3
2.275
16.607
3.7
3.507
12.975
9.8
1.981
19.413
5.2
1.941
10.093
10
16.6
1.377
22.858
6.2
1.762
10.924
15
23
1.095
25.185
7.6
1.816
13.801
20
25.4
0.965
24.531
9.2
1.616
14.867
25
30.6
3.222
98.593
11.35
1.459
16.559
15
1.334
20.010
30
Waveform distorted
MJ DB
10.8
2.220
23.976
5.8
1.014
5.881
15.3
1.965
30.064
7.3
1.888
13.782
10
26.8
1.333
35.724
8.75
1.707
14.936
15
37
1.056
39.072
10.84
1.492
16.173
20
40.7
0.942
38.339
14.1
1.338
18.865
25
44.8
3.264
146.227
17.7
1.203
21.293
30
45.9
3.083
141.509
21.1
1.104
23.294
5. COMPARATIVE EVALUATION
Fig.
5.1 Four
schemes
Value of Resistor
Fig. 5.2 Four schemes implemented with split R-
model
implemented
witResistor
model
Value of
Value of Resistor
AUTHORS
Shubha B Baravani
Dept. of Electronics and Communication
Gogte Institute of Technology, Belgaum
Karnataka, India
shubha_baravani07@rediffmail.com
7. REFERENCES
[1]. H. Zhang, V. George, and J. M. Rabaey, LowSwing on-chip signaling techniques:
Effectiveness and robustness,
IEEE Trans. Very Large Scale Integr. (VLSI)
Syst.
[2]. M. Ferretti and P. A. Beerel, Low swing
Signaling using a dynamic diode-connected
driver, in Proc. Solid-State Circuits Conf.,
Villach, Austria.
[3]. E. Kusse and J. M. Rabaey, Low-energy
Embedded FPGA structures, in Proc. Int.
Symp.Low Power Electron. Des.
[4]. A. Rjoub and O. Koufopavlou, Efficient drivers,
receivers and repeaters for low power