Digital Electronics and Design with VHDL, Volnei A.

Pedroni, ElsevierMorgan Kaufmann, 2008

Digital Electronics and Design with VHDL

Volnei A. Pedroni
ElsevierMorgan Kaufmann, 2008

Samples of VHDL Codes Presented in the Examples

Below are some of the VHDL codes from the examples in Part II of the book (Chapters 19-25).

VHDL code from Example 19.1 (Buffered multiplexer)

---------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------------ENTITY buffered_mux IS
PORT (a, b, c, d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sel: IN INTEGER RANGE 0 TO 3;
ena: IN STD_LOGIC;
y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END buffered_mux;
---------------------------------------------------ARCHITECTURE myarch OF buffered_mux IS
SIGNAL x: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
x <= a WHEN sel=0 ELSE --Mux
b WHEN sel=1 ELSE
c WHEN sel=2 ELSE
d;
y <= x WHEN ena='1' ELSE -Tristate buffer
(OTHERS => 'Z');
END myarch;
----------------------------------------------------

VHDL code from Example 19.7 (Carry-ripple adder)

-------- The component: ---------------------------ENTITY full_adder IS
PORT (a, b, cin: IN BIT;
s, cout: OUT BIT);
END full_adder;
---------------------------------------------------ARCHITECTURE full_adder OF full_adder IS
BEGIN
s <= a XOR b XOR cin;
cout <= (a AND b) OR (a AND cin) OR (b AND cin);
END full_adder;
----------------------------------------------------

-------- Main code: -----------------------------------------ENTITY carry_ripple_adder IS

GENERIC (N : INTEGER := 8); --number of bits

Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
PORT (a, b: IN BIT_VECTOR(N-1 DOWNTO 0);
cin: IN BIT;
s: OUT BIT_VECTOR(N-1 DOWNTO 0);
cout: OUT BIT);
END carry_ripple_adder;
--------------------------------------------------------------ARCHITECTURE structural OF carry_ripple_adder IS
SIGNAL carry: BIT_VECTOR(N DOWNTO 0);
-----------------------------------------------COMPONENT full_adder IS
PORT (a, b, cin: IN BIT; s, cout: OUT BIT);
END COMPONENT;
-----------------------------------------------BEGIN
carry(0) <= cin;
gen_adder: FOR i IN a'RANGE GENERATE
FA: full_adder PORT MAP (a(i), b(i), carry(i), s(i), carry(i+1));
END GENERATE;
cout <= carry(N);
END structural;
---------------------------------------------------------------

VHDL code from Example 20.1 (Address decoder)

--------- Code for N=3 and WHEN: ---------------ENTITY address_decoder IS
PORT (x: IN BIT_VECTOR(2 DOWNTO 0);
y: OUT BIT_VECTOR(7 DOWNTO 0));
END address_decoder;
-------------------------------------------------ARCHITECTURE address_decoder OF address_decoder IS
BEGIN
y <= "00000001" WHEN x="000" ELSE
"00000010" WHEN x="001" ELSE
"00000100" WHEN x="010" ELSE
"00001000" WHEN x="011" ELSE
"00010000" WHEN x="100" ELSE
"00100000" WHEN x="101" ELSE
"01000000" WHEN x="110" ELSE
"10000000";
END address_decoder;
---------------------------------------------------------- Code for arbitrary N: ----------------ENTITY address_decoder IS
GENERIC (N: INTEGER := 3); --can be any value
PORT (x: IN INTEGER RANGE 0 TO 2**N-1;
y: OUT BIT_VECTOR(2**N-1 DOWNTO 0));
END address_decoder;
-------------------------------------------------ARCHITECTURE address_decoder OF address_decoder IS
BEGIN
gen: FOR i IN x'RANGE GENERATE
y(i) <= '1' WHEN i=x ELSE '0';
END GENERATE;
END address_decoder;
--------------------------------------------------

VHDL code from Example 20.2 (BCD-to-SSD converter)

------- Package: -----------------------------------------------

Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
PACKAGE my_functions IS
FUNCTION bcd_to_ssd (SIGNAL input: INTEGER) RETURN BIT_VECTOR;
END my_functions;
---------------------------------------------------------------PACKAGE BODY my_functions IS
FUNCTION bcd_to_ssd (SIGNAL input: INTEGER) RETURN BIT_VECTOR IS
VARIABLE output: BIT_VECTOR(6 DOWNTO 0);
BEGIN
CASE input IS
WHEN 0 => output:="1111110"; --decimal 126
WHEN 1 => output:="0110000"; --decimal 48
WHEN 2 => output:="1101101"; --decimal 109
WHEN 3 => output:="1111001"; --decimal 121
WHEN 4 => output:="0110011"; --decimal 51
WHEN 5 => output:="1011011"; --decimal 91
WHEN 6 => output:="1011111"; --decimal 95
WHEN 7 => output:="1110000"; --decimal 112
WHEN 8 => output:="1111111"; --decimal 127
WHEN 9 => output:="1111011"; --decimal 123
WHEN OTHERS => output:="1001111";
--letter "E" (Error) -> decimal 79
END CASE;
RETURN output;
END bcd_to_ssd;
END my_functions;
----------------------------------------------------------------

------Main code:-------------------------------USE work.my_functions.all;

-----------------------------------------------ENTITY bcd_to_ssd_converter IS
PORT (x: IN INTEGER RANGE 0 TO 9;
y: OUT BIT_VECTOR(6 DOWNTO 0));
END bcd_to_ssd_converter;
-----------------------------------------------ARCHITECTURE decoder OF bcd_to_ssd_converter IS
BEGIN
y <= bcd_to_ssd(x);
END decoder;
------------------------------------------------

VHDL code from Example 21.2 (Carry-lookahead adder)

------- 4-bit carry-lookahead adder: -------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------ENTITY carry_lookahead_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cin: IN STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: OUT STD_LOGIC);
END carry_lookahead_adder;
--------------------------------------------------ARCHITECTURE structure OF carry_lookahead_adder IS
SIGNAL G, P, c: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
------- Computation of G and P:
G <= a AND b;
P <= a XOR b;
------- Computation of carry:
c(0) <= cin;
c(1) <= G(0) OR

Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
(P(0) AND cin);
c(2) <= G(1) OR
(P(1) AND G(0)) OR
(P(1) AND P(0) AND cin);
c(3) <= G(2) OR
(P(2) AND G(1)) OR
(P(2) AND P(1) AND G(0)) OR
(P(2) AND P(1) AND P(0) AND cin);
cout <= G(3) OR
(P(3) AND G(2)) OR
(P(3) AND P(2) AND G(1)) OR
(P(3) AND P(2) AND P(1) AND G(0)) OR
(P(3) AND P(2) AND P(1) AND P(0) AND cin);
------- Computation of sum:
sum <= P XOR c;
END structure;
---------------------------------------------------

------- Main code: -------------------------------LIBRARY ieee;

USE ieee.std_logic_1164.all;
--------------------------------------------------ENTITY big_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cin: IN STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cout: OUT STD_LOGIC);
END big_adder;
--------------------------------------------------ARCHITECTURE big_adder OF big_adder IS
SIGNAL carry: STD_LOGIC_VECTOR(8 DOWNTO 0);
----------------------------------------------COMPONENT carry_lookahead_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cin: IN STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: OUT STD_LOGIC);
END COMPONENT;
----------------------------------------------BEGIN
carry(0) <= cin;
gen_adder: FOR i IN 1 TO 8 GENERATE
adder: carry_lookahead_adder PORT MAP (
a(4*i-1 DOWNTO 4*i-4),
b(4*i-1 DOWNTO 4*i-4),
carry(i-1),
sum(4*i-1 DOWNTO 4*i-4),
carry(i));
END GENERATE;
cout <= carry(8);
END big_adder;
---------------------------------------------------

VHDL code from Example 22.4 (Fibonacci series generator)

----------------------------------------------------ENTITY fibonacci IS
GENERIC (N: INTEGER := 16); --number of bits
PORT (clk, rst: IN BIT;
fibo_series: OUT INTEGER RANGE 0 TO 2**N-1);

Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
END fibonacci;
----------------------------------------------------ARCHITECTURE fibonacci OF fibonacci IS
SIGNAL a, b, c: INTEGER RANGE 0 TO 2**N-1;
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
b <= 1;
c <= 0;
ELSIF (clk'EVENT AND clk='1') THEN
c <= b;
b <= a;
END IF;
a <= b + c;
END PROCESS;
fibo_series <= c;
END fibonacci;
-----------------------------------------------------

VHDL code from Example 22.5 (Frequency meter)

---------------------------------------------ENTITY freq_meter IS
GENERIC (fclk: INTEGER := 5; --clock freq.
fxmax: INTEGER := 15); --max fx
PORT (clk, x: IN BIT;
test: OUT BIT;
fx: OUT INTEGER RANGE 0 TO fxmax);
END freq_meter;
---------------------------------------------ARCHITECTURE behavioral OF freq_meter IS
SIGNAL twindow: BIT;
SIGNAL temp: INTEGER RANGE 0 TO fxmax;
BEGIN
----- Time window: -----------------------PROCESS (clk)
VARIABLE count: INTEGER RANGE 0 TO fclk;
BEGIN
IF (clk'EVENT AND clk='1') THEN
count := count + 1;
IF (count=fclk) THEN
twindow <= '1';
ELSIF (count=fclk+1) THEN
twindow <= '0';
count := 0;
END IF;
END IF;
END PROCESS;
------ Counter for x: --------------------PROCESS (x, twindow)
VARIABLE count: INTEGER RANGE 0 TO 20;
BEGIN
IF (twindow='1') THEN
count := 0;
ELSIF (x'EVENT AND x='1') THEN
count := count + 1;
END IF;
temp <= count;
END PROCESS;
-------- Register: ------------------------PROCESS (twindow)
BEGIN
IF (twindow'EVENT AND twindow='1') THEN

Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
fx <= temp;
END IF;
END PROCESS;
test <= twindow;
END behavioral;
------------------------------------------------

VHDL code from Example 23.3 (Car alarm, version 1)

---------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------------------ENTITY car_alarm IS
PORT (clk, rst, remote, sensors: IN STD_LOGIC;
siren: OUT STD_LOGIC);
END car_alarm;
---------------------------------------------------------ARCHITECTURE fsm OF car_alarm IS
TYPE alarm_state IS (disarmed, armed, intrusion);
ATTRIBUTE enum_encoding: STRING;
ATTRIBUTE enum_encoding OF alarm_state: TYPE IS "sequential";
SIGNAL pr_state, nx_state: alarm_state;
SIGNAL flag: STD_LOGIC;
BEGIN
----- Flag: ----------------------------PROCESS (remote, rst)
BEGIN
IF (rst='1') THEN
flag <= '0';
ELSIF (remote'EVENT AND remote='0') THEN
flag <= NOT flag;
END IF;
END PROCESS;
----- Lower section: -------------------PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
pr_state <= disarmed;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
----- Upper section: ------------------PROCESS (pr_state, flag, remote, sensors)
BEGIN
CASE pr_state IS
WHEN disarmed =>
siren <= '0';
IF (remote='1' AND flag='0') THEN
nx_state <= armed;
ELSE
nx_state <= disarmed;
END IF;
WHEN armed =>
siren <= '0';
IF (sensors='1') THEN
nx_state <= intrusion;
ELSIF (remote='1' AND flag='1') THEN
nx_state <= disarmed;
ELSE
nx_state <= armed;
END IF;
WHEN intrusion =>

Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
siren <= '1';
IF (remote='1' AND flag='1') THEN
nx_state <= disarmed;
ELSE
nx_state <= intrusion;
END IF;
END CASE;
END PROCESS;
END fsm;
----------------------------------------------------------

VHDL code from Example 24.3 (Type I testbench for an adder)

----- design file (adder.vhd): --------------ENTITY adder IS
PORT (a, b: IN INTEGER RANGE 0 TO 255;
sum: OUT INTEGER RANGE 0 TO 511);
END adder;
---------------------------------------------ARCHITECTURE adder OF adder IS
BEGIN
sum <= a + b;
END adder;
-------------------------------------------------- test file (test_adder.vhd): -----------ARCHITECTURE test_adder OF test_adder IS
----- component declaration: ------------COMPONENT adder IS
PORT (a, b: IN INTEGER RANGE 0 TO 255;
sum: OUT INTEGER RANGE 0 TO 511);
END COMPONENT;
----- signal declarations: --------------SIGNAL a: INTEGER RANGE 0 TO 255;
SIGNAL b: INTEGER RANGE 0 TO 255;
SIGNAL sum: INTEGER RANGE 0 TO 511;
BEGIN
----- component instantiation: ----------dut: adder PORT MAP (a=>a, b=>b, sum=>sum);
----- signal a: -------------------------PROCESS
BEGIN
a <= 0;
WAIT FOR 50 ns;
a <= 150;
WAIT FOR 50 ns;
a <= 200;
WAIT FOR 50 ns;
a <= 250;
WAIT FOR 50 ns;
END PROCESS;
----- signal b: -------------------------PROCESS
BEGIN
b <= 0;
WAIT FOR 75 ns;
b <= 120;
WAIT FOR 75 ns;
b <= 240;
WAIT FOR 50 ns;
END PROCESS;
END test_adder;
----------------------------------------------

Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008