USE ieee.std_logic_1164.all;
ENTITY part1 IS
PORT ( SW
LEDG
LEDR
END part1;
: OUT STD_LOGIC);
END COMPONENT;
BEGIN
PROCESS (Clock, Reset)
BEGIN
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY flipflop IS
PORT ( D, Clock, Resetn, Setn : IN STD_LOGIC;
Q
: OUT STD_LOGIC);
END flipflop;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF (Resetn = '0') THEN -- synchronous clear
Q <= '0';
ELSIF (Setn = '0') THEN -- synchronous set
Q <= '1';
ELSE
Q <= D;
END IF;
END IF;
END PROCESS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- A sequence detector FSM
-- SW0 is the active low synchronous reset, SW1 is the w input, and KEY0 is the
clock.
-- The z output appears on LEDG0, and the state is indicated on LEDR8..0
ENTITY part2 IS
PORT ( SW
KEY
LEDG
LEDR
END part2;
END CASE;
END PROCESS; -- state_table
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF (Resetn = '0') THEN -- synchronous clear
y_present <= A;
ELSE
y_present <= y_next;
END IF;
END IF;
END PROCESS;
END Behavior;