TECHNOLOGY: VLSI

DOMAIN : IEEE TRANSACTIONS ON CORE VLSI

CODE PROJECT TITLES YEAR

V9CV06 FAULT SECURE ENCODER AND DECODER FOR NANO- 2009
MEMORY APPLICATIONS
V9CV07 NOVEL AREA-EFFICIENT FPGA ARCHITECTURES FOR FIR 2009
FILTERING WITH SYMMETRIC SIGNAL EXTENSION
V9CV08 CUSTOM FLOATING-POINT UNIT GENERATION FOR 2009
EMBEDDED SYSTEMS
V9CV09 DESIGN AND SYNTHESIS OF PROGRAMMABLE LOGIC BLOCK 2009
WITH MIXED LUT AND MACROGATE
V8CV11 AREA-EFFICIENT ARITHMETIC EXPRESSION EVALUATION 2008
USING DEEPLY PIPELINED FLOATING POINT CORES USING
VHDL
V8CV12 DESIGN OF REVERSIBLE FINITE FIELD ARITHMETIC CIRCUITS 2008
WITH ERROR DETECTION
V7CV13 REGISTER FOR PHASE DIFFERENCE BASED LOGIC 2007
V7CV14 DESIGNING EFFICIENT ONLINE TESTABLE REVERSIBLE 2007
ADDER WITH NEW REVERSIBLE GATE

TECHNOLOGY: VLSI
DOMAIN : IEEE TRANSACTIONS ON LOW POWER AND
FPGA

CODE PROJECT TITLES YEAR

V9LP01 BZ-FAD: A LOW-POWER LOW-AREA MULTIPLIER BASED ON 2009
SHIFT-AND-ADD ARCHITECTURE
V9LP02 THE ARISE APPROACH FOR EXTENDING EMBEDDED 2009
PROCESSORS WITH ARBITRARY HARDWARE
ACCELERATORS
V9LP03 VARIATION-AWARE LOW-POWER SYNTHESIS 2009
METHODOLOGY FOR FIXED-POINT FIR FILTERS
V8LP04 LOW POWER DESIGN OF PRECOMPUTATION-BASED 2008
CONTENT-ADDRESSABLE MEMORY
V8LP05 L-CBF: A LOW-POWER, FAST COUNTING BLOOM FILTER 2008
ARCHITECTURE USING VHDL
V8LP06 LOW-POWER LEADING-ZERO COUNTING AND ANTICIPATION 2008
LOGIC FOR HIGH-SPEED FLOATING POINT UNITS
V7LP07 FPGA IMPLEMENTATION OF LOW POWER PARALLEL 2007
 MULTIPLIER
V7LP08 A LOW-POWER MULTIPLIER WITH THE SPURIOUS POWER 2007
SUPPRESSION TECHNIQUE
V0LP09 SHIFT INVERT CODING FOR LOW POWER VLSI 2004
Low-Power Leading-Zero Counting and Anticipation Logic for High- 2008
Speed Floating Point Units
controllable arbitrary integer frequency divider based onVHDL. 2009

An area efficient universal cryptography processor for smart cards

A pico-blazed based embedded system for monitor application 2008
FPGA based power efficient chanelised for software defined radio 2007
Improvement of the Orthogonal code convolution capabilities using 2007
FPGA implementation
A BIST ckt for DLL fault detection. 2008
Low power leading zero counting and anticipation logic for high speed 2008
floating point unit
Hybrid type cam design for both power and performance 2008
Improvement of the orthogonal code convolution capabilities using 2007
FPGA implementation

TECHNOLOGY: VLSI
DOMAIN : IEEE TRANSACTIONS ON IMAGE
PROCESSING

CODE PROJECT TITLE YEAR

V8IP01 LOW POWER HARDWARE ARCHITECTURE FOR VBSME 2008
USING PIXEL TRUNCATION
V7IP02 A PROCESSOR-IN-MEMORY ARCHITECTURE FOR 2007
MULTIMEDIA COMPRESSION
V7IP03 SHIFT-REGISTER-BASED DATA TRANSPOSITION FOR COST- 2007
EFFECTIVE DISCRETE COSINE TRANSFORM

TECHNOLOGY: VLSI
DOMAIN : IEEE TRANSACTIONS ON SECURITY AND
COMMUNICATION

CODE PROJECT TITLES YEAR

V9SC01 ASYNCHRONOUS PROTOCOL CONVERTERS FOR TWO-PHASE 2009
 DELAY-INSENSITIVE GLOBAL COMMUNICATION
V9SC02 FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION 2008
ALGORITHM
V9SC03 DESIGN OF ADVANCED ENCRYPTION STANDARD USING 2008
VHDL
V7SC04 A ROBUST UART ARCHITECTURE BASED ON RECURSIVE 2007
RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE
V6SC05 COMPACT HARDWARE DESIGN OF WHIRLPOOL HASHING 2006
CORE

TECHNOLOGY: VLSI
DOMAIN : IEEE TRANSACTIONS ON TESTING

CODE PROJECT TITLE YEAR

V9TE01 BIT-SWAPPING LFSR AND SCAN-CHAIN ORDERING: A NOVEL 2009
TECHNIQUE FOR PEAK- AND AVERAGE-POWER REDUCTION
IN SCAN-BASED BIST
V9TE02 LOW-POWER SCAN TESTING FOR TEST DATA COMPRESSION 2009
USING A ROUTING-DRIVEN SCAN ARCHITECTURE
V8TE03 ENHANCEMENT OF FAULT INJECTION TECHNIQUES BASED 2008
ON THE MODIFICATION OF VHDL CODE