begin

piso : process (clk,reset,load,din) is

variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
temp := din ;
elsif (rising_edge (clk)) then
dout <= temp(3);
temp := temp(2 downto 0) & '0';
end if;
end process piso;

signal DST:STD_LOGIC_VECTOR (15 downto 0):=(others=>'0');

signal dato,alto:STD_LOGIC:='0';
begin
process(reset,clk)
begin
if reset='1' then
DST<=(others=>'0');
dato<='0';
alto<='0';
elsif rising_edge(clk) then
if inicio='1' then
dato<='1';--inicia bit
alto<='1';--se detiene bit
DST<=entrada_paralelo;
else
dato<=DST(15);
alto<='0';
DST<=DST(14 downto 0)&alto;
end if;
end if;
end process;
salida_serie<=dato;
end Behavioral;