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A

Compal confidential

Schematics Document
Mobile Penryn uFCPGA with Intel
Cantiga_PM+ICH9-M core logic
3

LA-4082P Vader Discrete (NB9P-GS,NB9M-GE)


2009-01-07

Rev 1.0_2F

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS, MB A4082
Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

of

61

Compal confidential

Montevina Consumer Discrete


Dual-Core Thermal Sensor
EMC1402
Quad-Core Thermal Sensor
EMC1403

VRAM DDR2
256/512MB

CK505

Mobile Penryn

P4

72QFN

Clock Generator
SLG8SP553V

uFCPGA-478 CPU

P22,23,24,25

128 bits

P15

P4, 5, 6

Fan conn

P4

H_A#(3..35)

Discrete
Nvidia NB9P-GE
Nvidia NB9M-GE

FSB

H_D#(0..63)

667/800/1066 MHz 1.05V

DDR2 SO-DIMM X2
DDR2 667MHz 1.8V

P18,19,20,21

LVDS Panel
Interface
CRT
2

Intel Cantiga MCH

P13, 14

Dual Channel

FCBGA 1329

P17

USB conn x3

P7, 8, 9, 10, 11, 12

USB2.0*7

DMI X4

BT Conn

C-Link

P38

P38

PCI-E BUS*5 & USB2.0 *3


Mini-Card*3

New Card

WLAN & Robson &TV


USB2.0*2
PCIE*3
P32,35

USB2.0*1
PCIE*1
P32

P17

Azalia

Intel ICH9-M

P31

Touch Screen Conn

P44

USB Camera

Realtek 8111C
(GLAN)

P38

P16

Support V1.3

HDMI

BANK 0, 1, 2, 3

Discrete

P42

SATA Master-2
SATA Slave

mBGA-676

Flash Memory Card /


1394 Controller
JM380
CardReader/1394

FPR Conn

SATA Master-1

Audio CKT

SATA Slave

AMP & Audio Jack

Codec_IDT9271B7

P26,27,28,29

P34

MIC & SPKR


TPA6020

P35

Sub-woofer & EQ

USB2.0 X1

MDC

P33

P37

RJ45/11 CONN
3

LPC BUS

P31

SATA HDD Connector

Discrete only

P33

SATA 2nd HDD


Option Connector

ACCELEROMETER-1
P39

5 in1 Slot

ENE
KB926

P33

ACCELEROMETER-2

Dock

P30

USB2.0*1
RGB

SATA ODD Connector

RJ45

P30

P40

SPDIF

P39

CIR

e-SATA Combo Connector


Int.KBD

Touch Pad CONN.

RTC CKT.
P41

P30

1394 port

LED

P36

USB2.0*1 & SATA*1

P38

MIC*1

P40

P41

LINE-OUT*1

P27

SPDIF

SPI

P42

SPI ROM
25LF080A P39

Capsense switch Conn


P41
4

K/B backlight Conn


P41

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DC/DC Interface CKT.

2006/03/10

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P43

SCHEMATICS, MB A4082
Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

of

61

Voltage Rails

O MEANS ON

X MEANS OFF

+5VS

SMBus Control Table

+3VS

SOURCE

+1.5VS

power
plane
+1.8V

+5VALW

+0.9V

SMB_EC_CK1

+VCCP

SMB_EC_DA1

+CPU_CORE

SMB_EC_CK2

+B

SMB_EC_DA2
+3VALW

+VGA_CORE

State

SMB_CK_CLK1

+2.5VS

SMB_CK_DAT1

+1.8VS

DDC2_CLK

+1.2VS

DDC2_DATA

INVERTER

SERIAL
EEPROM

BATT

Thermal
Sensor

SODIMM

CLK CHIP

MINI
CARD

LCD

Sensor
board

KB926

KB926

ICH9

NB9M

+0.9VGA

USB
assignment:

PCIe
assignment:

USB-1 Right side

PCIe-2 X

USB-2 Left side(with ESATA)

PCIe-3 WLAN

USB-3 Dock

PCIe-4 New Card

USB-4 Camera

USB-5 WLAN

PCIe-5 Card
reader
PCIe-6 GLAN (Marvell)

S0

S1

USB-0 Right side

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery


don't exist

Symbol Note :

PCIe-1 TV tuner/WWAN/Robeson

: means Analog Ground


@ : means just reserve , no build
DEBUG@ : means just reserve
for debug.

USB-6 Bluetooth

USB-7 Finger Printer

USB-9 Express
card
USB-10 X

: means Digital Ground

USB-8 MiniCard(WWAN/TV)

USB-11 X

EC SM Bus1 address
Device
Smart Battery
24C16

HEX

Address

16H

0001 011X

A0H

1010 000X

CAP BOARD -- Cypress

38H

CAP BOARD -- ST

b0H

G-sensor

EC SM Bus2 address
Device
CPU EMC1402
VGA

HEX

Address

4CH

1001 1000b

4DH

1001 1010b

0011 1001(read)
0011 1010(write)

I2C / SMBUS ADDRESSING


DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2006/03/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS, MB A4082
Rev
G

401540

Date:

Thursday, January 08, 2009

Sheet

of

61

ITP-XDP Connector
+VCCP

QC@ R2128
1
QC@ R2129
1
QC@ R2130
1
QC@ R2131
1
QC@ R2132
1
QC@ R2133
1
QC@ R2134
1
QC@ R2125
2

JCPUA

D5
C6
B4
A3

STPCLK#
LINT0
LINT1
SMI#

XDP_BPM2#1
XDP_BPM2#0
H_THERMDA2_R
H_THERMDC2_R
XDP_BPM2#2

M4
N5
T2
V3
B2
D2
QC@ +H_GTLREF2
D22
R2127 1
2 0_0402_5% D3
1
2
1
2 0_0402_5% F6
+VCCP
QC@ R53
QC@ R54
51_0402_1%
QC@ R2088
H_THERMDA2
H_THERMDC2
QC@ R2089

0_0402_5%
1
2
1
2
0_0402_5%

H_BR0#

IERR#
INIT#

D20
B3

H_IERR#
H_INIT#

LOCK#

H4

H_LOCK#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

HIT#
HITM#

G6
E4

H_HIT#
H_HITM#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

CONTROL

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

H_BR0# 7

THERMTRIP#

R732

54.9_0402_1%

XDP_TDO

R733

54.9_0402_1%

XDP_BPM#5

R734

54.9_0402_1%

XDP_TRST#

R792

54.9_0402_1%

XDP_TCK

R737

54.9_0402_1%

MV1 Change value to 55 ohm

H_LOCK# 7
H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

MV-1 Remove XDP connector

H_HIT# 7
H_HITM# 7

QC@
U78

+3VS

Delete H_PROCHOT# off-page due to


VR doesn't have it's input pin @08/31
XDP_DBRESET# 28

R7

2 56_0402_1%

H_THERMDA_R
H_THERMDC_R

R8
R9

1
1

2 0_0402_5%
2 0_0402_5%

C7

H_THERMTRIP#

R2126
100_0402_1%
QC@

RSVD[01]/BPM_2#[1]
RSVD[02]/BPM_2#[0]
RSVD[03]/THRMDA_2
RSVD[04]/THRMDC_2
RSVD[05]/BPM_2#[2]
RSVD[06]
RSVD[07]/GTLREF_2
RSVD[08]/TDO_M
RSVD[09]/TDI_M

XDP_TMS

H_INIT# 27

H_PROCHOT#

A22
A21

54.9_0402_1%

Place TP with a
GND 0.1" away

+VCCP
H_THERMDA
H_THERMDC

H_THERMTRIP# 7,27,40

CLK_CPU_BCLK

BCLK[0]
BCLK[1]

This shall place near CPU

D21
A24
B25

H CLK

0125 Change value to 51 ohm

10/08 follow Intel suggestion to change value

PROCHOT#
THERMDA
THERMDC

R731

T1

XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

THERMAL

H_THERMDA
QC@ C2114
H_THERMDC
1
2
2200P_0402_50V7K
H_THERMDA2
QC@ C2115
1
2 H_THERMDC2
2200P_0402_50V7K

QC@
C2113
+3VS

C1
DC@

CLK_CPU_BCLK 15

DC@
C2 1

0125 For Quad-core CPU

CLK_CPU_BCLK#

+3VS

CLK_CPU_BCLK# 15

VDD

SMCLK

10

SMB_EC_CK2

DP1

SMDATA

SMB_EC_DA2

DN1

ALERT#

DP2

THERM#

DN2

GND

THERM#

EMC1403-1-AIZL-TR_MSOP10
DC@ U55

VDD

SMCLK

SMB_EC_CK2

H_THERMDA

DP

SMDATA

SMB_EC_DA2

H_THERMDC
2
2200P_0402_50V7K
THERM#

DN

ALERT#

THERM#

GND

R10
1
2
10K_0402_5%

SMB_EC_CK2 20,40
SMB_EC_DA2 20,40

1
2
10K_0402_5%
R2140

+3VS

MV-1 Add R for 2nd


source thermal source

EMC1402-1-ACZL-TR_MSOP8

H_THERMDA, H_THERMDC routing


together, Trace width / Spacing = 10 / 10
mils

Address:100_1100

PWM Fan Control circuit

DC_RESERVED/QC

+5VS

Penryn

CONN@
JP2

+VCCP

H_THERMDA2, H_THERMDC2 routing


together, Trace width / Spacing = 10 / 10
mils

@
R12
56_0402_5%

D1
RB751V_SOD323

C3
4.7U_0805_10V4Z

C4
0.1U_0402_16V4Z

1
2
5
6

OCP# 28

D Q1

@ D2

G
SI3456BDV-T1-E3_TSOP6

S
4

RLZ5.1B_LL34

40 FAN_PWM

+VCCP

@ R45
100K_0402_5%

R1
56_0402_5%

@ R51

2 1
B

BSS138_SOT23~D
@ Q4

10K_0402_5%

10K_0402_5%
@
R49

C
@ Q3

H_IERR#

2
G
S

1
2

GND
GND

+FAN

OCP#
3
1
@ Q2
MMBT3904_NL_SOT23-3
+VCCP

1
2

H_PROCHOT#

2/3Vtt

1
2

3
4

Floating

+3VS

R44
QC@
2K_0402_5%

0V

Quad core (QC)

+H_GTLREF2

QC@
R43
1K_0402_5%

GTLREF2

GND

2 2

GTLREF_C

CPU
Dual core (DC)

1
2

ACES_88231-02001

1025 For Support Dual core and Quad core

+VCCP

+VCCP

XDP_TDI

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

0.1U_0402_16V4Z

H_STPCLK#
H_INTR
H_NMI
H_SMI#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#

F1

BR0#

XDP_BPM2#3 6

A6
A5
C4

H_DEFER#
H_DRDY#
H_DBSY#

1K_0402_5%

Change value in 5/02

H_ADS# 7
H_BNR# 7
H_BPRI# 7

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_A20M#
H_FERR#
H_IGNNE#

H5
F21
E1

ICH

27 H_A20M#
27 H_FERR#
27 H_IGNNE#

H_ADS#
H_BNR#
H_BPRI#

DEFER#
DRDY#
DBSY#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

H1
E2
G5

ADS#
BNR#
BPRI#

ADDR GROUP_1

7 H_ADSTB#1

K3
H2
K2
J3
L1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

27
27
27
27

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

XDP/ITP SIGNALS

7 H_REQ#0
7 H_REQ#1
7 H_REQ#2
7 H_REQ#3
7 H_REQ#4
7 H_A#[17..35]

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP_0

7 H_ADSTB#0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

@ R730
1

XDP_DBRESET#

51_0402_1%
XDP_BPM#3
2
51_0402_1%
XDP_BPM#2
2
51_0402_1%
XDP_BPM#1
2
51_0402_1%
XDP_BPM#0
2
51_0402_1%
XDP_BPM2#0
2
51_0402_1%
XDP_BPM2#1
2
51_0402_1%
XDP_BPM2#2
2
51_0402_1%
XDP_BPM2#3
1

0.1U_0402_16V4Z

7 H_A#[3..16]

+3VS

0125 For Quad-core CPU

2006/02/13

Issued Date

E
MMBT3904_NL_SOT23-3

Compal Electronics, Inc.

Compal Secret Data

Security Classification
GTLREF2 6

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

of

61

+VCC_CORE

E5
B5
D24
D6
D7
AE6

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

H_DPRSTP# 7,27,51
H_DPSLP# 27
H_DPWR# 7
H_PWRGOOD 27
H_CPUSLP# 7
H_PSI# 51

Penryn

* Route the TEST3 and TEST5 signals through


a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

R17

Resistor placed within 0.5"


of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.

CPU_BSEL0

166

200

266

R18

R19

R20

DC@ R52 1

2 0_0402_5%

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]/BR1#
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21 +VCCPA
+VCCPB
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VCCSENSE 51

VSSSENSE

AE7

VSSSENSE

VSSSENSE 51

+VCCP
R13
1
1
R14

2 0_0402_5%
2 0_0402_5%

1
+ C5
330U_D2E_2.5VM_R7
2

+1.5VS
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

51
51
51
51
51
51
51

1
C6
2

0.01U_0402_16V7K

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

COMP0
COMP1
COMP2
COMP3

R26
U26
AA1
Y1

DATA GRP 2

COMP[0]
COMP[1]
COMP[2]
COMP[3]

MISC

27.4_0402_1%

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

54.9_0402_1%

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

27.4_0402_1%

+V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

54.9_0402_1%

2 1K_0402_5%
2 1K_0402_5%
T2
T3
T4
T5
T6
15 CPU_BSEL0
15 CPU_BSEL1
15 CPU_BSEL2

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

1
1

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

@ R15
@ R16

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

JCPUC

7 H_DSTBN#1
7 H_DSTBP#1
7 H_DINV#1

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

DATA GRP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

DATA GRP 3

7
7
7
7

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP 0

+VCC_CORE

H_D#[32..47] 7

JCPUB
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

7 H_D#[0..15]

10U_0805_6.3V6M

1
C7
2

Near pin B26


B

Penryn
.

1025 For Support Dual core and Quad core

Length match within 25 mils.


The trace width/space/other
is 20/7/25.

+VCCP

R21
1K_0402_1%

+VCC_CORE

+V_CPU_GTLREF

TEST4

@ C2125
0.1U_0402_16V4Z

R23
2K_0402_1%

0125 Place C close to the CPU_TEST4 pin.


Make sure CPU_TEST4 routing is reference
to GND and away from other noisy signals.

2 100_0402_1%

VCCSENSE

R24

2 100_0402_1%

VSSSENSE

Close to CPU pin within


500mils.

Close to CPU pin


AD26 within
500mils.

R22

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

of

61

+VCC_CORE

5
1

Place these
capacitors on L8
(North
side,Secondary
Layer)

DC@
R2055 1

2
0_0402_5%

DC@
R2033 1

GTLREF2
2
0_0402_5%

10U_0805_6.3V6M

C9
10U_0805_6.3V6M

C10
10U_0805_6.3V6M

C11
10U_0805_6.3V6M

C12
10U_0805_6.3V6M

C13
10U_0805_6.3V6M

C14
10U_0805_6.3V6M

C15
10U_0805_6.3V6M
D

+VCC_CORE

JCPUD
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

C8

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[001]
VSS[082]
VSS[002]
VSS[083]
VSS[003]
VSS[084]
VSS[004]
VSS[085]
VSS[005]
VSS[086]
VSS[006]
VSS[087]
VSS[007]
VSS[088]
VSS[008]
VSS[089]
VSS[009]
VSS[090]
VSS[010]
VSS[091]
VSS[011]
VSS[092]
VSS[012]
VSS[093]
VSS[013]
VSS[094]
VSS[014]
VSS[095]
VSS[015]
VSS[096]
VSS[016]
VSS[097]
VSS[017]
VSS[098]
VSS[018]
VSS[099]
VSS[019]
VSS[100]
VSS[020]
VSS[101]
VSS[021]
VSS[102]
VSS[022]
VSS[103]
VSS[023]
VSS[104]
VSS[024]
VSS[105]
VSS[025]
VSS[106]
VSS[026]
VSS[107]
VSS[027]
VSS[108]
VSS[028]/RSVD_0
VSS[109]
VSS[029]
VSS[110]
VSS[030]
RSVD_1/VSS[111]
VSS[031]
VSS[112]
VSS[032]
VSS[113]
VSS[033]
VSS[114]
VSS[034]
VSS[115]
VSS[035]
VSS[116]
VSS[036]
VSS[117]
VSS[037]
VSS[118]
VSS[038]
VSS[119]
VSS[039]
VSS[120]
VSS[040]
VSS[121]
VSS[041]
VSS[122]
VSS[042]
VSS[123]
VSS[043]
VSS[124]
VSS[044]
VSS[125]
VSS[045]/GTLREF_C
VSS[126]
VSS[046]
VSS[127]
VSS[047]
VSS[128]
VSS[048]
RSVD_2/VSS[129]
VSS[049]
VSS[130]
VSS[050]
VSS[131]
VSS[051]
VSS[132]
VSS[052]
VSS[133]
VSS[053]
VSS[134]
VSS[054]
VSS[135]
VSS[055]
VSS[136]
VSS[056]
VSS[137]
VSS[057]
VSS[138]
VSS[058]
VSS[139]
VSS[059]
VSS[140]
VSS[060]
VSS[141]
VSS[061]
VSS[142]
VSS[062]
VSS[143]
VSS[063]
VSS[144]
VSS[064]
VSS[145]
VSS[065]
VSS[146]
VSS[066]
BPM_2#[3]/VSS[147]
VSS[067]
VSS[148]
VSS[068]
VSS[149]
VSS[069]
VSS[150]
VSS[070]
VSS[151]
VSS[071]
VSS[152]
VSS[072]
VSS[153]
VSS[073]
VSS[154]
VSS[074]
VSS[155]
VSS[075]
VSS[156]
VSS[076]
VSS[157]
VSS[077]
VSS[158]
VSS[078]
VSS[159]
VSS[079]
VSS[160]
VSS[080]
VSS[161]
VSS[081]
VSS[162]
VSS[163]

5
1

Place these
capacitors on L8
(North
side,Secondary
Layer)

C16
10U_0805_6.3V6M

C17
10U_0805_6.3V6M

C18
10U_0805_6.3V6M

C19
10U_0805_6.3V6M

C20
10U_0805_6.3V6M

C21
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C23
10U_0805_6.3V6M

+VCC_CORE

5
1

Place these
capacitors on L8
(North
side,Secondary
Layer)

C24
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C26
10U_0805_6.3V6M

C27
10U_0805_6.3V6M

C28
10U_0805_6.3V6M

C29
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

C31
10U_0805_6.3V6M

+VCC_CORE

DC@
R2056

2
0_0402_5%

Place these
capacitors on L8
(North
side,Secondary
Layer)

C32
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

C34
10U_0805_6.3V6M

C35
10U_0805_6.3V6M

C36
10U_0805_6.3V6M

C37
10U_0805_6.3V6M

C38
10U_0805_6.3V6M

C39
10U_0805_6.3V6M
C

Mid Frequence Decoupling

ESR <= 1.5m ohm


Capacitor >
1980uF

Near CPU CORE regulator


+VCC_CORE

DC@
R2057

2
0_0402_5%

330U_D2E_2.5VM_R7

1
C40
330U_D2E_2.5VM_R7

C41

1
+

@ C42

330U_D2E_2.5VM_R7

1
C43

+
2

330U_D2E_2.5VM_R7
B

DC@ R2054
XDP_BPM2#3
1
2
0_0402_5%

Inside CPU center cavity in 2 rows

+VCCP

5
1

C45
0.1U_0402_10V6K

C46
0.1U_0402_10V6K

C47
0.1U_0402_10V6K

C48
0.1U_0402_10V6K

C49
0.1U_0402_10V6K

C50
0.1U_0402_10V6K

Penryn
.

1025 For Support Dual core and Quad core


A

GTLREF2

GTLREF2 4

XDP_BPM2#3

XDP_BPM2#3 4

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

of

61

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

+H_VREF

A11
B11

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

2 10K_0402_5%

PM_EXTTS#1

R33

2 10K_0402_5%

CLKREQ#_7

R34

2 10K_0402_5%

5
5
5
5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

5
5
5
5

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

4
4
4
4
4

H_RS#0 4
H_RS#1 4
H_RS#2 4

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

0.1U_0402_16V4Z

18,26,31,32,33,35 PLT_RST#
4,27,40 H_THERMTRIP#
28,51 DPRSLPVR

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
THERMTRIP#
DPRSLPVR

1 @
C55
2

+1.8V

+V_DDR_MCH_REF generated by DC-DC

1
2

C59

221_0603_1%
2
1

1
1

R41
10K_0402_1%

C57
2

R48

+V_DDR_MCH_REF
0.1U_0402_16V4Z

R47

13,14 +V_DDR_MCH_REF
+H_SWNG
0.1U_0402_16V4Z

C58

100_0402_1%
2
1

0.1U_0402_16V4Z

24.9_0402_1%
2
1

1K_0402_1%
1
2
2K_0402_1%
2
1

R46

R40

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

BC28
AY28
AY36
BB36

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

BA17
AY16
AV16
AR13

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

BD17
AY17
BF15
AY13

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP
SM_RCOMP#

BG22
BH21

SMRCOMP
SMRCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

BF28
BH28

SMRCOMP_VOH
SMRCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

AV42
AR36
BF17
BC36

+V_DDR_MCH_REF
SM_PWROK
SM_REXT
TP_SM_DRAMRST#

R29
B7
N33
P32
AT40
AT11
T20
R32

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

13
13
14
14

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

13
13
14
14

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

13
13
14
14

M_ODT0
M_ODT1
M_ODT2
M_ODT3
R28
R29

13
13
14
14

+1.8V

2 80.6_0402_1%
2 80.6_0402_1%

1
1

Follow Design Guide


For Cantiga: 80.6ohm

B38
A38
E41
F41

1009 Follow Design Guide


R30
1
R31
1
T30 PAD

2 0_0402_5%
2 499_0402_1%

1015 Follow Design Guide

F43
E43

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AE41
AE37
AE47
AH39

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AE40
AE38
AE48
AH40

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AE35
AE43
AE46
AH42

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AD35
AE44
AF46
AH43

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

B33
B32
G33
F33
E33

T31
T32
T33
T34
T35

GFX_VR_EN

C34

T36

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

AH37
AH36
AN36
AJ35
AH34

PEG_CLK
PEG_CLK#

13
13
14
14

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15
C

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

28
28
28
28

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

28
28
28
28

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

28
28
28
28

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

28
28
28
28

+VCCP

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
+CL_VREF

R36
1K_0402_1%

CL_CLK0 28
CL_DATA0 28
M_PWROK 28,40
CL_RST# 28

0621 add CLK and DAT for DVI


DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

N28
M28
G36
E36
K36
H36

CLKREQ#_7
MCH_ICH_SYNC#

TSATN#

B12

TSATN#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

B28
B30
B29
C29
A28

T37
T38

C56
0.1U_0402_16V4Z

R37
499_0402_1%

2
CLKREQ#_7 15
MCH_ICH_SYNC#

56_0402_5%
1
2
R42

28

*R37*Follow Intel
feedback
+VCCP

Delete Off-page
@1028

0906 delete

0830 Add pull-up and pull-down resistor.

CANTIGA ES_FCBGA1329

Near B3 pin

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

within 100 mils from NB

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

NC

H_RCOMP

R38
10K_0402_1%

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

PM

28 PM_BMBUSY#
5,27,51 H_DPRSTP#
13 PM_EXTTS#0
14 PM_EXTTS#1
28,40 PM_PWROK
R943
1
2
R35
1
2 100_0402_5%
0_0402_5%

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

+VCCP

+H_VREF

RESERVED
RESERVED
RESERVED
RESERVED

AR24
AR21
AU24
AV20

CLK

15 MCH_CLKSEL0
15 MCH_CLKSEL1
15 MCH_CLKSEL2

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

R32

5
5
5
5

+VCCP

R39

T26
T27
T28
T29

BG23
BF23
BH18
BF18

PM_EXTTS#0

Layout Note:
V_DDR_MCH_REF trace
width and spacing is 20/20.

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

RESERVED

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

DMI

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

CANTIGA ES_FCBGA1329

Route H_SCOMP and H_SCOMP# with trace width,


spacing and impedance (55 ohm) same as FSB data
traces

AY21

+3VS

H_AVREF
H_DVREF

layout note:

T24
R27
1K_0402_1%

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

H_RS#_0
H_RS#_1
H_RS#_2

H_CPURST#
H_CPUSLP#

SMRCOMP_VOL

AP24
AT21
AV24
AU20

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

RESERVED
RESERVED
RESERVED

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

B15
K13
F13
B13
B14

T21
T22
T23

B31
B2
M1

DDR CLK/ CONTROL/COMPENSATION

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

L9
M8
AA6
AE5

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

20% of 1.8V VCC_SM

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

R26
3.01K_0402_1%

L10
M7
AA5
AE6

R25
1K_0402_1%

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

C52

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

0.01U_0402_25V7K

J8
L3
Y13
Y1

80% of 1.8V VCC_SM

C54

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

SMRCOMP_VOH

0.01U_0402_25V7K

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

2.2U_0603_6.3V4Z
C51

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

C12
E11

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

+1.8V

T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20

GRAPHICS VID

H_RESET#
H_CPUSLP#

4 H_RESET#
5 H_CPUSLP#

H_SWING
H_RCOMP

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

ME

C5
E3

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

CFG

+H_SWNG
H_RCOMP

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

MISC

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

HOST

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6

RSVD

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

2.2U_0603_6.3V4Z
C53

U57A

5 H_D#[0..63]

U57B

H_A#[3..35] 4

HDA

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

of

61

14 DDR_B_D[0..63]

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

SA_RAS#
SA_CAS#
SA_WE#

BB20
BD20
AY20

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_BS0 13
DDR_A_BS1 13
DDR_A_BS2 13
DDR_A_RAS# 13
DDR_A_CAS# 13
DDR_A_WE# 13

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

DDR_A_MA[0..14]

13

13

13

13

CANTIGA ES_FCBGA1329

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

BD21
BG18
AT25

MEMORY

SA_BS_0
SA_BS_1
SA_BS_2

DDR_A_DM[0..7]

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

DDR

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U57E

SYSTEM

U57D

DDR

13 DDR_A_D[0..63]

SB_BS_0
SB_BS_1
SB_BS_2

BC16
BB17
BB33

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

SB_RAS#
SB_CAS#
SB_WE#

AU17
BG16
BF14

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_BS0 14
DDR_B_BS1 14
DDR_B_BS2 14
DDR_B_RAS# 14
DDR_B_CAS# 14
DDR_B_WE# 14

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

DDR_B_MA[0..14]

14

14

14

14

CANTIGA ES_FCBGA1329

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

of

61

Strap Pin Table


U57C

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

H47
E46
G40
A40

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

H48
D45
F40
B40

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

A41
H38
G37
J37

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

B42
G38
F37
K37

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

LVDS

M29
C44
B43
E37
E38
C41
C40
B37
A37

H24

TV_RTN

C31
E32

TV_DCONSEL_0
TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32
J32
J29
E29
L29

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

VGA

@ R2138
1
2
0_0402_5%

TVA_DAC
TVB_DAC
TVC_DAC

TV

@ R2137
1
2
0_0402_5%

F25
H25
K25

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

C1289
C1290
C1291
C1292
C1293
C1294
C1295
C1296
C1297
C1298
C1299
C1300
C1301
C1302
C1303
C1304

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXN0 18
PEG_M_TXN1 18
PEG_M_TXN2 18
PEG_M_TXN3 18
PEG_M_TXN4 18
PEG_M_TXN5 18
PEG_M_TXN6 18
PEG_M_TXN7 18
PEG_M_TXN8 18
PEG_M_TXN9 18
PEG_M_TXN10 18
PEG_M_TXN11 18
PEG_M_TXN12 18
PEG_M_TXN13 18
PEG_M_TXN14 18
PEG_M_TXN15 18

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

C1305
C1306
C1307
C1308
C1309
C1310
C1311
C1312
C1313
C1314
C1315
C1316
C1317
C1318
C1319
C1320

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXP0 18
PEG_M_TXP1 18
PEG_M_TXP2 18
PEG_M_TXP3 18
PEG_M_TXP4 18
PEG_M_TXP5 18
PEG_M_TXP6 18
PEG_M_TXP7 18
PEG_M_TXP8 18
PEG_M_TXP9 18
PEG_M_TXP10 18
PEG_M_TXP11 18
PEG_M_TXP12 18
PEG_M_TXP13 18
PEG_M_TXP14 18
PEG_M_TXP15 18

2
49.9_0402_1%

PEG_RXN0 18
PEG_RXN1 18
PEG_RXN2 18
PEG_RXN3 18
PEG_RXN4 18
PEG_RXN5 18
PEG_RXN6 18
PEG_RXN7 18
PEG_RXN8 18
PEG_RXN9 18
PEG_RXN10 18
PEG_RXN11 18
PEG_RXN12 18
PEG_RXN13 18
PEG_RXN14 18
PEG_RXN15 18

CFG[4:3]

Reserved

CFG5 (DMI select)

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

CFG6

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

CFG7 (Intel Management


Engine Crypto strap)

PEG_RXP0 18
PEG_RXP1 18
PEG_RXP2 18
PEG_RXP3 18
PEG_RXP4 18
PEG_RXP5 18
PEG_RXP6 18
PEG_RXP7 18
PEG_RXP8 18
PEG_RXP9 18
PEG_RXP10 18
PEG_RXP11 18
PEG_RXP12 18
PEG_RXP13 18
PEG_RXP14 18
PEG_RXP15 18

1 =(TLS)chiper suite with confidentiality

CFG8

Reserved

CFG9

0 = Reverse Lane,15->0, 14->1

(PCIE Graphics Lane Reversal)

1 = Normal Operation,Lane Number in order

CFG10 (PCIE Lookback enable)

0 = Enable
1 = Disable

CFG11

Reserved

CFG[13:12] (XOR/ALLZ)

00
01
10
11

CFG[15:14]

Reserved

CFG16 (FSB Dynamic ODT)

0 = Disabled

= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation(Default)

1 = Enabled

*
C

CFG[18:17]

Reserved

CFG19 (DMI Lane Reversal)

0 = Normal Operation
(Lane number in Order)

1 = Reverse Lane
CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.


+3VS

@
R59
4.02K_0402_1%

R65

7 CFG7

CFG5

7 CFG5

CANTIGA ES_FCBGA1329

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

1
2
2.21K_0402_1%

R71

7 CFG10

@
R63
2.21K_0402_1%

@
R68

7 CFG9

R74

7 CFG11

R77

7 CFG12

0125 Add R and R -- no stuff

T37
T36

R50

PEG_COMPI
PEG_COMPO

M33
K33
J33

000 = FSB 1066MHz


010 = FSB 800MHz Selected By CPU
011 = FSB 667MHz
Others = Reserved

CFG[2:0] FSB Freq select

PEGCOMP trace width


and spacing is 20/25 mils.

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

GRAPHICS

L32
G32
M32

PCI-EXPRESS

+VCC_PEG

+3VS

7 CFG19
7 CFG20
7 CFG16
7 CFG6
7 CFG8

R64

1
2
4.02K_0402_1%

7 CFG13

R67

1
2
@ 4.02K_0402_1%

7 CFG14

R70

1
2
@ 4.02K_0402_1%

7 CFG15

1
2
2.21K_0402_1%

7 CFG17

R73
@
R76

1
2
@ 2.21K_0402_1%

R66
R69
R72
R75
R78

7 CFG18

MV1 No-stuff R59,R67,R65,R77,R66

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

of

61

+VCCP
+VCCP
R82
1
2
0_0603_5%

+V1.05VS_AXF
U57H

VCCA_DPLLB

AE1

24mA

VCCA_HPLL

139.2mA

VCCA_MPLL

VSSA_LVDS

414uA

C122

1
2
0_0805_5%

4.7U_0805_10V4Z
1
1
C129
C130

C128

AA48

VCCA_PEG_PLL

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM

720mA

0.1U_0402_16V4Z

A32

VCC_HDA

50mA

+1.05VS_PEGPLL

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47
M38
L37

48.363mA
157.2mA

VCCD_LVDS
VCCD_LVDS

50mA

AXF
SM CK

+1.8V_SM_CK

0.1U_0402_16V4Z

+1.5VS

R90
1

0_0805_5%
C126

C125

C124
10U_0805_10V4Z

+VCCP
R93
1
2
MBK2012121YZF_0805

+1.05VS_PEGPLL

VCC_TX_LVDS

K47

VCC_HV
VCC_HV
VCC_HV

C35
B35
A35

10U_0805_10V4Z

+VCCP
R92
1
2
0_0805_5%

1
1

C131 +

C132

C134
10U_0805_10V4Z

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

V48
U48
V47
U47
U46

+VCC_PEG

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

AH48
AF48
AH47
AG47

+1.05VS_DMI

C140
0.1U_0402_16V4Z

+1.05VS_DMI

+VCCP
L7
1
2
BLM18PG121SN1D_0603

+3VS_HV

10U_0805_10V4Z

2 10U_0805_10V4Z

C141

+VCCP
R95
1
2
0_0603_5%

C142
0.1U_0402_16V4Z

+VCCP_D

456mA
VTTLF
VTTLF
VTTLF

A8
L1
AB2

+VCCP

0.47U_0603_10V7K
C145

+1.5VS

C2117

0.1U_0402_16V4Z

C2116

0.01U_0402_16V7K

R2093
1
2
100_0603_1%

BF21
BH20
BG20
BF20

0.47U_0603_10V7K
C144

CANTIGA ES_FCBGA1329

C133

0.47U_0603_10V7K
C143

1212 Montevina DG
+1.5VS_QDAC

C118

118.8mA

1732mA

58.67mA

VCCD_PEG_PLL

60.31mA

+V1.05VS_AXF

124mA

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

105.3mA

LVDS

+1.5VS_QDAC
+1.05VS_HPLL

M25

B22
B21
A21

0.1U_0402_16V4Z

TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
VCCA_TV_DAC
VCCA_TV_DAC

VCC_AXF
VCC_AXF
VCC_AXF

C139

+1.5VS_TVDAC

C117

+VCCP
R89
1
2
MBK2012121YZF_0805

+1.05VS_MPLL

0.1U_0402_16V4Z

0_0402_5%
2

B24
A24

10/08 add this power rail

0.1U_0402_16V4Z
0.1U_0402_16V4Z

HV

C138

R2090
1

220U_6.3V_M

A CK

VCCA_SM_CK
VCCA_SM_CK
26mA
VCCA_SM_CK
VCCA_SM_CK
26mA
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF

PEG

10U_0805_10V4Z

C137

+VCC_PEG

VTTLF

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

DMI

C136

R85
1
2
0_0805_5%

TV

C135

+1.8V

10U_0805_10V4Z

C123

POWER

HDA

1U_0603_10V4Z

+1.5VS_TVDAC

D TV/CRT

1U_0603_10V4Z

+1.05VS_A_SM_CK

1U_0603_10V4Z

+1.05VS_HPLL

321.35mA

1
2
0_0603_5%

C109

10U_0805_10V4Z

R94

1 @
C116

A SM

R91

+1.05VS_PEGPLL

+1.05VS_A_SM

+VCCP

0.1U_0402_16V4Z

VCCA_PEG_BG

50mA
2

A PEG

AD48
1

A LVDS

J47
+1.5VS_PEG_BG

1U_0603_10V4Z

2.2U_0805_16V4Z

+1.5VS

R88
1
2
0_0603_5%

VCCA_LVDS

10U_0805_10V4Z

4.7U_0805_10V4Z

+3VS

@ R87
1
2
0_0603_5%

+1.8V_SM_CK

0.47U_0603_10V7K

13.2mA
J48

VTT

+1.05VS_MPLL

64.8mA

PLL

AD1

C108
10U_0805_10V4Z

C115

L48
+1.05VS_HPLL

64.8mA

C114

VCCA_DPLLA

C113

F47

CRT

VCCA_DAC_BG
VSSA_DAC_BG

C110

A25
B25
D

1
+

220U_6.3V_M

2.68mA

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

C107

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VCCA_CRT_DAC
VCCA_CRT_DAC

4.7U_0805_10V4Z

852mA
73mA
B27
A26

D3
2

R96
1
2
10_0402_5%

R97
1
2
0_0402_5%

+3VS_HV

CH751H-40PT_SOD323-2
+3VS

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Thursday, January 08, 2009

Sheet
1

10

of

61

U57G

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

BA36
BB24
BD16
BB21
AW16
AW13
AT13

VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

AJ14
AH14

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC GFX NCTF

6326.84mA

2006/02/13

Issued Date

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1U_0603_10V4Z

CANTIGA ES_FCBGA1329

1U_0603_10V4Z

C176

0.47U_0402_6.3V6K

C175

C174

0.22U_0603_10V7K

0.22U_0603_10V7K

C173

C172

AV44 VCCSM_LF1
BA37 VCCSM_LF2
AM40 VCCSM_LF3
AV21 VCCSM_LF4
AY5 VCCSM_LF5
AM10 VCCSM_LF6
BB13 VCCSM_LF7

C178 0.1U_0402_16V4Z

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

C177 0.1U_0402_16V4Z

CANTIGA ES_FCBGA1329

PAD T43
PAD T44

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

VCC GFX

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC SM LF

+VCCP

POWER

VCC

0317 change value

VCC NCTF

T32

VCC CORE

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

C161

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23

C158
330U_4V_M

0.01U_0402_16V7K
C160

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

10U_0805_10V4Z
C159

C166

0.1U_0402_16V4Z
C165

0.22U_0402_10V4Z
C164

0.22U_0402_10V4Z
C163

10U_0805_10V4Z

C162
220U_6.3V_M

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33

10U_0805_10V4Z

1
D

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

POWER

+1.8V

U57F

+VCCP

3000mA
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

VCC SM

Extnal Graphic: 1210.34mA


integrated Graphic: 1930.4mA

Sheet

Thursday, January 08, 2009


1

11

of

61

U57J

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

CANTIGA ES_FCBGA1329

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA16

VSS

AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS NCTF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS SCB

AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17

NC

U57I

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

VSS
VSS
VSS
VSS

U24
U28
U25
U29

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

BH48
BH1
A48
C1
A3

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

CANTIGA ES_FCBGA1329

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

12

of

61

+1.8V

+1.8V
+V_DDR_MCH_REF

DDR_A_D2
DDR_A_D3

Layout Note:
Place near
JP3

DDR_A_D8
DDR_A_D14
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D9
DDR_A_D15

+1.8V

0.1U_0402_16V4Z

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

DDR_A_D16
DDR_A_D17

1
1

C190

C189

0.1U_0402_16V4Z

C188

C187

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C186

C185

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C184

2.2U_0805_16V4Z

C183

2.2U_0805_16V4Z

C182

2.2U_0805_16V4Z

C181
330U_D2_2.5VM_R15

DDR_A_DQS#2
DDR_A_DQS2

1113 Change type for layout

DDR_A_D18
DDR_A_D19
DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27

Layout Note:
Place one cap close to every
2 pullup
resistors terminated to +0.9VS

7 DDR_CKE0_DIMMA
8 DDR_A_BS2

DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

+0.9V

8 DDR_A_BS0
8 DDR_A_WE#
1

8 DDR_A_CAS#
7 DDR_CS1_DIMMA#

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

7 M_ODT1
2

DDR_A_D37
DDR_A_D36

C203

C202

C201

C200

C199

C198

C197

C196

C195

C194

C193

C192

C191

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D35
DDR_A_D32
DDR_A_D40
DDR_A_D44

DDR_A_DM5

+0.9V

4
3

RP2

56_0404_4P2R_5%
RP3
DDR_A_MA1
1
DDR_A_MA3
2

4
3

4
3

56_0404_4P2R_5%
RP5
DDR_A_RAS#
1
DDR_CS0_DIMMA# 2

4
3

4
3

56_0404_4P2R_5%
RP7
DDR_A_BS0
1
DDR_A_MA10
2

4
3

4
3

56_0404_4P2R_5%
RP9
DDR_A_CAS#
1
DDR_A_WE#
2

4
3

4
3

56_0404_4P2R_5%
RP11
DDR_CS1_DIMMA# 2
M_ODT1
1

3
4

4
3

RP4

56_0404_4P2R_5%
1 DDR_A_MA9
2 DDR_A_MA12

RP8

56_0404_4P2R_5%
1 DDR_A_MA4
2 DDR_A_MA2

RP12

RP13
DDR_A_MA11

4
3

DDR_A_D41
DDR_A_D46
DDR_A_D49
DDR_A_D48

56_0404_4P2R_5%
1 DDR_A_MA7
2 DDR_A_MA6

RP6

RP10

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

56_0404_4P2R_5%
1 DDR_A_BS2
2 DDR_CKE0_DIMMA

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
DDR_A_D61
DDR_A_D60
DDR_A_DM7
DDR_A_D59
DDR_A_D58

56_0404_4P2R_5%
1 DDR_A_MA0
2 DDR_A_BS1

14,15,39 CLK_SMBDATA
14,15,39 CLK_SMBCLK
+3VS

56_0404_4P2R_5%
1 M_ODT0
2 DDR_A_MA13

CLK_SMBDATA
CLK_SMBCLK

56_0404_4P2R_5%
1 DDR_CKE1_DIMMA
2 DDR_A_MA14

R108 56_0402_5%

1
C204 C205

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
G2

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

FOX_AS0A426-N4RN-7F~D

SO-DIMM A

DDR_A_D6
DDR_A_D0
DDR_A_DM0
DDR_A_D5
DDR_A_D7

2006/02/13

2006/03/10

Deciphered Date

DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 7
M_CLK_DDR#0 7

DDR_A_D11
DDR_A_D10

DDR_A_D20
DDR_A_D21
PM_EXTTS#0 7

DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA 7

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7
M_ODT0 7

DDR_A_D39
DDR_A_D38
DDR_A_DM4
DDR_A_D34
DDR_A_D33
DDR_A_D45
DDR_A_D43
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 7
M_CLK_DDR#1 7

DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

0.1U_0402_16V4Z

4
3

2.2U_0603_6.3V4Z

56_0404_4P2R_5%
RP1
DDR_A_MA8
1
DDR_A_MA5
2

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
G1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

R107
10K_0402_5%
2
1

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C180

DDR_A_DQS#0
DDR_A_DQS0

8 DDR_A_MA[0..14]

CONN@

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

C179

DDR_A_D4
DDR_A_D1

8 DDR_A_DQS[0..7]

+V_DDR_MCH_REF 7,14

JDIMM1

0.1U_0402_16V4Z

8 DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

8 DDR_A_D[0..63]

R106
10K_0402_5%
2
1

8 DDR_A_DQS#[0..7]

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

13

of

61

+1.8V

+1.8V

8 DDR_B_DQS#[0..7]

JDIMM2 CONN@

8 DDR_B_DQS[0..7]

DDR_B_DQS#0
DDR_B_DQS0
D

DDR_B_D2
DDR_B_D3

Layout Note:
Place near
JP10

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

+1.8V

+V_DDR_MCH_REF 7,13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

DDR_B_D5
DDR_B_D4
DDR_B_DM0
DDR_B_D6
DDR_B_D7

C207

DDR_B_D0
DDR_B_D1

8 DDR_B_MA[0..14]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

C206

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

0.1U_0402_16V4Z

+V_DDR_MCH_REF

8 DDR_B_DM[0..7]

2.2U_0805_16V4Z

8 DDR_B_D[0..63]

DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2 7
M_CLK_DDR#2 7

DDR_B_D14
DDR_B_D15

DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25

330U_4V_M

DDR_B_DM3

DDR_B_D30
DDR_B_D31

Layout Note:
Place one cap close to every
2 pullup
resistors terminated to +0.9VS

DDR_CKE2_DIMMB

7 DDR_CKE2_DIMMB

DDR_B_BS2

8 DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9V

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

8 DDR_B_BS0
8 DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

8 DDR_B_CAS#
7 DDR_CS3_DIMMB#
2
C229

C228

C227

C226

C225

C224

C223

C222

C221

C220

C219

C218

C217

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10

M_ODT3

7 M_ODT3

DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

+0.9V

4
3

4
3

56_0404_4P2R_5%
RP16
DDR_B_BS0
1
DDR_B_MA10
2

4
3

4
3

56_0404_4P2R_5%
RP18
DDR_B_MA0
1
DDR_B_BS1
2

4
3

4
3

56_0404_4P2R_5%
RP20
DDR_B_RAS#
1
DDR_CS2_DIMMB# 2

4
3

4
3

56_0404_4P2R_5%
RP22
DDR_B_CAS#
1
DDR_B_WE#
2

4
3

4
3

RP17

56_0404_4P2R_5%
DDR_B_MA5
1
DDR_B_MA8
2

RP21

56_0404_4P2R_5%
DDR_B_MA7
1
DDR_B_MA6
2

3
4

4
3
RP26

DDR_CKE3_DIMMB 1
R111

2
56_0402_5%

4
3

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D56
DDR_B_D61
DDR_B_DM7
DDR_B_D59
DDR_B_D58

56_0404_4P2R_5%
DDR_B_MA4
1
DDR_B_MA2
2

CLK_SMBDATA
CLK_SMBCLK

13,15,39 CLK_SMBDATA
13,15,39 CLK_SMBCLK
+3VS

56_0404_4P2R_5%
M_ODT2
1
DDR_B_MA13
2
56_0404_4P2R_5%
DDR_B_BS2
1
DDR_CKE2_DIMMB
2

1
C230

FOX_AS0A426-N8RN-7F

SO-DIMM B

DDR_B_D26
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
C

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB 7

DDR_B_MA14

0612 add

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_BS1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2
DDR_B_MA13

M_ODT2 7

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 7
M_CLK_DDR#3 7

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R109
1

2006/02/13

2006/03/10

Deciphered Date

+3VS

10K_0402_5%
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

C231

DDR_B_D22
DDR_B_D23

R110

RP25

DDR_B_D42
DDR_B_D43

56_0404_4P2R_5%
DDR_B_MA14
1
DDR_B_MA11
2

RP19

RP23

DDR_B_DM5

56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2

2.2U_0603_6.3V4Z

RP15

PM_EXTTS#1 7

DDR_B_DM2

10K_0402_5%

56_0404_4P2R_5%
RP14
DDR_B_MA1
1
DDR_B_MA3
2

56_0404_4P2R_5%
RP24
DDR_CS3_DIMMB# 2
M_ODT3
1

DDR_B_D40
DDR_B_D41

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

0.1U_0402_16V4Z

DDR_B_D21
DDR_B_D16

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1

DDR_B_DQS#2
DDR_B_DQS2

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

G1
G2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D17
DDR_B_D20

201
202

C216

C215

0.1U_0402_16V4Z

C214

0.1U_0402_16V4Z

C244

C213

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C212

C211

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C210

2.2U_0805_16V4Z

C209

C208

2.2U_0805_16V4Z

2.2U_0805_16V4Z

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

14

of

61

FSC

FSB

FSA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

REF
MHz

266

100

33.3

14.318

DOT_96 USB
MHz
MHz
96.0

R112
1
2
0_0805_5%

+3VS

48.0

03/02 change
2

133

100

33.3

14.318

96.0

48.0

200

100

33.3

14.318

96.0

48.0

166

100

33.3

14.318

96.0

C234
10U_0805_10V4Z

Routing the trace at least 10mil

333

100

33.3

14.318

96.0

0.1U_0402_16V4Z

100

100

33.3

14.318

96.0

48.0

400

100

33.3

14.318

96.0

48.0

0.1U_0402_16V4Z

C237
0.1U_0402_16V4Z

C238
0.1U_0402_16V4Z

C239
0.1U_0402_16V4Z

C240
0.1U_0402_16V4Z

+1.05VS_CK505

R113
1
2
0_0805_5%

14.31818MHZ_16P

Place close to U51


1

0.1U_0402_16V4Z
1
C245
C246

2
10U_0805_10V4Z
C251
18P_0402_50V8J

C236

+VCCP

CLK_XTAL_IN

48.0

CLK_XTAL_OUT

48.0

C235

Y1

+3VS_CK505

Reserved

10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
C248
C249
C250

C247

2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

C944

2
0.1U_0402_16V4Z

C252
18P_0402_50V8J

Vendor suggests 22pF

R118
1

56_0402_5%
CLRP1
NO SHORT PADS
1
2
R122
1K_0402_5%

R863

7 CLKREQ#_7

NB

MCH_CLKSEL0 7

CPU

7
7
4
4

1
2 475_0402_1%
CLK_MCH_BCLK#
CLK_MCH_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK

R_CLKREQ#_7
CLK_MCH_BCLK#
CLK_MCH_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK

R_CKPWRGD
FSB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

CLK_XTAL_OUT
CLK_XTAL_IN
R140

2 33_0402_1%

1
1
2
R148
1K_0402_5%

MCH_CLKSEL1 7

FSC
CLK_SMBDATA
CLK_SMBCLK

13,14,39 CLK_SMBDATA
13,14,39 CLK_SMBCLK

39 CLK_DEBUG_PORT1
32 CLK_DEBUG_PORT0
40 CLK_PCI_EC

@
R154
0_0402_5%

1
1
1

2 33_0402_1%
2 33_0402_1%
2 33_0402_1%

R133

2 33_0402_1%

PCI2_TME
27_SEL
PCI_CLK3
ITP_EN

26 CLK_PCI_ICH

@
R127
R126
R131

CKPWRGD/PD#
FS_B/TEST_MODE
VSS_REF
XTAL_OUT
XTAL_IN
VDD_REF
REF_0/FS_C/TEST_
REF_1
SDA
SCL
NC
VDD_PCI
PCI_1
PCI_2
PCI_3
PCI_4/SEL_LCDCL
PCIF_5/ITP_EN
VSS_PCI

1025 Add R127 to meet Intel CLK design

FSC

5 CPU_BSEL2

+3VS_CK505

1
2
R171
1K_0402_5%

MCH_CLKSEL2 7

R136

28 CLK_48M_ICH

PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRC_10#
SRC_10
CLKREQ_10#
SRC_11
SRC_11#
CLKREQ_11#
SRC_9#
SRC_9
CLKREQ_9#
VSS_SRC
CLKREQ_4#
SRC_4#
SRC_4
VDD_SRC_IO
CLKREQ_3#

R862

2 475_0402_1%

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLKREQ#_6 32
CLK_PCIE_MCARD2 32
CLK_PCIE_MCARD2# 32

Card Reader

XDP/ITP
3G_PLL
TV

18 CLK_PCIE_VGA
18 CLK_PCIE_VGA#

2 0_0402_5% CLK_VGA
2 0_0402_5% CLK_VGA#

1
1

2 475_0402_1%

1
1

2 475_0402_1%

2 475_0402_1%

R_CLKREQ#_4
R861
CLK_PCIE_NCARD#
CLK_PCIE_NCARD

2 475_0402_1%

R_CLKREQ#_C

2 475_0402_1%

R860

CLK_PCIE_MCARD0#
CLK_PCIE_MCARD0
CLKREQ#_10 32
CLK_PCIE_MCARD1
CLK_PCIE_MCARD1#
CLKREQ#_11 35
CLK_PCIE_LAN# 31
CLK_PCIE_LAN 31
CLKREQ#_9 31

32
32

WLAN

35
35

Robson
GLAN

CLKREQ#_4 32
CLK_PCIE_NCARD# 32
CLK_PCIE_NCARD 32

New Card

CLKREQ#_C 28

27M_SSC_CLOCK
27M_CLK_CLOCK

1
1

CLK_PCIE_SATA# 27
CLK_PCIE_SATA 27

SATA

CLK_PCIE_ICH# 28
CLK_PCIE_ICH 28

ICH

R2102
2 33_0402_1%
2 33_0402_1%
R2103

27M_SSC
27M_CLK

27M_SSC 19
27M_CLK 19

27MHZ For VGA

VGA (Discrete)

R2006
R2007

H_STP_PCI# 28
H_STP_CPU# 28

CLK_PCIE_MCARD0#
CLK_PCIE_MCARD0
R_CLKREQ#_10
R865
CLK_PCIE_MCARD1
CLK_PCIE_MCARD1#
R_CLKREQ#_11
R866
CLK_PCIE_LAN#
CLK_PCIE_LAN
R_CLKREQ#_9
R864

CLK_PCIE_ICH#
CLK_PCIE_ICH
+1.05VS_CK505

CLK_PCIE_VGA
CLK_PCIE_VGA#

H_STP_PCI#
H_STP_CPU#

CLK_PCIE_SATA#
CLK_PCIE_SATA

+1.05VS_CK505
@
R175
0_0402_5%

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

SLG8SP553VTR_QFN72_10x10

FSA

2 33_0402_1%

R170
1
2
10K_0402_5%
R174
1
2
0_0402_5%

@
R169
1K_0402_5%

+VCCP

CLK_PCIE_CR# 33
CLK_PCIE_CR 33

VDD_48
USB_0/FS_A
USB_1/CLKREQ_A#
VSS_48
VDD_IO
SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_IO
VDD_PLL3
LCDCLK/27M
LCDCLK#/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRC_2
SRC_2#
VSS_SRC
SRC_3
SRC_3#

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

1
1
1

@
R142
1K_0402_5%

5 CPU_BSEL1

2 0_0402_5%
2 0_0402_5%

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

2
2

@ R119
@ R120
R123

28,51 VGATE
51 CLK_ENABLE#
28 CK_PWRGD

28 CLK_14M_ICH

R151
1
2
0_0402_5%

1
1

+1.05VS_CK505

VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
CLKREQ_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
VDD_SRC_IO
SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
VDD_SRC

U51

+3VS_CK505

+VCCP

FSB

R2002
R2003

+3VS_CK505
@
R130
1K_0402_5%

CLK_SRC
CLK_SRC#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
R_CLKREQ#_6

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

5 CPU_BSEL0

+VCCP

R121
1
2
2.2K_0402_5%
R124
1
2
0_0402_5%

FSA

+1.05VS_CK505

+3VS_CK505
2

1212 Add R and R


+3VS
+3VS

SRC8/SRC8#
ITP/ITP#
Enable DOT96 & SRC1(UMA)
Enable SRC0 & 27MHz(DIS)

+3VS

+3VS
R158
2.2K_0402_5%

28,32,35 ICH_SMBDATA

+3VS

28,32,35 ICH_SMBCLK

R178
10K_0402_5%

@ C232
2
5P_0402_50V8C
@ C233
2
4.7P_0402_50V8C
@ C241
2
4.7P_0402_50V8C
@ C242
2
4.7P_0402_50V8C
@ C243
2
5P_0402_50V8C

CLK_SMBCLK

4
2N7002DW-7-F_SOT363-6
Q75B

CLK_48M_ICH

CLK_14M_ICH

CLK_PCI_ICH

CLK_PCI_EC

CLK_DEBUG_PORT0
A

2.2K_0402_5%

CLK_SMBDATA

1
2N7002DW-7-F_SOT363-6
Q75A

SB, MINI PCI


@
R176
10K_0402_5%

R159

PCI_CLK3

=
=
=
=

0
1
0
1

ITP_EN

PCI_CLK3
1

ITP_EN

R179
10K_0402_5%

@
R181
10K_0402_5%

2006/02/13

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

15

of

61

+CRTVDD

+5VS

0_0603_5%
BLUE_CRT
2

42 D_VSYNC

C255
0.1U_0402_16V4Z
1
2

1020 change size to meet NV request

@
R205
51K_0402_5%

R196
1

2 0_0603_5%

D_VSYNC

R197

R198

2.2K_0402_5%

2.2K_0402_5%

D_DDCDATA

U7
SN74AHCT1G125GW_SOT353-5

1 @
C262
2

1 @
C263

5P_0402_50V8C

+3VS

VSYNC_G_A

D_HSYNC

R199
2.2K_0402_5%

R200
2.2K_0402_5%

M_DDCDATA 18

Q69B
2N7002DW-7-F_SOT363-6

5P_0402_50V8C
D_DDCCLK

1
2

2 0_0603_5%

+3VS
+CRTVDD

18 M_VSYNC

@
R204
51K_0402_5%

HSYNC_G_A

R193
1

5
1

P
OE#

5
1
P
OE#

18 M_HSYNC

U6
SN74AHCT1G125GW_SOT353-5
Y 4

+5VS

JCRT
CONN@
SUYIN_070546FR015S265ZR

16 GND
17 GND
+CRTVDD

R2071
1

@ D7
DAN217_SC59

BLUE

@ D6
@D6

GREEN

0_0603_5%
GREEN_CRT
2

42 D_HSYNC

+5VS
C254
0.1U_0402_16V4Z
1
2

0_0603_5%
RED_CRT
2

R2070
1

42 BLUE

R2069
1

@ D5
@D5

42 GREEN

RED

42 RED

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

Place close to
JCRT

0.1U_0402_16V4Z
C253

DAN217_SC59

1.1A_6VDC_FUSE

1106 EMI request

CH491D_SC59

BLUE_CRT
GREEN_CRT
RED_CRT

W=40mils

F1
1

+RCRT_VCC
D4
2

DAN217_SC59

+5VS

CRT
Connector

M_DDCCLK 18

Q69A
2N7002DW-7-F_SOT363-6

1102 R204,R205 no stuff


D_DDCDATA 42
D_DDCCLK 42

Note: CRT / TV-out should route to JP30


first then to the JP1 & JP2 on system side.

CRT Termination/EMI Filter


3

18 VGA_RED
18 VGA_GRN

2 HLC0603CSCCR11JT_0603

RED

L15

2 HLC0603CSCCR11JT_0603

GREEN

L17

2 HLC0603CSCCR11JT_0603

BLUE

1
1
1
C314 C315 C316
22P_0402_50V8J
2

150_0402_1%

150_0402_1%

150_0402_1%

18 VGA_BLU

L13

R241 R242 R243

22P_0402_50V8J
2

1
4.7P_0402_50V8B

C317

C318

C319
4.7P_0402_50V8C

22P_0402_50V8J
4.7P_0402_50V8B

MV1 Add 4.7pF on C317,C318,C319

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

16

of

61

0125 Add R

1108 EMI request

+LCDVDD
+LCDVDD

+5VALW

C266

R207
470_0805_5%

220P_0402_25V8J

0.1U_0402_16V4Z

R208
1M_0402_5%

C264

C267
0.1U_0402_16V4Z

4.7U_0805_10V4Z

2
G

@ C2111

C265

R209 1

680P_0402_50V7K
2
1

+3VS

18
18
18
18
18
18

USB20_P4_R
USB20_N4_R

LVDS_BCLK+
LVDS_BCLK-

18 LVDS_BCLK+
18 LVDS_BCLK-

C269

LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-

LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

ACES_88242-4001
CONN@

LVDS_A2- 18
LVDS_A2+ 18
LVDS_A1- 18
LVDS_A1+ 18
LVDS_A0- 18
LVDS_A0+ 18
LVDS_ACLK- 18
LVDS_ACLK+ 18

R210
2.2K_0402_5%

Limited Current < 1A


DMIC_DAT
DMIC_CLK
+5V_LOGO
INV_PWM
BKOFF#
DAC_BRIG

R462 1

2
100_0805_5%

DDC2_CLK
DDC2_DATA
1
C272
470P_0402_50V8J

Avoid Panel display garbage after


power on.

DMIC_DAT 34
DMIC_CLK 34
+5VS
INV_PWM 40
BKOFF# 40
DAC_BRIG 40
+USB_CAM
DDC2_CLK 20
DDC2_DATA 20
C2120
470P_0402_50V8J

B+

@
D17

Logo LED
1102 Change size to 0805

IO1

IO2 GND

0_0805_5%

L9
1
2
FBMA-L11-201209-221LMA30T_0805

0308_Reserve L8 and
install L9.

1212 EMI request

PRTR5V0U2X_SOT143-4

VIN

+3VS

USB20_P4_R

USB20_N4_R

C273
470P_0402_50V8J
2

INVPWR_B+
@
L8

+5VALW

2N7002DW-7-F_SOT363-6
Q71B

20 ENAVDD

LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND

1000P_0402_25V

JLVDS

2 0_0402_5%
2 0_0402_5%

C268

LVDS CONN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

2 100K_0402_5%

R565 1
R564 1

28 USB20_P4
28 USB20_N4

680P_0402_50V7K

C271

680P_0402_50V7K

C270

Q71A
2N7002DW-7-F_SOT363-6

@ C2110
220P_0402_25V8J

change to 0805

+3VS
Q7
SI2301BDS-T1-E3_SOT23-3

1
1

6 2

DMIC_DAT
@ R2122
@R2122
10K_0402_5%

INVPWR_B+

+LCDVDD

DMIC_CLK
1

BKOFF#

+LCDVDD

4.7U_0805_10V4Z

R213
2.2K_0402_5%
1

DDC2_CLK
DDC2_DATA

R212
2.2K_0402_5%

USB Camera Power

1106 Add SB control pin

+5VS

+USB_CAM

+5VALW

PJP4
PAD-OPEN 2x2m

U54
1

IN

GND

SHDN

OUT

BYP

28 GPIO20

R2072
0_0402_5%

@
R2073 1

C952
4.7U_0805_10V4Z

2
2

G916-390T1UF_SOT23-5

R892
24.9_0402_1%

2 0_0402_5%

10U_0805_10V4Z

C1288

R891
53.6_0402_1%

@ PJP5
PAD-OPEN 2x2m

SA000025F00

S IC G916T1UF SOT23 5P ADJUSTABLE


LDO

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

17

of

61

+PCIE

LVDS & DAC Interface

U71A
1/16 PCI_EXPRESS

PEG Interface

500 mA

U71I

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

0.1U_0402_16V4Z

AK16
AK17
AK21
AK24
AK27

7/16 IFPAB

AM12
AM11

LVDS_ACLK- 17
LVDS_ACLK+ 17

IFPA_TXD0
IFPA_TXD0

AL8
AM8

LVDS_A0- 17
LVDS_A0+ 17

IFPA_TXD1
IFPA_TXD1

AM9
AM10

LVDS_A1- 17
LVDS_A1+ 17

IFPA_TXD2
IFPA_TXD2

AL10
AK10

LVDS_A2- 17
LVDS_A2+ 17

IFPA_TXC
IFPA_TXC

+1.8VS
1

L61
1

BLM18PG181SN1D_0603
2

IFPAB_PLLVDD

AK9

C1033

C1019

C1034

@
R1044
1K_0402_1%

+1.8VS
L62
1

IFPAB_IOVDD

C1020

C1036

220P_0402_50V7K

4.7U_0603_6.3V6K

4700P_0402_25V7K

C1035

1U_0402_6.3V4Z

BLM18PG181SN1D_0603
2
4.7U_0603_6.3V6K

1600 mA

IFPAB_RSET

7,26,31,32,33,35

PLT_RST#

C1037

AG9

IFPA_IOVDD

AG10

IFPB_IOVDD

145 mA
1

C1038

IFPA_TXD3
IFPA_TXD3

AL11
AK11

IFPB_TXC
IFPB_TXC

AN13
AP13
AP8
AN8

LVDS_B0- 17
LVDS_B0+ 17

IFPB_TXD5
IFPB_TXD5

AN10
AP10

LVDS_B1- 17
LVDS_B1+ 17

IFPB_TXD6
IFPB_TXD6

AR10
AR11

LVDS_B2- 17
LVDS_B2+ 17

R944 1

AP11
AN11

2 200_0402_1%

15 CLK_PCIE_VGA
15 CLK_PCIE_VGA#
9 PEG_RXP0
9 PEG_RXN0

C1039
C1040

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

C1041
C1042

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

C1043
C1044

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

9 PEG_RXP3
9 PEG_RXN3

C1045
C1046

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

9 PEG_RXP4
9 PEG_RXN4

U71G

2
10K_0402_5%

AG7

6/16 DACC
DACC_VDD

AK6

DACC_VREF

AH7

DACC_RSET

I2CB_SCL
I2CB_SDA

DACC_HSYNC
DACC_VSYNC

DAC C

G3
G2

DACC_RED

AK4
AL4

DACC_BLUE

AJ4

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

1009 change HDMI I2C channel for Nvidia suggestion


1105 nVIDIA suggetion, add R
1108 nVIDIA suggestion -- change HDMI DDC to I2CD

9 PEG_RXP5
9 PEG_RXN5

C1049
C1050

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEX_TX1
PEX_TX1

AN19
AP19

PEX_RX1
PEX_RX1

AL19
AK19

PEX_TX2
PEX_TX2

AR19
AR20

PEX_RX2
PEX_RX2

PEG_C_RXP3 AL20
PEG_C_RXN3 AM20

PEX_TX3
PEX_TX3

AP20
AN20

PEX_RX3
PEX_RX3

PEG_C_RXP4 AM21
PEG_C_RXN4 AM22

PEX_TX4
PEX_TX4

AN22
AP22

PEX_RX4
PEX_RX4

AL22
AK22

PEX_TX5
PEX_TX5

AR22
AR23

PEX_RX5
PEX_RX5

PEG_C_RXP6 AL23
PEG_C_RXN6 AM23

PEX_TX6
PEX_TX6

AP23
AN23

PEX_RX6
PEX_RX6

PEG_C_RXP2
PEG_C_RXN2

PEG_C_RXP5
PEG_C_RXN5

9 PEG_M_TXP5
9 PEG_M_TXN5
9 PEG_RXP6
9 PEG_RXN6

C1051
C1052

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

9 PEG_M_TXP6
9 PEG_M_TXN6
9 PEG_RXP7
9 PEG_RXN7

NB9P-GS_BGA 969~D

C1053
C1056

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEG_C_RXP7 AM24
PEG_C_RXN7 AM25

9 PEG_M_TXP7
9 PEG_M_TXN7
9 PEG_RXP8
9 PEG_RXN8

U71F

DACA_VREF

AK13

DACA_RSET

DACA_HSYNC
DACA_VSYNC

AM13
AL13

M_HSYNC 16
M_VSYNC 16

DACA_RED

AM15

VGA_RED 16

DACA_GREEN

AM14

DAC A

DACA_BLUE

VGA_GRN 16

AL14

R1591

150_0402_1%

R1590

150_0402_1%

150_0402_1%

NB9P-GS_BGA 969~D

VGA_BLU 16

R1592

9 PEG_RXP11
9 PEG_RXN11

9 PEG_RXP14
9 PEG_RXN14

AR25
AR26

PEX_RX8
PEX_RX8

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEG_C_RXP9 AL26
PEG_C_RXN9 AM26

PEX_TX9
PEX_TX9

AP26
AN26

PEX_RX9
PEX_RX9

C1063
C1064

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEG_C_RXP10 AM27
PEG_C_RXN10 AM28

PEX_TX10
PEX_TX10

AN28
AP28

PEX_RX10
PEX_RX10

C1068
C1069

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEG_C_RXP11 AL28
PEG_C_RXN11 AK28

PEX_TX11
PEX_TX11

AC6

5/16 DACB(TV)
DACB_VDD

AC5

DACB_VREF

AB6

DACB_RSET

1009 disable TV function

9 PEG_RXP15
9 PEG_RXN15
9 PEG_M_TXP15
9 PEG_M_TXN15

DAC B
DACB_CSYNC

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19

A2
AB7
AD6
AF6
AG6
AJ5
AK15
AL7
D35
E35
E7
F7
H32
M7
P6
P7
R7
U7
V6

0.1U_0402_16V4Z

4700P_0402_16V7K

C1025

C1026

4.7U_0603_6.3V6K

+PCIE

4700P_0402_16V7K

C1027

1U_0603_10V4Z

C1028

C1029

C1030

C1031

C1032

2
22U_0805_6.3VAM

0.1U_0402_16V4Z

4700P_0402_16V7K

4.7U_0603_6.3V6K

110 mA

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5

0.1U_0402_16V7K

J10
J11
J12
J13
J9

C1058

C1054

C1055

2
1U_0603_10V4Z

VDD_SENSE
GND_SENSE

AD20
AD19

PEX_PLLVDD

AG14

VDD_SENSE 52

+PCIE
L64
1

AR28
AR29

PEX_RX11
PEX_RX11

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEG_C_RXP12 AK29
PEG_C_RXN12 AL29

PEX_TX12
PEX_TX12

AP29
AN29

PEX_RX12
PEX_RX12

C1074
C1075

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEG_C_RXP13 AM29
PEG_C_RXN13 AM30

PEX_TX13
PEX_TX13

AN31
AP31

PEX_RX13
PEX_RX13

C1076
C1077

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PEG_C_RXP14 AM31
PEG_C_RXN14 AM32

PEX_TX14
PEX_TX14

PEX_RFU1

AG19

AR31
AR32

PEX_RX14
PEX_RX14

PEX_RFU2

AG20

PEX_TERMP

AG21

R1043

PEG_C_RXP15 AN32
PEG_C_RXN15 AP32

2 2.49K_0402_1%

PEX_TX15
PEX_TX15

AR34
AP34

PEX_RX15
PEX_RX15

TESTMODE

AP35

R949

2 10K_0402_5%

C1078
C1079

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

1U_0603_10V4Z

C1070
C1072

9 PEG_M_TXP14
9 PEG_M_TXN14

U71H

2
10K_0402_5%

PEX_TX8
PEX_TX8

C1061
C1062

9 PEG_M_TXP13
9 PEG_M_TXN13

R948 1

C1024

0.1U_0402_16V4Z

9 PEG_M_TXP12
9 PEG_M_TXN12
9 PEG_RXP13
9 PEG_RXN13

AL25
AK25

PEG_C_RXP8
PEG_C_RXN8

9 PEG_M_TXP11
9 PEG_M_TXN11
9 PEG_RXP12
9 PEG_RXN12

PEX_RX7
PEX_RX7

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

9 PEG_M_TXP10
9 PEG_M_TXN10

R1042

C1067

9 PEG_RXP10
9 PEG_RXN10

AN25
AP25
1
1

9 PEG_M_TXP9
9 PEG_M_TXN9

M_DDCCLK 16
M_DDCDATA 16

G1
G4

C1066

AK12

I2CA_SCL
I2CA_SDA

DACA_VREF

150 mA

C1065

4/16 DACA
DACA_VDD

124_0402_1%

AJ12

0.1U_0402_16V4Z

C1172

470P_0402_50V7K

4700P_0402_16V7K

4.7U_0603_6.3V6K

DACA_VDD

BLM18PG181SN1D_0603
2

C1023

+3VS

PEX_TX7
PEX_TX7

C1059
C1060

9 PEG_M_TXP8
9 PEG_M_TXN8
9 PEG_RXP9
9 PEG_RXN9

PEX_REFCLK
PEX_REFCLK

PEX_RX0
PEX_RX0

9 PEG_M_TXP4
9 PEG_M_TXN4

AM1
AM2

DACC_GREEN

C1047
C1048

AR16
AR17

PEG_C_RXP1 AM18
PEG_C_RXN1 AM19

9 PEG_M_TXP3
9 PEG_M_TXN3

R945 1

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_TX0
PEX_TX0

9 PEG_M_TXP2
9 PEG_M_TXN2

AJ17
AJ18

AP17
AN17

9 PEG_M_TXP1
9 PEG_M_TXN1
9 PEG_RXP2
9 PEG_RXN2

L63
1

PEX_CLKREQ

PEG_C_RXP0 AL17
PEG_C_RXN0 AM17

9 PEG_M_TXP0
9 PEG_M_TXN0
9 PEG_RXP1
9 PEG_RXN1

NB9P-GS_BGA 969~D

+3VS

PEX_RST

AR13

NB9M & NB9P-GS stuff


LVDS_BCLK- 17
LVDS_BCLK+ 17

IFPB_TXD4
IFPB_TXD4

IFPB_TXD7
IFPB_TXD7

AM16

4.7U_0603_6.3V6K

220P_0402_50V7K

C1018

4700P_0402_25V7K

1U_0402_6.3V4Z

AJ11

C1022

22U_0805_6.3VAM

IFPAB_PLLVDD

32 mA

IFPAB_RSET

C1021

1U_0603_10V4Z

10NH_LQG15HS10NJ02D_5%_0402

100mA
1

C1260

C1057

0.01U_0402_16V7K

C1073

C1071
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

AB5

NB9P-GS_BGA 969~D

1009 disable TV function


DACB_RED

AA4

DACB_GREEN

AB4

DACB_BLUE

Y4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

NB9P-GS_BGA 969~D

2006/02/13

Deciphered Date

2006/03/10

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Thursday, January 08, 2009


E

Sheet

18

of

61

U71P
15/16 GND

+3VS

R950
U71K
10K_0402_5%

U71D

D7
D6
C7
B7
A7

D3
C4
D4

ROM_SI
ROM_SO
ROM_SCLK

HDA_BCLK
HDA_RST
HDA_SDI
HDA_SDO
HDA_SYNC

PV2 nVIDIA suggestion


R951 1

1109 nVIDIA suggestion -- R387,R388,R415,R422,R427 -- install


Change R415 to 10 ohm

F6

I2CH_SDA

G6

2
M9
40.2K_0402_1%

BUFRST
PGOOD_OUT

A4
C5

2
2.2K_0402_5%

+3VS

STRAP_REF_MIOB

@ D48

2
0.01U_0402_25V7K

NB9P-GS_BGA 969~D

+3VS

C1084
0.1U_0402_16V4Z
HDCP_WP

AE7

IFPE_IOVDD

R956
10K_0402_5%

AD7

IFPF_IOVDD

2
HDCP_SCL

R958
10K_0402_5%

1212 HDCP ROM -- R951 pull up,R959 no install


1

R957
2.2K_0402_5%

AE5
AE6

DPL2_TXD0
DPL2_TXD0

AF5
AF4

DPL1_TXD1
DPL1_TXD1

AG4
AH4

DPL0_TXD2
DPL0_TXD2

AH5
AH6

IFPF

+3VS

+3VS

HDCP
ROM

IFPEF_RSET

AD4
AE4

SPDIF_OUT 34

@R979
@R979
3.4K_0402_1%

BAV99-7-F_SOT23-3

AK14
K9

IFPEF_PLLVDD

R952
10K_0402_5%

@
R978
24.3K_0402_1%

@ C1083

STRAP_REF_3V3
RFU_GND
RFU_GND

AJ6
AL1

AUX
AUX

DPL3_TXC
DPL3_TXC

R955

A5

40.2K_0402_1%
2
N9

+3VS

+3VS

R954

2.2K_0402_5%
2

HDCP_SDA
R953

SPDIF

IFPE

1112 C1083,D48 no stuff

HDCP_SCL

I2CH_SCL

9/16 IFPEF

ROM_SI 20
ROM_SO 20
ROM_SCLK 20

AUX
AUX

AF2
AF3

DPL3_TXC
DPL3_TXC

AH3
AH2

DPL2_TXD0
DPL2_TXD0

AH1
AJ1

DPL1_TXD1
DPL1_TXD1

AJ2
AJ3

DPL0_TXD2
DPL0_TXD2

AL3
AL2

0_0402_5% HDA_BITCLK_VGA
0_0402_5% HDA_RST#_VGA
10_0402_5%HDA_SDIN_VGA
0_0402_5% HDA_SDOUT_VGA
0_0402_5% HDA_SYNC_VGA

ROM_SI
ROM_SO
ROM_SCLK

2
2
2
2
2

ROM_CS#

1
1
1
1
1

C3

33_0402_5%

R387
R388
R415
R422
R427

HDA_VGA_BITCLK
HDA_VGA_RST#
HDA_SDIN2
HDA_VGA_SDOUT
HDA_VGA_SYNC

ROM_CS

RFU
RFU

27
27
27
27
27

J26
J25

15P_0402_50V8J

@ R611 1

13/16 MISC2

@ C823 1

@
R959
10K_0402_5%

U61

1
2
3
4

A0
A1
A2
GND

VCC
WP
SCL
SDA

8
7
6
5

HDCP_WP
HDCP_SCL
HDCP_SDA

NB9P-GS_BGA 969~D

AT24C02N-10SU-2.7_SO8

+IFPC_PLLVDD is 3.3V for NB9P-GE, but it is 1.1V for NB9P-GS/GE2 and NB9M-GS-B

U71J
8/16 IFPCD

IFPC

1106 Delete R98,R1006,Q8,Q73


+1.8VS

L67
1

1U_0402_6.3V4Z

4700P_0402_25V7K

AJ9

IFPCD_PLLVDD

IFPC_RSET

AK7

IFPCD_RSET

NB9P-GS_BGA 969~D

C1091
4.7U_0603_6.3V6K

C1092

C1093

C1094

+PCIE

C1095
R971
1K_0402_1%

1U_0402_6.3V4Z

1109 Delete R99, Change +IFPC_PLLVDD to +PCIE

AUX
AUX

AN3
AP2

DPL3_TXC
DPL3_TXC

AR2
AP1

HDMI_C_CLKHDMI_C_CLK+

C1335
C1336

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

HDMI_CLK- 44
HDMI_CLK+ 44

DPL2_TXD0
DPL2_TXD0

AM4
AM3

HDMI_C_TX0HDMI_C_TX0+

C1337
C1338

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

HDMI_TX0- 44
HDMI_TX0+ 44

DPL1_TXD1
DPL1_TXD1

AM5
AL5

HDMI_C_TX1HDMI_C_TX1+

C1339
C1340

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

HDMI_TX1- 44
HDMI_TX1+ 44

DPL0_TXD2
DPL0_TXD2

AM6
AM7

HDMI_C_TX2HDMI_C_TX2+

C1341
C1342

1
1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

HDMI_TX2- 44
HDMI_TX2+ 44

AUX
AUX

AN4
AP4

32 mA

BLM18PG181SN1D_0603

IFPCD_PLLVDD

E15
E18
E24
E27
E30
E6
E9
F2
F31
F34
F5
J2
J31
J34
J5
L9
M11
M13
M15
M17
M19
M2
M21
M23
M25
M31
M34
M5
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R31
R34
R5
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V12
V14
V16
V18
V2
V20
V22
V24
V31
V5
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA2
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AA5
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD11
AD13
AD15
AD17
AD2
AD21
AD23
AD25
AD31
AD34
AD5
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG31
AG34
AG5
AK2
AK31
AK34
AK5
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AL6
AL9
AN2
AN34
AP12
AP15
AP18
AP21
AP24
AP27
AP3
AP30
AP33
AP6
AP9
B12
B15
B21
B24
B27
B3
B30
B33
B6
B9
C2
C34
E12

NB9M-GE & NB9P-GS --> 0.1uF

4700P_0402_16V7K

470P

IFPD
L87
1

1U_0402_6.3V4Z

4700P_0402_25V7K

IFPC_PLLVDD

AJ8

IFPC_IOVDD

AK8

IFPD_IOVDD

BLM18PG181SN1D_0603

U71E

14/16 XTAL_PLL

1U_0402_6.3V4Z

BLM18PG181SN1D_0603

C1261

1U_0402_6.3V4Z

C1085

GPU_PLLVDD

0.1U_0402_16V4Z

C1086

C1087

AE9
AD9
AF9

PLLVDD
VID_PLLVDD
SP_PLLVDD

C1257

1U_0402_6.3V4Z

C1256

C1259

C1255

R973
10K_0402_5%

4700P_0402_16V7K

36 mA

DPL3_TXC
DPL3_TXC

AR4
AR5

DPL2_TXD0
DPL2_TXD0

AP5
AN5

C1088

470P

0.1U_0402_16V4Z

1U_0402_6.3V4Z
XTALSSIN

B1

XTALIN

XTALOUTBUFF

D1

XTALOUT

B2

27M_CLK

@ R968
10K_0402_5%

2 499_0402_1%
2 499_0402_1%

HDMI_TX1HDMI_TX1+

R963 1
R962 1

2 499_0402_1%
2 499_0402_1%

HDMI_TX2HDMI_TX2+

R961 1
R960 1

2 499_0402_1%
2 499_0402_1%

D
Q74
2N7002_SOT23-3

R969
10K_0402_5%

2
G

+3VS

NB9P-GS_BGA_969P

1 @
C1090

1 @
C1089

AR7
AR8

2 499_0402_1%
2 499_0402_1%

R965 1
R964 1

NB9P-GS_BGA 969~D

XTALOUT

AN7
AP7

DPL0_TXD2
DPL0_TXD2

R967 1
R966 1

HDMI_TX0HDMI_TX0+

NB9P-GS_BGA 969~D

D2
1

15 27M_SSC

DPL1_TXD1
DPL1_TXD1

HDMI_CLKHDMI_CLK+

L66

4.7U_0603_6.3V6K

NB9M-GE & NB9P-GS-->Pull down 500 ohm resistor and 2N7002


1

+PCIE

C1258

18P_0402_50V8J

18P_0402_50V8J

27M_CLK
@
R972
10K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

15 27M_CLK

2006/02/13

Deciphered Date

2006/03/10

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Thursday, January 08, 2009


1

Sheet

19

of

61

1102 R2046,R2047 no stuff


I/O

ACTIVE

USAGE

GPIO0

IN

N/A

Primary DVI Hot-plug

GPIO1

IN

N/A

2nd DVI Hot-plug

1
1

VGA Core power

+3VS

GPIO

@
R2046
2.2K_0402_5%

1107 Swap THERMDN and THERMDP

+NVVDD

+NVVDD

Close to VGA

16/16 NVVDD

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

0.1U_0402_16V7K

0.1U_0402_16V7K

GPIO2

OUT

Panel Back-Light PWM

GPIO3

OUT

Panel Power Enable

GPIO4

C1099

C1100

0.1U_0402_16V7K
0.1U_0402_16V7K
C1104

4700P_0402_25V7K

C1106

4700P_0402_25V7K
4700P_0402_25V7K
C1117

C1109

10U_0603_6.3V6M

4700P_0402_25V7K
C1114

C1115

4700P_0402_25V7K

4700P_0402_25V7K

C1118

10U_0603_6.3V6M

C1108

C1113

C1119

N/A

B5

THERMDP

NVVDD VID0

GPIO6

OUT

N/A

NVVDD VID1

GPIO7

OUT

N/A

FBVDD VID0

GPIO8

IN

Thermal Alert

GPIO9

OUT

FAN PWM

GPIO10

OUT

N/A

FBVref Select

GPIO11

OUT

N/A

SLI SYNCO

GPIO12

IN

N/A

AC Detect

GPIO13

OUT

PS Control or HDMI_CEC

GPIO14

OUT

PS Control

T79
T80
T81
T82
T83

I2CS_SCL
I2CS_SDA

E2
E1

I2CA_SDA
I2CA_SCL

I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA

E3
E4
F4
G5
D5
E5

DDC2_CLK
DDC2_DATA

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST

AP14
AR14
AN14
AN16
AP16

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SWAP_RDY_A/GPIO22
STEREO/GPIO23

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST

10U_0603_6.3V6M

R976 2
R977 1

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6

1 0_0402_5%
2 0_0402_5%

R2066
2

2.2K_0402_5%
1
+3VS

2
R2065

1
2.2K_0402_5%

Thermal
LVDS
HDMI

1109 nVIDIA suggestion -- change HDMI DDC to I2CD

HDMI_DETECT

HDMI_DETECT 44

ENVDD
ENABLT
GPU_VID0
GPU_VID1
THERM#_VGA_R
SNN_GPIO9

SMB_EC_CK2 4,40
SMB_EC_DA2 4,40
DDC2_CLK 17
DDC2_DATA 17
HDMICLK_VGA 44
HDMIDAT_VGA 44

R994
1
1
R995

0_0402_5%
THERM_SCI#
2
VGA_THERM_SCI#
2
0_0402_5%

ENAVDD 17
ENABLT 40
GPU_VID0 52
GPU_VID1 52
THERM_SCI# 28,40

+3VS
ENABLT
GPU_VID0
GPU_VID1

R1016

@ R2146
2

10K_0402_5%
1

2
@ R2147

1
10K_0402_5%

10K_0402_5%

VADER 1.1 PV-- Nvidia request

NB9P-GS_BGA 969~D

4700P_0402_25V7K

C1120

C1116

U71L
+3VS

4700P_0402_25V7K

12/16 MISC1
THERMDN

C1103

0.1U_0402_16V7K

C1112

OUT

B4

Panel Back-Light Enable


VGA_THERMDA

0.1U_0402_16V7K
C1107

4700P_0402_25V7K

C1111

C1102

0.1U_0402_16V7K

0.1U_0402_16V7K

C1110

C1101

0.1U_0402_16V7K
C1105

0.1U_0402_16V7K

GPIO5
C1098

OUT

VGA_THERMDC

U71O

+NVVDD

@
R2047
2.2K_0402_5%

2
2

U71N

4700P_0402_25V7K

NB9P-GS_BGA 969~D

AA9
AB9
W9
Y9

11/16 MIOB
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ

AA7

MIOBCAL_PD_VDDQ

AA6

MIOBCAL_PU_GND

AF1

U71M

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6
W5
W7
V7

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD11

MIOB_CTL3
MIOB_HSYNC
MIOB_VSYNC
MIOB_DE

W3
W1
W2
Y5

MIOB_CTL3
MIOB_HSYNC

MIOB_CLKOUT
MIOB_CLKOUT
MIOB_CLKIN

V4
W4
AE1

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
MIOBD12
MIOBD13
MIOBD14
MIOBD15
MIOBD16
MIOBD17

MIOB_VREF

+3VS

T87
T85
T86
T84
T88
T93
T91
T89
T90
T92
T108

STRAP0
STRAP1
STRAP2

P9
R9
T9
U9

10/16 MIOA
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ
MIOA_VDDQ

U5

MIOACAL_PD_VDDQ

T5

MIOACAL_PU_GND

N5

MIOA_VREF

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11
MIOAD12
MIOAD13
MIOAD14

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

MIOA_CTL3
MIOA_HSYNC
MIOA_VSYNC
MIOA_DE

P5
N3
L3
N2

MIOA_CLKOUT
MIOA_CLKOUT
MIOA_CLKIN

R4
T4
N4

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9

T98
T96
T94
T95
T97
T103
T101
T99
T100
T102

+3VS

@
R981 1

2 5.1K_0402_5%

R982 1

2 45.3K_0402_5%

R984 1

2 10K_0402_5%

@
R985 1

2 5.1K_0402_5%

@
R986 1

2 5.1K_0402_5%

R987 1

2 10K_0402_5%

@
R988 1

2 30K_0402_1%

@
R989 1

2 5.1K_0402_5%

@
R990 1
R992 1

2 5.1K_0402_5%

R991 1

2 15K_0402_5%

@
R993 1

pull up 45K

STRAP1

pull down 10K

STRAP2

pull up 10K

ROM_SO

pull up 5K

ROM_CLK

pull down 15K

NB9P-GS_BGA 969~D

pull up 5K
pull up 5K

MIOA_DE

NB9P-GS_BGA 969~D

R1029

pull up 45K

T104

R983

10K_0402_5%

pull down 10K

T111

NB9M-GE/NB9P-GE2

MIOA_HSYNC

10K_0402_5%

NB9P-GS

STRAP0

T105

STRAP0
STRAP1
STRAP2
ROM_SI
ROM_SO
ROM_SCLK

19 ROM_SI
19 ROM_SO
19 ROM_SCLK

MIOB_DE

MULTI LEVEL STRAPS For NB9M-Gx (64bit)


NB9P-GS and NB9P-GE2 is as same as NB9M-GE-B

T109
T110

STRAP2 -- R987

pull down 15K

ROM_SI

2 5.1K_0402_5%
2 5.1K_0402_5%

Samsung 16Mx16

pull down 10K

Hynix 16Mx16

pull down 20K

Samsung 32Mx16

pull down 30K

Hynix 32Mx16

pull down 45K

Qimonda 32Mx16

pull down 35K

R988

VGA Thermal Sensor ADM1032ARMZ


+3VS

Closed to VGA

+3VS

0.1U_0402_16V4Z

+3VS

@
U62

VDD

VGA_THERMDA

@ C1097
1
2

D+

VGA_THERMDC

D-

2200P_0402_50V7K

THERM#_VGA

THERM#

@ R975
1
2
10K_0402_5%

@
C1096

@
R974
10K_0402_5%

SCLK

VGA_SM_CLK

SDATA

VGA_SM_DA

ALERT#

VGA_THERM_SCI#

GND

@
R1032
@
R980

1 0_0402_5%

SMB_EC_CK2

2 0_0402_5%

SMB_EC_DA2

ADM1032ARMZ REEL_MSOP8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

Deciphered Date

2006/03/10

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Thursday, January 08, 2009

Sheet

20

of

61

VRAM Interface
DATA Bus
Address

+1.8VS

U71B

22,23 MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

22,23 DQMA[7..0]

R30
R32
P31
N30
L31
M32
M30
L30
P33
P34
N35
P35
N34
L33
L32
N33
K31
K30
G30
K32
G32
H30
F30
G31
H33
K35
K33
G34
K34
E33
E34
G33
AG30
AH31
AG32
AF31
AF30
AD30
AC32
AE30
AE32
AF33
AF34
AE35
AE33
AE34
AC35
AB32
AN33
AK32
AL33
AM33
AL31
AK30
AJ30
AH30
AM35
AH33
AH35
AH32
AH34
AM34
AL35
AJ33

DQMA0 P30
DQMA1 P32
DQMA2 J30
DQMA3 H34
DQMA4 AF32
DQMA5 AF35
DQMA6 AL32
DQMA7 AL34

22 QSA[3..0]

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

23 QSA[7..4]

22 QSA#[3..0]

N31
L34
J32
H35
AE31
AC33
AJ32
AJ34

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

23 QSA#[7..4]

2/16 FBA
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

N32
L35
H31
G35
AD32
AC34
AJ31
AJ35

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

P29
R29
L29
M29
AD29
AE29
AG29
AH29

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22

0.022U_0402_16V7K

C1132

0.1U_0402_16V4Z

C1133

C1126

0.022U_0402_16V7K

C1142

C1135

C1144

C1136

C1145

0.1U_0402_16V4Z

C1146

A3

CMD1

A0

CMD2

A2

CMD3

A1

4700P_0402_25V7K

4700P_0402_25V7K

C1148

C1147

4700P_0402_25V7K

0.1U_0402_16V4Z

1U_0402_6.3V4Z

C1128

C1149

C1150

0.1U_0402_16V4Z

0.022U_0402_16V7K

C1151

U71C

A0

A3

CMD5

A4

CMD6

A5

CMD8

CS#

CS#

CMD9

WE#

WE#

CMD10

BA0

BA0

CMD11

CKE

CKE

CMD12

ODT

ODT

C1129

1U_0402_6.3V4Z

A12

A12

CMD15

RAS#

RAS#

A11

A11

CMD17

A10

A10

CMD18

BA1

BA1

CMD19

A8

A8

CMD20

A9

A9

CMD21

A6

A6

CMD22

A5

CMD23

A7

CMD24

A4

CMD25

CAS#

CAS#

CMD26

A13

A13

CMD27

BA2

BA2

A7

CMD28
CMD29
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

T32
T31
AC31
AC30

CLKA0
CLKA0#
CLKA1
CLKA1#

CMD30
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6

CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25

22
22,23
22
22,23
23
23
23

CMDA8 22,23
CMDA9 22,23
CMDA10 22,23
CMDA11 22,23
CMDA12 22,23
CMDA13 23
CMDA14 22,23
CMDA15 22,23
CMDA16 22,23
CMDA17 22,23
CMDA18 22,23
CMDA19 22,23
CMDA20 22,23
CMDA21 22,23
CMDA22 22
CMDA23 22,23
CMDA24 22
CMDA25 22,23

24,25 DQMB[7..0]

ODT
CKE

CMDA12

R1027

2 10K_0402_5%

CMDA11

R1028

2 10K_0402_5%
24 QSB[3..0]

25 QSB[7..4]

24 QSB#[3..0]

25 QSB#[7..4]
CLKA0 22
CLKA0# 22
CLKA1 23
CLKA1# 23

D11
E11
F10
D8
F8
F9
E8
F12
B11
C13
A11
B8
A8
C8
C11
C10
D12
E13
F17
F15
F16
E16
F14
F13
D13
A13
B13
A14
C16
A17
B16
D16
D24
D26
E25
F25
F27
E28
F28
D29
A25
B25
D25
C26
C28
B28
A28
A29
E29
F29
D30
E31
C33
D33
F32
E32
B29
C29
B31
C31
B32
C32
B34
B35

3/16 FBC
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7

F11
D10
D15
A16
D27
D28
D34
A34

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

E10
A10
D14
C14
E26
B26
D32
A32

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

D9
B10
E14
B14
F26
A26
D31
A31

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

G11
G12
G14
G15
G24
G25
G27
G28

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

A2

CMD16

CMD14

0.022U_0402_16V7K

24,25 MDB[63..0]

A1

CMD4

CMD13
4700P_0402_25V7K

+1.8VS

32..63

CMD7

4.7U_0603_6.3V6K

0.022U_0402_16V7K

C1143

C1134

0.022U_0402_16V7K

4700P_0402_25V7K

4.7U_0603_6.3V6K

0..31

CMD0

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

+1.8VS
FBA_DEBUG

FB_DLLAVDD
FB_PLLAVDD

T30

R997 1

2
60.4_0402_1%

L69
1

1U_0402_6.3V4Z

AG27
AF27

C1155

CKE
ODT

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

C17
B19
D18
F21
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20

CMDB0
CMDB1
CMDB2
CMDB3
CMDB4
CMDB5
CMDB6

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

E17
D17
D23
E23

CLKB0
CLKB0#
CLKB1
CLKB1#

FBC_DEBUG

G19

C1131

4.7U_0603_6.3V6K

C1124

0.022U_0402_16V7K

4700P_0402_25V7K
C1137

C1123

4.7U_0603_6.3V6K

C1139

C1127

4700P_0402_25V7K

C1140

C1141

0.1U_0402_16V4Z

R1025

2 10K_0402_5%

CMDB12

R1026

2 10K_0402_5%

CMDB8
CMDB9
CMDB10
CMDB11
CMDB12
CMDB13
CMDB14
CMDB15
CMDB16
CMDB17
CMDB18
CMDB19
CMDB20
CMDB21
CMDB22
CMDB23
CMDB24
CMDB25

0.1U_0402_16V4Z

CMDB11

CMDB0
CMDB1
CMDB2
CMDB3
CMDB4
CMDB5
CMDB6

C1125

0.022U_0402_16V7K

C1138

24
24,25
24
24,25
25
25
25

CMDB8 24,25
CMDB9 24,25
CMDB10 24,25
CMDB11 24,25
CMDB12 24,25
CMDB13 25
CMDB14 24,25
CMDB15 24,25
CMDB16 24,25
CMDB17 24,25
CMDB18 24,25
CMDB19 24,25
CMDB20 24,25
CMDB21 24,25
CMDB22 24
CMDB23 24,25
CMDB24 24
CMDB25 24,25

CLKB0 24
CLKB0# 24
CLKB1 25
CLKB1# 25

C1156

R996 1

+PCIE

J19 0.01U_0402_25V7K
J18
1
1
C1152
C1153
2

0.057 Amps

L68
2

BLM18PG181SN1D_0603
C1154

2
2
1U_0402_6.3V4Z 4.7U_0603_6.3V6K

K27 R998

2 30_0402_1%

FBCAL_PU_GND

L27 R1000

2 30_0402_1%

FBCAL_TERM_GND

M27 R1001
@

2 40.2_0402_1%

FBCAL_PD_VDDQ

C1157
4.7U_0603_6.3V6K

2
60.4_0402_1%

+1.8VS

NB9P-GS_BGA 969~D

0.01U_0402_25V7K

FB_VREF

1 @
C1158
NB9P-GS_BGA 969~D

Rb
2

0.022U_0402_16V7K

0.1U_0402_16V4Z

C1122

4700P_0402_25V7K

BLM18PG181SN1D_0603

J27
@
R1002
1K_0402_1%

FBAC_DLLAVDD
FBAC_PLLAVDD

Rt

1K_0402_1%

C1130

+1.8VS

1
@
R999

+PCIE

+1.8VS

N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

for NB9P-GE, the R998/R1000 are 40 ohm


For NB9M-GS-B are 30.1 ohm.

0.1U_0402_16V4Z

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

VREF = 0.5 * FBVDDQ


DDR2: 1.0V = 2.0V * 1K/(1K + 1K)
FBVREF = FBVDDQ * Rb/(Rt + Rb)

2006/02/13

Deciphered Date

2006/03/10

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Thursday, January 08, 2009

Sheet

21

of

61

DATA Bus

VRAM DDR2 chips (256MB & 512MB)

Address

32Mx16 DDR2 400MHz *8==>512MB


32Mx16 DDR2 400MHz *4==>256MB
21,23 QSA[7..0]

QSA#[7..0]

21,23 QSA#[7..0]

DQMA[7..0]

21,23 DQMA[7..0]

@
U63
21,23 CMDA10
21,23 CMDA18
21,23
21,23
21,23
21,23
21,23
21,23
21,23
21
21
21
21
21,23
21,23

CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA22
CMDA24
CMDA0
CMDA2
CMDA3
CMDA1

CMDA10
CMDA18

L2
L3

BA0
BA1

CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA22
CMDA24
CMDA0
CMDA2
CMDA3
CMDA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

K8
J8

CK
CK

CMDA11

K2

CKE

@
U64
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDA7
MDA0
MDA5
MDA2
MDA3
MDA4
MDA1
MDA6
MDA23
MDA18
MDA20
MDA16
MDA17
MDA21
MDA19
MDA22

CMDA10
CMDA18

L2
L3

BA0
BA1

CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA22
CMDA24
CMDA0
CMDA2
CMDA3
CMDA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

K8
J8

CK
CK

CMDA11

K2

CKE

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

MDA27
MDA28
MDA24
MDA31
MDA30
MDA25
MDA29
MDA26
MDA15
MDA9
MDA12
MDA8
MDA11
MDA13
MDA10
MDA14

21,23 CMDA9
21,23 CMDA15
21,23 CMDA25

21,23 CMDA12

CMDA8

L8

CS

CMDA9

K3

WE

CMDA15

K7

RAS

CMDA25

L7

CAS

DQMA2
DQMA0

F3
B3

LDM
UDM

CMDA12

K9

ODT

QSA2
QSA#2

F7
E8

LDQS
LDQS

R1003
1K_0402_1%

QSA0
QSA#0

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+MEM_VREFA0

R1004

1K_0402_1%

C1163
0.1U_0402_16V4Z

+1.8VS

L76
2

VSS1
VSS2
VSS3
VSS4
VSS5

FBMA-L10-160808-300LMT

2
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

+1.8VS

A0

CMD2

A2

CMD3

A1

A0
A1

CMD4

A3

CMD5

A4

CMD6

A5

C1161
0.1U_0402_16V4Z

C1162

CMDA8

L8

CS

CMDA9

K3

WE

CMDA15

K7

RAS

CMDA25

L7

CAS

DQMA1
DQMA3

F3
B3

LDM
UDM

CMDA12

K9

ODT

QSA1
QSA#1

F7
E8

LDQS
LDQS

QSA3
QSA#3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+1.8VS

L75
2

+MEM_VREFA0

A3
E3
J3
N1
P9

HY5PS561621F-25

CS#

CS#

CMD9

WE#

WE#

CMD10

BA0

BA0

CMD11

CKE

CKE

CMD12

ODT

ODT
A2

CMD14

A12

A12

CMD15

RAS#

RAS#

CMD16

A11

A11

CMD17

A10

A10

CMD18

BA1

BA1

CMD19

A8

A8

CMD20

A9

A9

CMD21

A6

A6

CMD22

A5

CMD23

A7

CMD24

A4

CMD25

CAS#

CAS#

CMD26

A13

A13

CMD27

BA2

BA2

A7

CMD28

FBMA-L10-160808-300LMT

CMD29
CMD30

4.7U_0805_6.3V6K

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

CMD8

C1159
0.1U_0402_16V4Z

C1160
4.7U_0805_6.3V6K

CLKA0

21 CLKA0

21,23 CMDA8

CMD1

32..63

CMD13

21,23 CMDA11

A3

CMD7

MDA[63..0]

21,23 MDA[63..0]

CMD0

R1005
475_0402_1%

HY5PS561621F-25

Vref= 0.5* 1.8V for NB9M, R1004=1K ohm

CLKA0#

21 CLKA0#

Vref= 0.5* 1.8V for NB9P-GS/GE2, R1004=1K ohm

QSA[7..0]

0..31

475ohm 1% for NB9M


NB9P-GE, keep 240ohm

DDR2 BGA MEMORY

+1.8VS

DDR BGA MEMORY

+1.8VS

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.1U_0402_16V4Z

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.01U_0402_16V7K

C1173

C1174

C1175

0.01U_0402_16V7K

C1176

C1177

0.1U_0402_16V4Z

C1178

C1179

0.1U_0402_16V4Z

C1180

C1164

0.01U_0402_16V7K

C1165

C1166

0.01U_0402_16V7K

C1167

C1168

0.1U_0402_16V4Z

C1169

C1170

0.1U_0402_16V4Z

C1171

0.01U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

22

of

61

DATA Bus

VRAM DDR2 chips (256MB & 512MB)

Address

CMD0

A3

32Mx16 DDR2 400MHz *8==>512MB


32Mx16 DDR2 400MHz *4==>256MB

CMD1

A0

CMD2

A2

CMD3

A1

21,22 QSA[7..0]
21,22 MDA[63..0]

A3

DQMA[7..0]

CMD5

A4

QSA#[7..0]

CMD6

A5

QSA[7..0]

CMD7

MDA[63..0]

CMD8

CS#

CS#

CMD9

WE#

WE#

CMD10

BA0

BA0

CMD11

CKE

CKE

CMD12

ODT

@
U65
21,22 CMDA10
21,22 CMDA18
21,22
21,22
21,22
21,22
21,22
21,22
21,22
21
21
21
21
21,22
21,22

CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA6
CMDA5
CMDA4
CMDA13
CMDA3
CMDA1

21,22 CMDA11

21,22 CMDA8
21,22 CMDA9
21,22 CMDA15
21,22 CMDA25

21,22 CMDA12

CMDA10
CMDA18

L2
L3

CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA6
CMDA5
CMDA4
CMDA13
CMDA3
CMDA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

CMDA11

K2

CKE

CMDA8

L8

CS

CMDA9

K3

WE

CMDA25

L7

DQMA5
DQMA4

F3
B3

CMDA12

R1008
1K_0402_1%

CK
CK

F7
E8

LDQS
LDQS

QSA4
QSA#4

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

1
R1009
1K_0402_1%
2

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

LDM
UDM

QSA5
QSA#5

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

CAS

ODT

+MEM_VREFA1

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

RAS

K9

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

K8
J8

K7

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BA0
BA1

CLKA1#
CLKA1

CMDA15

@
U66

+1.8VS

A1

CMD4

MDA39
MDA32
MDA38
MDA34
MDA33
MDA37
MDA35
MDA36
MDA44
MDA43
MDA47
MDA40
MDA41
MDA46
MDA42
MDA45

+1.8VS

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

L2
L3

CMDA14
CMDA16
CMDA17
CMDA20
CMDA19
CMDA23
CMDA21
CMDA6
CMDA5
CMDA4
CMDA13
CMDA3
CMDA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

L78
2

CMDA11

K2

CKE

CMDA8

L8

CS

CMDA9

K3

WE

FBMA-L10-160808-300LMT

C1183
0.1U_0402_16V4Z

CMDA25

L7

DQMA6
DQMA7

F3
B3

CMDA12
4.7U_0805_6.3V6K

CK
CK

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

CAS
LDM
UDM
ODT

QSA6
QSA#6

F7
E8

LDQS
LDQS

QSA7
QSA#7

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+MEM_VREFA1

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

RAS

K9

C1184

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

K8
J8

K7

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BA0
BA1

CLKA1#
CLKA1

CMDA15

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

CMDA10
CMDA18

MDA59
MDA60
MDA58
MDA62
MDA63
MDA56
MDA61
MDA57
MDA51
MDA53
MDA48
MDA55
MDA52
MDA49
MDA54
MDA50

L77
2

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

HY5PS561621F-25

CMD14

A12

A12

CMD15

RAS#

RAS#

CMD16

A11

A11

CMD17

A10

A10

CMD18

BA1

BA1

CMD19

A8

A8

CMD20

A9

A9

CMD21

A6

A6

CMD22

A5

CMD23

A7

CMD24

A4

CMD25

CAS#

CAS#

CMD26

A13

A13

CMD27

BA2

BA2

A7

CMD29
CMD30

C1181
0.1U_0402_16V4Z

C1182
4.7U_0805_6.3V6K

CLKA1

21 CLKA1

R1010
475_0402_1%
CLKA1#

21 CLKA1#
C1185
0.1U_0402_16V4Z

A2

CMD28

FBMA-L10-160808-300LMT

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ODT

CMD13

+1.8VS

21,22 QSA#[7..0]

A0

21,22 DQMA[7..0]

32..63

0..31

HY5PS561621F-25

475ohm 1% for NB9M


NB9P-GE, keep 240ohm

1107 Change R1010 to 475 ohm

Vref= 0.5* 1.8V for NB9M, R1009=1K ohm


Vref= 0.5* 1.8V for NB9P-GS/GE2, R1009=1K ohm

DDR2 BGA MEMORY

+1.8VS

DDR BGA MEMORY

+1.8VS

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.1U_0402_16V4Z

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.01U_0402_16V7K

C1195

C1196

C1197

0.01U_0402_16V7K

C1198

C1199

0.1U_0402_16V4Z

C1200

C1201

0.1U_0402_16V4Z

C1202

C1186

0.01U_0402_16V7K

C1187

C1188

0.01U_0402_16V7K

C1189

C1190

0.1U_0402_16V4Z

C1191

C1192

0.1U_0402_16V4Z

C1193

0.01U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

23

of

61

DATA Bus

VRAM DDR2 chips (256MB & 512MB)

Address

CMD0

A3

32Mx16 DDR2 400MHz *8==>512MB

CMD1

A0

CMD2

A2

DQMB[7..0]

CMD3

A1

QSB#[7..0]

CMD4

A3

QSB[7..0]

CMD5

A4

MDB[63..0]

CMD6

A5

21,25 DQMB[7..0]
21,25 QSB#[7..0]
D

21,25 QSB[7..0]
21,25 MDB[63..0]

0..31

32..63
A0
A1
D

CMD7

21,25
21,25
21,25
21,25
21,25
21,25
21,25
21
21
21
21
21,25
21,25

CMDB14
CMDB16
CMDB17
CMDB20
CMDB19
CMDB23
CMDB21
CMDB22
CMDB24
CMDB0
CMDB2
CMDB3
CMDB1

CMDB10
CMDB18

L2
L3

BA0
BA1

CMDB14
CMDB16
CMDB17
CMDB20
CMDB19
CMDB23
CMDB21
CMDB22
CMDB24
CMDB0
CMDB2
CMDB3
CMDB1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB0#
CLKB0

K8
J8

CMDB11

K2

21,25 CMDB11

21,25 CMDB8
21,25 CMDB9
21,25 CMDB15
21,25 CMDB25

21,25 CMDB12

VRAM2@
R1013

CKE

CMDB8

L8

CMDB9

K3

WE

CMDB15

K7

RAS

CS

CMDB25

L7

CAS

DQMB2
DQMB1

F3
B3

LDM
UDM

CMDB12

K9

ODT

QSB2
QSB#2

F7
E8

LDQS
LDQS

QSB1
QSB#1

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

1K_0402_1%
+MEM_VREFB0

1
VRAM2@
R1014
1K_0402_1%

1 VRAM2@
C1207
2

0.1U_0402_16V4Z

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDB11
MDB13
MDB9
MDB14
MDB15
MDB8
MDB12
MDB10
MDB18
MDB21
MDB17
MDB23
MDB22
MDB16
MDB20
MDB19

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

CMDB10
CMDB18

L2
L3

BA0
BA1

CMDB14
CMDB16
CMDB17
CMDB20
CMDB19
CMDB23
CMDB21
CMDB22
CMDB24
CMDB0
CMDB2
CMDB3
CMDB1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB0#
CLKB0

K8
J8

CMDB11

K2

CK
CK
CKE

+1.8VS

VRAM2@
L80
2

FBMA-L10-160808-300LMT
1 VRAM2@
C1205
2

+1.8VS

CK
CK

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

0.1U_0402_16V4Z

1 VRAM2@
C1206
2

CMDB8

L8

CMDB9

K3

WE

CMDB15

K7

RAS

CS

CMDB25

L7

CAS

DQMB3
DQMB0

F3
B3

LDM
UDM

CMDB12

K9

ODT

QSB3
QSB#3

F7
E8

LDQS
LDQS

QSB0
QSB#0

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

MDB0
MDB6
MDB2
MDB4
MDB5
MDB3
MDB7
MDB1
MDB27
MDB28
MDB24
MDB30
MDB31
MDB25
MDB29
MDB26

+1.8VS

VRAM2@
L79
2

HY5PS561621F-25

WE#

CMD10

BA0

BA0

CMD11

CKE

CKE

CMD12

ODT

ODT
A2

CMD14

A12

A12

CMD15

RAS#

RAS#

CMD16

A11

A11

CMD17

A10

A10

CMD18

BA1

BA1

CMD19

A8

A8

CMD20

A9

A9

CMD21

A6

A6

CMD22

A5

CMD23

A7

CMD24

A4

CMD25

CAS#

CAS#

CMD26

A13

A13

CMD27

BA2

BA2

A7

FBMA-L10-160808-300LMT

CMD28
1 VRAM2@
C1203

4.7U_0805_6.3V6K

+MEM_VREFB0

CS#

WE#

CMD13

1 VRAM2@
C1204

0.1U_0402_16V4Z

CMD29
CMD30

4.7U_0805_6.3V6K

CLKB0

21 CLKB0

21,25 CMDB10
21,25 CMDB18

@
U68

CS#

CMD9

HY5PS561621F-25

CLKB0#

21 CLKB0#

Vref= 0.5* 1.8V for NB9M, R1014=1K ohm

VRAM2@
R1015
475_0402_1%

@
U67

CMD8

475ohm 1% for NB9M


NB9P-GE, keep 240ohm

Vref= 0.5* 1.8V for NB9P-GS/GE2, R1014=1K ohm

1107 Change R1015 to 475 ohm


DDR2 BGA MEMORY
+1.8VS

DDR BGA MEMORY

+1.8VS

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.1U_0402_16V4Z

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.01U_0402_16V7K

1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@


C1217
C1218
C1219
C1220
C1221
C1222
C1223
C1224

1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@


C1208
C1209
C1210
C1211
C1212
C1213
C1214
C1215

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2
0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

24

of

61

DATA Bus

VRAM DDR2 chips (256MB & 512MB)

Address

CMD0

A3

32Mx16 DDR2 400MHz *8==>512MB

CMD1

A0

CMD2

A2

CMD3

A1

DQMB[7..0]

21,24 DQMB[7..0]

QSB#[7..0]

21,24 QSB#[7..0]
D

QSB[7..0]

21,24 QSB[7..0]

MDB[63..0]

21,24 MDB[63..0]

0..31

32..63
A0
A1

CMD4

A3

CMD5

A4

CMD6

A5

CMD7

21,24
21,24
21,24
21,24
21,24
21,24
21,24
21
21
21
21
21,24
21,24

CMDB14
CMDB16
CMDB17
CMDB20
CMDB19
CMDB23
CMDB21
CMDB6
CMDB5
CMDB4
CMDB13
CMDB3
CMDB1

CMDB10
CMDB18

L2
L3

BA0
BA1

CMDB14
CMDB16
CMDB17
CMDB20
CMDB19
CMDB23
CMDB21
CMDB6
CMDB5
CMDB4
CMDB13
CMDB3
CMDB1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB1#
CLKB1

K8
J8

CMDB11

K2

21,24 CMDB11

21,24 CMDB8
21,24 CMDB9
21,24 CMDB15
21,24 CMDB25

21,24 CMDB12

VRAM2@
R1018

CKE

CMDB8

L8

CMDB9

K3

WE

CMDB15

K7

RAS

CS

CMDB25

L7

CAS

DQMB5
DQMB4

F3
B3

LDM
UDM

CMDB12

K9

ODT

QSB5
QSB#5

F7
E8

LDQS
LDQS

QSB4
QSB#4

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

1K_0402_1%

VRAM2@
R1019

+MEM_VREFB1
B

1K_0402_1%

1 VRAM2@
C1229
2
0.1U_0402_16V4Z

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDB39
MDB35
MDB38
MDB33
MDB32
MDB36
MDB34
MDB37
MDB45
MDB43
MDB46
MDB40
MDB41
MDB47
MDB42
MDB44

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

CMDB10
CMDB18

L2
L3

BA0
BA1

CMDB14
CMDB16
CMDB17
CMDB20
CMDB19
CMDB23
CMDB21
CMDB6
CMDB5
CMDB4
CMDB13
CMDB3
CMDB1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB1#
CLKB1

K8
J8

CMDB11

K2

CK
CK
CKE

+1.8VS

VRAM2@
L82
2

FBMA-L10-160808-300LMT
1 VRAM2@
C1227
2

+1.8VS

CK
CK

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

1 VRAM2@
C1228

CMDB8

L8

CMDB9

K3

WE

CMDB15

K7

RAS

CS

CMDB25

L7

CAS

DQMB7
DQMB6

F3
B3

LDM
UDM

CMDB12

K9

ODT

QSB7
QSB#7

F7
E8

LDQS
LDQS

QSB6
QSB#6

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

MDB49
MDB55
MDB51
MDB53
MDB54
MDB48
MDB52
MDB50
MDB59
MDB60
MDB56
MDB63
MDB62
MDB58
MDB61
MDB57

+1.8VS

VRAM2@
L81
2

4.7U_0805_6.3V6K

+MEM_VREFB1

HY5PS561621F-25

WE#

CMD10

BA0

BA0

CMD11

CKE

CKE

CMD12

ODT

ODT
A2

CMD14

A12

A12

CMD15

RAS#

RAS#

CMD16

A11

A11

CMD17

A10

A10

CMD18

BA1

BA1

CMD19

A8

A8

CMD20

A9

A9

CMD21

A6

A6

CMD22

A5

CMD23

A7

CMD24

A4

CMD25

CAS#

CAS#

CMD26

A13

A13

CMD27

BA2

BA2

A7

FBMA-L10-160808-300LMT

CMD28
1 VRAM2@
C1225

0.1U_0402_16V4Z
2

CS#

WE#

CMD13

0.1U_0402_16V4Z

1 VRAM2@
C1226
2

CMD29
CMD30

4.7U_0805_6.3V6K

CLKB1

21 CLKB1

21,24 CMDB10
21,24 CMDB18

@
U70

CS#

CMD9

CLKB1#

21 CLKB1#

HY5PS561621F-25

VRAM2@
R1020
475_0402_1%

@
U69

CMD8

475ohm 1% for NB9M


NB9P-GE, keep 240ohm

1107 Change R1020 to 475 ohm

Vref= 0.5* 1.8V for NB9M, R1019=1K ohm


Vref= 0.5* 1.8V for NB9P-GS/GE2, R1019=1K ohm
DDR2 BGA MEMORY
+1.8VS

DDR BGA MEMORY

+1.8VS

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.1U_0402_16V4Z

1000P_0402_50V7K

0.01U_0402_16V7K

4.7U_0805_6.3V6K

0.01U_0402_16V7K

1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@


C1239
C1240
C1241
C1242
C1243
C1244
C1245
C1246

1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@1 VRAM2@


C1230
C1231
C1232
C1233
C1234
C1235
C1236
C1237

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2
0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

25

of

61

+3VS

PCI_DEVSEL#

2 8.2K_0402_5%

PCI_STOP#

R335 1

2 8.2K_0402_5%

PCI_TRDY#

R336 1

2 8.2K_0402_5%

PCI_FRAME#

R337 1

2 8.2K_0402_5%

PCI_PLOCK#

R338 1

2 8.2K_0402_5%

PCI_IRDY#

R339 1

2 8.2K_0402_5%

PCI_SERR#

R340 1

2 8.2K_0402_5%

PCI_PERR#

R341 1

2 8.2K_0402_5%

PCI_PIRQA#

R342 1

2 8.2K_0402_5%

PCI_PIRQB#

U58B
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

+3VS

R343 1

2 8.2K_0402_5%

PCI_PIRQC#

R344 1

2 8.2K_0402_5%

PCI_PIRQD#

R345 1

2 8.2K_0402_5%

PCI_PIRQE#

R346 1

2 8.2K_0402_5%

PCI_PIRQF#

R347 1

2 8.2K_0402_5%

PCI_PIRQG#

R348 2

1 8.2K_0402_5%

PCI_PIRQH#

R349 1

2 8.2K_0402_5%

PCI_REQ0#

R350 1

2 8.2K_0402_5%

PCI_REQ1#

R351 1

2 8.2K_0402_5%

PCI_REQ2#

R352 1

2 8.2K_0402_5%

PCI_REQ3#

A16 swap override Strap


Low= A16 swap override Enble
PCI_GNT3# High= Default*
PCI_GNT3#

@ R354
1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

J5
E1
J6
C4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

F1
G4
B6
A7
F13
F12
E6
F6

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

Place closely pin B10

PCI_REQ2#
PCI_REQ3#
PCI_GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

D8
B4
D6
A5

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

PCI_IRDY#

PLTRST#
PCICLK
PME#

C14
D4
R2

PLT_RST#
CLK_PCI_ICH
PCI_PME#

CLK_PCI_ICH
1

2 8.2K_0402_5%

R334 1

@
R353
10_0402_5%

R333 1

PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_RST# 39,40

@
C537
8.2P_0402_50V

PCI_SERR# 40

PLT_RST# 7,18,31,32,33,35
CLK_PCI_ICH 15
PCI_PME# 40

3/28 PCI_PME# Remvoe 8.2k pull high +3VALW


resistance.
C

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

H4
K6
F2
G2

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_PIRQH# 39

Boot BIOS Strap


B

PCI_GNT0#

SPI_CS#1

Boot BIOS Location

SPI

PCI

LPC

2
1K_0402_5%

*
+3VALW

28 SPI_CS1#_R

SPI_CS1#_R

@ R356
1

PCI_GNT0#

@ R355
1

2
1K_0402_5%
2
1K_0402_5%

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

26

of

61

ICH9M Internal VR Enable Strap


(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
+RTCVCC
+3VS

2 330K_0402_5% ICH_INTVRMEN

2 180K_0402_5% ICH_SRTCRST#

+3VS

ICH8M LAN100 SLP Strap


(Internal VR for VccLAN1.05 and VccCL1.05)

C538
0.1U_0402_16V4Z

@
R364

R2058

ICH_LAN100_SLP

2
1
10K_0402_5%

RTCX1
RTCX2

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

A25
F20
C22

RTCRST#
SRTCRST#
INTRUDER#

ICH_INTVRMEN
LAN100_SLP

B22
A22

INTVRMEN
LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

K5
K4
L6
K2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4/LFRAME#

K3

LPC_FRAME#

LDRQ0#
LDRQ1#/GPIO23

J3
J1

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

34 HDA_SDIN0
35 HDA_SDIN1
19 HDA_SDIN2

GLAN_COMP

P- HDD
S- HDD

30
30
30
30

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0
SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1
SATA_TXP1

1
1

C546
C547

1
1

GPIO56

B28
B27

GLAN_COMPI
GLAN_COMPO

AF6
AH4

HDA_BIT_CLK
HDA_SYNC

HDARST#

AE7

HDA_RST#

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2

AF4
AG4
AH3
AE5

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDOUT

AG5

HDA_SDOUT

AG7
AE8

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16
AH16
AF17
AG17

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA_LED#

C543
C545

B10

HDA_BITCLK
HDA_SYNC

PAD T51
PAD T52
41 SATA_LED#

LAN_TXD_0
LAN_TXD_1
LAN_TXD_2

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1_C
SATA_TXP1_C

AH13
AJ13
AG14
AF14

1212 Swap SATA1 and SATA4

CPU

D13
D12
E13

IHDA

24.9_0402_1% 1

LAN_RXD0
LAN_RXD1
LAN_RXD2

SATA

R371

F14
G13
D14

LAN / GLAN

@R365
@
R365 1

2 56_0402_5%

H_DPSLP#

@R366
@
R366 1

2 56_0402_5%

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

LPC_FRAME# 32,39,40

T50

A20GATE
A20M#

N7
AJ27

GATEA20
H_A20M#

DPRSTP#
DPSLP#

AJ25
AE23

H_DPRSTP_R#
H_DPSLP#

R369 1

FERR#

AJ26

R_H_FERR#

R370 1

CPUPWRGD

AD22

H_PWRGOOD

IGNNE#

AF25

H_IGNNE#

INIT#
INTR
RCIN#

AE22
AG25
L3

H_INIT#
H_INTR
KB_RST#

NMI
SMI#

AF23
AF24

H_NMI
H_SMI#

+VCCP

PAD

GATEA20 40
H_A20M# 4

R368
56_0402_5%

H_DPRSTP#
2
0_0402_5%

H_DPRSTP# 5,7,51
H_DPSLP# 5

H_FERR#
2
56_0402_5%

H_FERR# 4

H_PWRGOOD 5
H_IGNNE# 4

within 2" from R379

H_INIT# 4
H_INTR 4
KB_RST# 40

+VCCP
C

CLRP2
SHORT PADS

C23
C24

1U_0603_10V4Z

H_DPRSTP#

LPC_AD[0..3] 32,39,40

ICH_RTCX1
ICH_RTCX2

LPC

C539

30
30
30
30

2 10K_0402_5%
+VCCP

Low = Internal VR Disabled


High = Internal VR Enabled(Default)

RTC

2 20K_0402_5%

+1.5VS

2 8.2K_0402_5%

R362 1

@
R360

R367 1

R358 1

KB_RST#
SATA_LED#

U58A

+RTCVCC

GATEA20

2 330K_0402_5% LAN100_SLP

1015 add pull up to meet Intel design

R361

Low = Internal VR Disabled


High = Internal VR Enabled(Default)

H_NMI 4
H_SMI# 4

R374
56_0402_5%

STPCLK#

AH27

H_STPCLK#

THRMTRIP#

AG26

THRMTRIP_ICH#

TP12

AG27

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AH11
AJ11
AG12
AF12

SATA_RXN4_C
SATA_RXP4_C
SATA_TXN4_C
SATA_TXP4_C

C540 2
C541 2

1 0.01U_0402_50V7K
1 0.01U_0402_50V7K

SATA_RXN4_C 30
SATA_RXP4_C 30
SATA_TXN4 30
SATA_TXP4 30

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AH9
AJ9
AE10
AF10

SATA_RXN5_C
SATA_RXP5_C
SATA_TXN5_C
SATA_TXP5_C

C542 2
C544 2

1 0.01U_0402_50V7K
1 0.01U_0402_50V7K

SATA_RXN5_C 38
SATA_RXP5_C 38
SATA_TXN5 38
SATA_TXP5 38

SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS

AH18
AJ18
AJ7
AH7

CLK_PCIE_SATA#
CLK_PCIE_SATA

H_STPCLK# 4
R379

2 54.9_0402_1%

R357

0_0402_5%
2
1

2 1M_0402_5%

0_0402_5%
2
1

R363

ICH_INTVRMEN

SM_INTRUDER#

R359

H_THERMTRIP# 4,7,40

placed within 2" from


ICH9M

R382

ODD

e-SATA
De-feature disable

CLK_PCIE_SATA# 15
CLK_PCIE_SATA 15

2
24.9_0402_1%

ICH9-M ES_FCBGA676

Within 500 mils

1008 add them for Intel suggestion

XOR CHAIN ENTRANCE STRAP:RSVD

19 HDA_VGA_BITCLK
35 HDA_BITCLK_MDC
34 HDA_BITCLK_CODEC

+3VS

@ R383
@R383
1

@ R384
@R384
1

19 HDA_VGA_SYNC
35 HDA_SYNC_MDC
34 HDA_SYNC_CODEC

HDA_SDOUT_CODEC
2
1K_0402_5%

ICH_RSVD
2
1K_0402_5%

19 HDA_VGA_RST#
35 HDA_RST#_MDC
34,40 HDA_RST#_CODEC
ICH_RSVD 28
19 HDA_VGA_SDOUT
35 HDA_SDOUT_MDC
34 HDA_SDOUT_CODEC

R439
R373
R372

33_0402_5%
33_0402_5%
33_0402_5%

1
1
1

2
2
2

HDA_BITCLK

R440
R375
R376

33_0402_5%
33_0402_5%
33_0402_5%

1
1
1

2
2
2

HDA_SYNC

R442
R378
R377

33_0402_5%
33_0402_5%
33_0402_5%

1
1
1

2
2
2

HDARST#

R444
R380
R381

33_0402_5%
33_0402_5%
33_0402_5%

1
1
1

2
2
2

HDA_SDOUT

VGA

ICH9-M
@
BATT1

MDC

CODEC
+RTCVCC

+3VL

CR2032 RTC BATTERY

BATT1.1

D36
W=20mils

0125 Change C548,C549 to 18PF


ICH_RSVD

HDA_BITCLK
1

R386
1

HDA_SDOUT_CODEC

ICH_RTCX1
ICH_RTCX2

C548

2
C549

18P_0402_50V8J

18P_0402_50V8J

Y3
1

32.768KHZ_12.5P_MC-146

W=20mils
2

2
1

0_0402_5%
@
R385
10_0402_5%

10M_0402_5%

0
A

R875
1

3 W=20mils

R876
1

CONN@
JBATT1
2

W=20mils

1K_0402_5%

DAN202U_SC70
C906
2.2U_0603_6.3V4Z

1
2
3
4

1
2
GND
GND
ACES_85205-02001

Place near ICH9


A

@
C550
10P_0402_25V8K

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

27

of

61

20080731 Add C2130 for 2F issue

@ R685
R686
@ R687

R689
R690
R691
R692
R693
R694
@ R870

PAD
GPIO18

@
R402
10K_0402_5%

CR_WAKE#

@
R403
10K_0402_5%

GPIO20

T57

4 XDP_DBRESET#
7 PM_BMBUSY#
40 EC_LID_OUT#

OCP#

15 H_STP_PCI#
15 H_STP_CPU#

PM_BMBUSY#

EC_SCI#_SB

0718 INSTALL R179

1
2
10K_0402_5%

GPIO49

GPIO57
EXP_CPPE#
GPIO21
GPIO19
GPIO36

R423 1
8.2K_0402_5%

+3VS

R411
R414
R416
R417
R418
@R419
@
R419
@R695
@
R695
B

R696
@R2096
@
R2096
R2101

32 EXP_CPPE#
+3VS
34 SB_SPKR
7 MCH_ICH_SYNC#
27 ICH_RSVD

1
2
@R424
@
R424 1K_0402_5%

STP_PCI#
STP_CPU#

1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
1K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%

ICH_LOW_BAT#

PMSYNC#/GPIO0

L4

CLKRUN#
WAKE#
SERIRQ
THRM#

D21

VRMPWRGD

A20

TP11

AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8

GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5

SB_SPKR
M7
MCH_ICH_SYNC# AJ24
ICH_RSVD
B21
AH20
AJ20
AJ21

LINKALERT#

low -->default
High -->No boot

S4_STATE#/GPIO26

C10

S4_STATE#

PWROK

G20

PM_PWROK

SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10

DPRSLPVR/GPIO16
BATLOW#

T58 PAD
SLP_S3# 40
SLP_S4# 40
SLP_S5# 40

R406
1

PM_PWROK 7,40

2 10K_0402_5%
DPRSLPVR 7,51

1 @
C553

4.7P_0402_50V8C

R3
D20

RSMRST#

D22

R_EC_RSMRST#

CK_PWRGD

R5

CK_PWRGD

CLPWROK

R6

M_PWROK

4.7P_0402_50V8C

R_EC_RSMRST#

CH751H-40PT_SOD323-2

0125 Add D90 for RTC timing

PWRBTN_OUT#

PWRBTN#

D90
2

PM_PWROK

ICH_LOW_BAT#

LAN_RST#

PWRBTN_OUT# 40

R_EC_RSMRST#

R413 1
2 100_0402_5%
R795 1
2 10K_0402_5%
CK_PWRGD 15

R_EC_RSMRST# 47

EC_RSMRST# 40

M_PWROK 7,40
+3VS

SLP_M#

B16

CL_CLK0
CL_CLK1

F24
B19

CL_CLK0

CL_DATA0
CL_DATA1

F22
C19

CL_DATA0

CL_VREF0
CL_VREF1

C25
A19

CL_VREF0_ICH
CL_VREF1_ICH

CL_RST0#
CL_RST1#

F21
D18

CL_RST#

A16
C18
C11
C20

XMIT_OFF
GPIO10
GPIO14

MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

10_0402_5%

1 @
C552

M2
B13

SLP_S3#
SLP_S4#
SLP_S5#

@
R396

C16
E16
G17

SLP_S3#
SLP_S4#
SLP_S5#

10_0402_5%

CLK_14M_ICH 15
CLK_48M_ICH 15

SATA
GPIO

SUSCLK

ICH_SUSCLK

CLK_14M_ICH

@
R395

CL_CLK0 7

R420
1

0.1U_0402_16V4Z
1

CL_DATA0 7

C554

2
3.24K_0402_1%

R421
453_0402_1%

+3VALW

CL_RST# 7
R425
1

XMIT_OFF 32
1

C555

2
3.24K_0402_1%

R426

1108 For LAN DSM


LAN_WOL_EN

R796 2

+3VALW

453_0402_1%

0.1U_0402_16V4Z

100K_0402_5%

U58D
ICH_PCIE_WAKE#

WLAN

32
32
32
32

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

C556 1
C557 1

PCIE_RXN1
PCIE_RXP1
2 0.1U_0402_16V4Z PCIE_C_TXN1
2 0.1U_0402_16V4Z PCIE_C_TXP1

N29
N28
P27
P26

PERN1
PERP1
PETN1
PETP1

Robson

35
35
35
35

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

C558 1
C559 1

PCIE_RXN2
PCIE_RXP2
2 0.1U_0402_16V4Z PCIE_C_TXN2
2 0.1U_0402_16V4Z PCIE_C_TXP2

L29
L28
M27
M26

PERN2
PERP2
PETN2
PETP2

TV Tuner

32
32
32
32

PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3

C560 1
C561 1

PCIE_RXN3
PCIE_RXP3
2 0.1U_0402_16V4Z PCIE_C_TXN3
2 0.1U_0402_16V4Z PCIE_C_TXP3

J29
J28
K27
K26

PERN3
PERP3
PETN3
PETP3

31
31
31
31

GLAN_RXN
GLAN_RXP
GLAN_TXN
GLAN_TXP

C564 1
C565 1

2
2

GLAN_RXN
G29
GLAN_RXP
G28
0.1U_0402_16V4Z GLAN_TXN_C H27
0.1U_0402_16V4Z GLAN_TXP_C H26

PERN4
PERP4
PETN4
PETP4

33
33
33
33

PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5

C608 1
C577 1

PCIE_RXN5
PCIE_RXP5
2 0.1U_0402_16V4Z PCIE_C_TXN5
2 0.1U_0402_16V4Z PCIE_C_TXP5

E29
E28
F27
F26

PERN5
PERP5
PETN5
PETP5

32
32
32
32

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

C562 1
C563 1

PCIE_RXN4
PCIE_RXP4
2 0.1U_0402_16V4Z PCIE_C_TXN4
2 0.1U_0402_16V4Z PCIE_C_TXP4

C29
C28
D27
D26

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

D23
D24
F23

SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6

D25
E23

SPI_MOSI
SPI_MISO

ICH_RI#
XDP_DBRESET#
S4_STATE#
ME_EC_CLK1
ME_EC_DATA1
GPIO10
EC_LID_OUT#

1008 no stuff

EC_SMI#

GLAN

GPIO14
EC_SCI#_GPIO12
XMIT_OFF

1394_CR1

New Card

Board ID
+3VS

+3VS

1212 Swap PCIE GLAN and New Card

10K_0402_5%
1

10K_0402_5%

38 BT_OFF
RP31

USB_OC#0
BT_OFF
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

17/14
USB_OC#6
BT_OFF
USB_OC#2
USB_OC#4

@
R775
10K_0402_5%

SPI_CS1#_R

PAD T63
PAD T64

R774

DIS/UMA

PAD T61
PAD T62

26 SPI_CS1#_R

R776

@
R777
10K_0402_5%

4
3
2
1

5
6
7
8

+3VALW

10K_1206_8P4R_5%
RP32

17"
platform-->H

UMA-->L

14"
platform-->L

USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#0

4
3
2
1

USBRBIAS

5
6
7
8

Discrete-->H

R430

WXMIT_OFF#
USB_OC#5
USB_OC#10
USB_OC#11

4
3
2
1

AG2
AG1

V27
V26
U29
U28

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB27
AB26
AA29
AA28

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

T26
T25

CLK_PCIE_ICH#
CLK_PCIE_ICH

AF29
AF28

DMI_IRCOMP

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11

DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP

SPI

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47

USB

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15
R428
1

24.9_0402_1%
2

USB20_N0 38
USB20_P0 38
USB20_N1 38
USB20_P1 38
USB20_N2 38
USB20_P2 38
USB20_N3 42
USB20_P3 42
USB20_N4 17
USB20_P4 17
USB20_N5 32
USB20_P5 32
USB20_N6 38
USB20_P6 38
USB20_N7 38
USB20_P7 38
USB20_N8 32
USB20_P8 32
USB20_N9 32
USB20_P9 32
USB20_N10 38
USB20_P10 38
USB20_N11 38
USB20_P11 38

Within 500 mils


+1.5VS

USB-0 Right side


USB-1 Right side
USB-2 E-SATA & USB Combo
USB-3 Dock
USB-4 USB Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Fingerprint
USB-8 MiniCard(TV)
USB-9 New Card
USB-10 Left Side
USB-11 Touch Screen

Within 500 mils

5
6
7
8

ICH9-M ES_FCBGA676

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10K_1206_8P4R_5%

Rev
G

401540

Date:

USBRBIAS
USBRBIAS#

22.6_0402_1%

10K_1206_8P4R_5%
RP33

1008 add board ID detection

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

CLK_14M_ICH
CLK_48M_ICH

P1

CLK14
CLK48

GPIO19 41

ICH9-M ES_FCBGA676

1212 For WLAN issue

A14
E19

CLKREQ#_C
GPIO38
GPIO39
EXP_CPPE#
GPIO49
GPIO57

15 CLKREQ#_C

SB_SPKR

R410

SMBALERT#/GPIO11

H_STP_PCI#

1
2
PAD T59
100K_0402_5%
OCP#
4 OCP#
CR_CPPE#
33 CR_CPPE#
EC_SCI#
1
2 EC_SCI#_SB
40 EC_SCI#
EC_SMI#
R2094
0_0402_5%
40 EC_SMI#
1
2 EC_SCI#_GPIO12
LAN_DSM#_SB
@R2095
@
R2095
0_0402_5%
31 LAN_DSM#_SB
17/14
GPIO18
1
2
31,40 ISOLATEB
R2085 1K_0402_1% GPIO20
17 GPIO20
CR_WAKE#
33 CR_WAKE#
DIS/UMA

1108 For LAN DSM


1109 Add GPIO22 for card reader wake up event

R409

A17

R412

1102 Add test point


1212 Add R2095 for EC_SCI#

R408

M6

EC_LID_OUT#

VGATE

15,51 VGATE

H1
AF3

SUS_STAT#/LPCPD#
SYS_RESET#

ICH_PCIE_WAKE# E20
SIRQ
M5
THERM_SCI#
AJ23

31,32 ICH_PCIE_WAKE#
40 SIRQ
20,40 THERM_SCI#

GPIO21
GPIO19
GPIO36
GPIO37

clocks

PM_BMBUSY#

CR_CPPE#

GPIO37

R405

RI#

R4
G19

PM_CLKRUN#

1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%

+3VALW

F19

SUS_STAT#
XDP_DBRESET#

AH23
AF19
AE21
AD20

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

R401

ICH_RI#

CLKREQ#_C

SMB

R400

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

R399

+3VS

G16
A13
E17
C17
B18

@ R398
D

THERM_SCI#

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

Direct Media Interface

R397

GPIO39

Place closely pin H1

CLK_48M_ICH

SYS / GPIO

R391
@ R394

1025 change to follow IBT00 design for G-sensor

15,32,35 ICH_SMBCLK
15,32,35 ICH_SMBDATA

PM_CLKRUN#

Place closely pin AF3

U58C

Power MGT

R390

2 2.2K_0402_5%
2 2.2K_0402_5%

MISC
GPIO
Controller Link

R389

R393 1
R392 1

+3VALW

SIRQ

PCI - Express

1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%

1
1

+3VS

68P_0402_50V8J
2

2
2

@ C2130
1

Sheet

Thursday, January 08, 2009


1

28

of

61

+RTCVCC

AE1

C572

10U_0805_10V4Z

C573

2
2.2U_0603_6.3V4Z

D13

CH751H-40_SC76

100_0402_5%

ICH_V5REF_RUN
1

20 mils

C849

CH751H-40_SC76
ICH_V5REF_SUS

20 mils
1

C850
0.1U_0402_10V6K

R435
1
2
CHB1608U301_0603
C588

+1.5VS
C590
1U_0603_10V4Z

1U_0603_10V4Z

VCCSATAPLL

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]

C595
0.1U_0402_16V4Z

T69
T70

C599

2.2U_0603_6.3V4Z

CHB1608U301_0603
2
10U_0805_10V4Z

R436
1
+1.5VS

+1.5VS
1

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2

R437
1

CHB1608U301_0603
C600
C601

VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]

4.7U_0805_10V4Z

1
+3VS
2

AJ5

VCCUSBPLL

AA7
AB6
AB7
AC6
AC7

VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

A10
A11

VCCLAN1_05[1]
VCCLAN1_05[2]

A12
B12

VCCLAN3_3[1]
VCCLAN3_3[2]

B9
F9
G3
G6
J2
J7
K7

VCCHDA

AJ4
AJ3

VCCSUS1_05[1]
VCCSUS1_05[2]

AC8
F17

C574

C576
22U_0805_6.3VAM

+3VS

+3VS
0.1U_0402_16V4Z
1

+VCCP

C581

C582

R778

T65
T66

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

A18
D16
D17
E22

C583

C578

C579

C580

(DMI)

1008 Change power rail for Discrete platform

R1038

F18

C585

AD8 VCCSUS1_5_ICH_1

1
2
0_0603_5%

2 0_0603_5%

1
+3VALW

+3VS

C586

C587
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

T75

VCCSUS1_5_ICH_2

T76

+3VALW

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

10U_0805_10V4Z

0317 change value

VCCSUS1_5[2]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

C575

+VCCP

VCCSUS1_5[1]

AF1

VCCSUS3_3[05]

R432
1
2
CHB1608U301_0603

0.01U_0402_16V7K

AD19
AF20
AG24
AC20

VCCSUSHDA

A27

VCCGLANPLL
80mA

VCCCL1_05
VCCCL1_5

19/78/78mA

23mA

D28
D29
E26
E27

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]

A26

VCCGLAN3_3

1mA

ICH9-M ES_FCBGA676

GLAN POWER

0.1U_0402_16V4Z

+3VS

VCC1_5_A[21]
VCC1_5_A[22]
11mA
11mA

USB CORE

0.1U_0402_16V4Z

VCC1_5_A[20]

AC12
AC13
AC14

+1.5VS
2
C596

VCC1_5_A[18]
VCC1_5_A[19]

AC21
G10
G9

+1.5VS

308mA
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

0.1U_0402_16V4Z

C591
0.1U_0402_16V4Z

C592
0.1U_0402_16V4Z

1342mA
VCC1_5_A[17]

AC18
AC19

212mA

VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

AC9
2

+1.5VS

C597

VCC3_3[01]
VCC3_3[02]
VCC3_3[07]

11mA

ATX

C593

AJ19

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

+1.5VS

AB23
AC23
AG29
AJ6
AC10

ARX

C589

10U_0805_10V4Z

0316 change design

48mA V_CPU_IO[1]
V_CPU_IO[2]

11mA

1U_0603_10V4Z

+1.5VS

C569

0.1U_0402_16V4Z

10_0402_5%

W23
Y23

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

0.1U_0402_16V4Z

R29

2mA

C568

0.1U_0402_16V4Z

D14

VCCDMIPLL
VCC_DMI[2]

23mA VCC_DMI[1]

AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R434

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

0.1U_0402_16V4Z

+5VALW +3VALW

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

4.7U_0603_6.3V6M

0.1U_0402_10V6K

646mA

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
47mA

CORE

C571

2mA

VCCP_CORE

10U_0805_10V4Z
1

V5REF_SUS

AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

1
+ C570

1634mA
2mA

C567

40 mils

V5REF

G3: 6uA

PCI

ICH_V5REF_SUS

VCCRTC

VCCPSUS

1
R433

A6

VCCPUSB

+3VS

A23
ICH_V5REF_RUN

VCCA3GP

+5VS

C566

220U_D2_4VM

R431
1
2
CHB1608U301_0603

+1.5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U58E

U58F

20 mils

+VCCP

G22
G23

+3VALW

VCCCL1_05_ICH

C594
4.7U_0603_6.3V6M

T71

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

19/73/73mA
VCCCL3_3[1]
VCCCL3_3[2]

A24
B24

1 @
C598
1U_0603_10V4Z

+3VS

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

ICH9-M ES_FCBGA676
A

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

29

of

61

HDD Connector
CONN@
JHDD1

0903 change Qty

+5VS

GND
A+
AGND
BB+
GND

0.1U_0402_16V4Z
1

C603

C604

2
2
10U_0805_10V4Z

C605

2
0.1U_0402_16V4Z

Pleace near HD CONN (JP23)


0903 change

+3VS

23
24

GND
GND

0.1U_0402_16V4Z
1 @
C609

1 @
C610

share HDD2

2
2
1000P_0402_50V7K

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1
2
3
4
5
6
7

SATA_TXP0
SATA_TXN0
SATA_RXN0 C602 2
SATA_RXP0 C607 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_TXP0 27
SATA_TXN0 27
SATA_RXN0_C 27
SATA_RXP0_C 27

Near CONN side.


8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

0903 change
+5VS

SUYIN_127072FR022G210ZR_RV
DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA
SUYIN_127043FR022G204ZL_22P_NR

Pleace near HD CONN

2nd HDD Connector-option


CONN@
JHDD2

0903 change Qty

+5VS
C

GND
A+
AGND
BB+
GND

0.1U_0402_16V4Z
1

C613

C614

2
2
10U_0805_10V4Z

C615

2
0.1U_0402_16V4Z

Pleace near HD CONN (JP23)

+3VS

23
24
0.1U_0402_16V4Z
1 @
C619

1 @
C620

GND
GND

10U_0603_6.3V6M

1 @
C621

1 @
C618

2
2
2
2
1000P_0402_50V7K 1U_0603_10V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1
2
3
4
5
6
7

SATA_TXP1
SATA_TXN1
SATA_RXN1 C612 2
SATA_RXP1 C617 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_TXP1 27
SATA_TXN1 27
SATA_RXN1_C 27
SATA_RXP1_C 27

Near CONN side.


8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

0903 change

+5VS

SUYIN_127072FR022G210ZR_RV
DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA
SUYIN_127043FR022G204ZL_22P_NR

Pleace near HD CONN


B

CD-ROM Connector
JODD

+5VS

Placea caps. near ODD CONN.

C625

C626

10U_0805_10V4Z

10U_0805_10V4Z

C624

1U_0603_10V4Z

0.1U_0402_16V4Z

C627

GND
A+
AGND
BB+
GND

1
2
3
4
5
6
7

DP
V5
V5
MD
GND
GND

8
9
10
11
12
13

14
15

GND
GND

SATA_TXP4
SATA_TXN4
SATA_RXN4 C622 2
SATA_RXP4 C623 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_TXP4 27
SATA_TXN4 27
SATA_RXN4_C 27
SATA_RXP4_C 27

Near CONN side.

X76

+5VS

X76

SUYIN_127382FR013G509ZR

ZZZ1

1009 Update to correct CIS


LA-4082P

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

30

of

61

+3V_LAN

1025 add to meet HP request


+AVDD33
+3V_LAN

C650
0.1U_0402_16V4Z

Close to Pin16,37,46,53

+3V_LAN

L74

+3VALW

@
R1106

0_0603_5%
C651

0.1U_0402_16V4Z
2
2
C631
C649

C642

C643

0.1U_0402_16V4Z

2
0_1206_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Close to Pin2 & pin59


D

e
Hk
uo
7
h
.
c
4

2
G

Q106
AP2305GN

+LAN_VDD12
+LAN_VDD12

40 LANPWR#
+3VS

+CTRL_18

Close to Pin1

C630

R2145
10K_0402_5%

22U_0805_6.3VAM

Place Close to Chip

C636

C629

C637

C638

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C639

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C640

C641

0.1U_0402_16V4Z

U18
0.1U_0402_16V4Z
C653 1
PCIE_RXP2_LAN
2

29

HSOP

28 GLAN_RXN

C654 1

PCIE_RXN2_LAN

30

HSON

0.1U_0402_16V4Z

28 GLAN_TXP
28 GLAN_TXN

GLAN_REQ#
2
0_0402_5%

1
R456

15 CLKREQ#_9
15 CLK_PCIE_LAN

7,18,26,32,33,35 PLT_RST#
+CTRL_18
+LAN_VDD12
R2048

+3V_LAN

0_0603_5%

R446 1
R454
1
2
0_0402_5%

28,32 ICH_PCIE_WAKE#
28,40 ISOLATEB

+3VS

HSIN

33

CLKREQB

26

REFCLK_P

27

REFCLK_N

20

PERSTB

SROUT12

FB12

62

LED3
LED2
LED1
LED0

54
55
56
57

LAN_LINK#
LAN_ACTIVITY#

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

3
4
6
7
9
10
12
13

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

ENSR

64

RSET

GLAN_WAKE#

19

LANWAKEB

ISOLATEB

36

ISOLATEB

LAN_X1

60

CKTAL1

LAN_X2

61

CKTAL2

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

21
32
38
43
49
52

EVDD12
EVDD12

22
28

VDD33
VDD33
VDD33
VDD33

16
37
46
53

@
R445

ISOLATEB

65

EXPOSE_PAD

25

EGND

31

R443

EGND

VDDSR

63

AVDD33
AVDD33

2
59

AVDD12
AVDD12
AVDD12
AVDD12

8
11
14
58

IGPIO
OGPIO

50
51

15K_0402_5%

15
17
18
34
35
39
40
41
42

0.1U_0402_16V4Z
2

R453 1

2
3.6K_0402_5%

+3V_LAN

@ U17
4 DO
3 DI
2 SK
1 CS

LAN_DO
LAN_DI
LAN_SK
LAN_CS

GND
NC
NC
VCC

2 @
C652

5
6
7
8

1
0.1U_0402_16V4Z

LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
LAN_MDI0LAN_MDI0+

MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-

24
23
22
21
20
19
18
17
16
15
14
13

NC
NC
NC
NC
NC
NC
NC
NC
NC

+LAN_VDD12

27P_0402_50V8J
2

0.01U_0402_16V7K
0.01U_0402_16V7K

C659

C660

C663

0_0603_5%

C256

L85
0_0603_5%
C634
22U_0805_6.3VAM

0.1U_0402_16V4Z

0125 Reserve to
prevent ESD issue
as other project.

+3V_LAN

RJ45_MIDI0RJ45_MIDI0+

LAN
Conn.
CONN@

JRJ45
C635

1
@ R2074
1
@ R2075
1
R2086

LAN_DSM#

2
0.01U_0402_16V7K

1
1

2
0.01U_0402_16V7K
2
0.01U_0402_16V7K

13

+3V_LAN
LAN_ACTIVITY#

0.1U_0402_16V4Z

+LAN_VDD12

C2107

2
10K_0402_5%
2
0_0402_5%
2
0_0402_5%

R452 2
1LAN_LED_YELLOW14
1 300_0402_5%
8
42 RJ45_MIDI3-

@
C656
68P_0402_50V8K 2

Yellow LED+
SHLD1
PR4DETECT PIN1

PR4+

LAN_DSM#_KBC 40

42 RJ45_MIDI1-

PR2-

LAN_DSM#_SB 28

42 RJ45_MIDI2-

PR3-

42 RJ45_MIDI2+

PR3+

42 RJ45_MIDI1+

PR2+

42 RJ45_MIDI0-

PR1-

42 RJ45_MIDI0+

PR1+

R450
1
2
75_0402_1%
R447
1
2
75_0402_1%
R448
1
2
75_0402_1%
R449
1
2
75_0402_1%

@
C657
68P_0402_50V8K

+3V_LAN
1

LAN_LINK#

11

R451 2
300_0402_5%

1LAN_LED_GREEN 12

Yellow LED-

42 RJ45_MIDI3+

+3VALW

16
9

DETCET PIN2

10

SHLD1

15

Green LED+
Green LEDFOX_JM36113-P1122-7F
LANGND

1
C658
1
2

C661
0.1U_0402_16V4Z

C662
4.7U_0805_10V4Z
A

1000P_1808_3KV7K
C664

0.01U_0402_16V7K
2 0.01U_0402_16V7K

2006/02/13

Issued Date

Place these components


colsed to LAN chip

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

C633

27P_0402_50V8J

+AVDD33

C2105
C2106

D89
@ PACDN042_SOT23~D

2
0.01U_0402_16V7K

RJ45_MIDI1RJ45_MIDI1+

C632

+3V_LAN

RJ45_GND
1

+LAN_EVDD12

LAN_LED_GREEN

RJ45_MIDI2RJ45_MIDI2+

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+LAN_EVDD12

HP PoE solution
1

0.1U_0402_16V4Z

C648

LAN_LED_YELLOW

C1121
RJ45_MIDI3RJ45_MIDI3+

C647

C257

L84

+LAN_VDD12

1LAN_X2

NS692405

C646

+3VALW

Y2

U19
TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-

AT93C46DN-SH-T_SO8

LAN_X1 2

0.1U_0402_16V4Z
2

C645

0.1U_0402_16V4Z

1108 Add LAN DSM function


1
2
3
4
5
6
7
8
9
10
11
12

C644

RTL8111C-GR_QFN64_9X9

LAN_MDI3LAN_MDI3+

25MHZ_20P

2
2.49K_0402_1%

1K_0402_1%
2

HSIP

24

45
47
48
44

C
1
1
1
8
r
o
f
A
m
d
a0
e
0
B3

15 CLK_PCIE_LAN#

23

LAN_DO
LAN_DI
LAN_SK
LAN_CS

EEDO
EEDI/AUX
EESK
EECS

28 GLAN_RXP

CLKREQ#_9

0.1U_0402_16V4Z

L83
1
2
4.7UH_1008HC-472EJFS-A_5%_1008

Sheet

Thursday, January 08, 2009


1

31

of

61

Mini Card 0--WLAN

Mini Card 2---TV tuner

1022 change to follow HP design

1022 change to follow HP design


+1.5VS_WLAN

+3VS_WLAN

+3VALW
+1.5VS_TV

0.01U_0402_16V7K

4.7U_0805_10V4Z

4.7U_0805_10V4Z

C1343

+3VS

C1344

C1345

C676

C677

0.1U_0402_16V4Z

0.01U_0402_16V7K
1

C678

2
2

0.1U_0402_16V4Z
1

0.1U_0402_16V4Z
R2141
10K_0402_5%

C1350

C672

0906 add

4.7U_0805_10V4Z
1

C673

C674

0.1U_0402_16V4Z
1

C679

2
4.7U_0805_10V4Z

C680

0.1U_0402_16V4Z

1226 Add R to +3VALW


+3VALW

+3VS

CONN@
JP13

15 CLK_PCIE_MCARD0#
15 CLK_PCIE_MCARD0

R461
1
1
R463

28 PCIE_RXN1
28 PCIE_RXP1

0_0402_5%
2 PCIE_C_RXN1
2 PCIE_C_RXP1
0_0402_5%
PCIE_TXN1
PCIE_TXP1

28 PCIE_TXN1
28 PCIE_TXP1

+3VS_WLAN

+3VALW

1
2
0_0603_5%
R2115

1
2

XMIT_OFF#
D

D88
1

@
R479
100K_0402_5%
2

@
R478
10K_0402_5%

2
G

CH751H-40PT_SOD323-2

1
2
R481 0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
G3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2
G4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

ICH_PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQ#_6

+1.5VS

1008 add them for debug card

15 CLK_PCIE_MCARD2#
15 CLK_PCIE_MCARD2

+1.5VS_WLAN

PLT_RST#

0125 Change R464 and R1582 to 0805


R464.2 connect to +3VS_WLAN

XMIT_OFF#
PLT_RST#
R464
1
@R1582
@
R1582 1

ICH_SMBCLK
ICH_SMBDATA

15 CLK_DEBUG_PORT0
28 PCIE_RXN3
28 PCIE_RXP3

2 0_0805_5%
2 0_0805_5%
+1.5VS_WLAN

+3VS_WLAN
+3VALW

0_0402_5%
R465 1
2
R467 1
2
0_0402_5%

PCIE_C_RXN3
PCIE_C_RXP3
PCIE_TXN3
PCIE_TXP3

28 PCIE_TXN3
28 PCIE_TXP3

1023 change to follow 14"

+3VS_TV

USB20_N5 28
USB20_P5 28

+3VS

WL_LED# 41

R2142
10K_0402_5%

+1.5VS_WLAN
+3VS_WLAN
CLKREQ#_6

+1.5VS_TV

+3VS

R477 1

2 0_0805_5%

+3VS_TV

@R2119
@
R2119

0_0805_5%

CONN@
JP14
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
G3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2
G4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

DEBUG@
DEBUG@
DEBUG@
DEBUG@
DEBUG@

+3VS_TV
R1577
R1578
R1579
R1580
R1581

+1.5VS_TV
1
2
1
2
1
2
1
2
1
2

PLT_RST#
@ R466
1
R468
1

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
LPC_FRAME# 27,39,40
LPC_AD3 27,39,40
LPC_AD2 27,39,40
LPC_AD1 27,39,40
LPC_AD0 27,39,40

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

0125 R466,R468 change to 0805


2 0_0805_5%
2 0_0805_5%

+3VALW
+3VS
+1.5VS_TV

ICH_SMBCLK
ICH_SMBDATA

USB20_N8 28
USB20_P8 28

1023 change to follow 14"


+1.5VS_TV

+3VS_TV

FOX_AS0B226-S99N-7F_52P

FOX_AS0B226-S99N-7F_52P

0903 update CIS to H5.2mm

@
Q13
2N7002_SOT23

1027 add them for meet Minicard Rev1.1 spec

1224 Delete R470,R471


1212 Move to WLAN

New Card

Near to Express Card slot.

+1.5VS

+3VS_PEC
CONN@
JEXP

U25
+3VS
C686 2

1 0.1U_0402_16V4Z

C687 2
+3VALW

1 0.1U_0402_16V4Z
PLT_RST#

40,41,43,49 SYSON

+3VALW

2
4
17

7,18,26,31,33,35 PLT_RST#

34,40,43,46,48,49,50,52

12
14

SUSP#
@ R485

28 EXP_CPPE#

1.5Vin
1.5Vin
3.3Vin
3.3Vin
AUX_IN
SYSRST#

1.5Vout
1.5Vout
3.3Vout
3.3Vout
AUX_OUT
OC#

SYSON

20

SHDN#

PERST#

SUSP#

STBY#

NC

1 100K_0402_5% 10
EXP_CPPE#

9
18

internal pull high to 3.3Vaux-in


EC need setting at Hi-Z & output Low

CPPE#

GND

11
13

+1.5VS_PEC

3
5

+3VS_PEC

15

+3V_PEC

1023 change to follow 14"


15,28,35 ICH_SMBCLK
15,28,35 ICH_SMBDATA
+1.5VS_PEC
+1.5VS_PEC
28,31 ICH_PCIE_WAKE#
+3V_PEC

19
8

4.7U_0805_10V4Z
3

USB20_N9
USB20_P9
EXP_CPPE#

28 USB20_N9
28 USB20_P9

PERST#

16
7

ICH_SMBCLK
ICH_SMBDATA

PERST#

+3VS_PEC
15 CLKREQ#_4

CPUSB#
+3VS

RCLKEN
S IC TPS2231MRGPR QFN 20P PWR SW

CLKREQ#_4
EXP_CPPE#

15 CLK_PCIE_NCARD#
15 CLK_PCIE_NCARD

1 0.1U_0402_16V4Z

R2143
10K_0402_5%
CLKREQ#_4

28 PCIE_RXN4
28 PCIE_RXP4
28 PCIE_TXN4
28 PCIE_TXP4

C685 2

0906 add debug channel

0903 update CIS to H5.2mm

15 CLKREQ#_6

2 0_0805_5%

1226 Add R to +3VALW

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

2
0_0805_5%
2
0_0805_5%
2
0_0805_5%

R476 1

+3VALW

ICH_PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQ#_10

1
@ R2118
@R2118
1
R458
1
R1564

+1.5VS
C671

+3VS_WLAN

38 CH_DATA
38 CH_CLK
15 CLKREQ#_10

28 XMIT_OFF

follow Mini-CARD SPEC

CLKREQ#_10

+3VALW

0.1U_0402_16V4Z

0.01U_0402_16V7K

+3VS_TV

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

2006/03/10

Deciphered Date

2
0.1U_0402_16V4Z

C688

C689

2
2
0.1U_0402_16V4Z

+3V_PEC
4.7U_0805_10V4Z
1

GND
GND
2

C690

C691

2
0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Secret Data


2006/02/13

C684

4.7U_0805_10V4Z
1

Issued Date

+1.5VS_PEC

SANTA_130801-1_26P

Security Classification

C683

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

32

of

61

Card Reader Connector


CONN@
JREAD

need change to low active switch


+VCC_OUT

Use 0603 type and over 20 mils


trace width on both side

@ C1333

10U_0805_10V4Z
XDCE#

C1331

1102 Install R1553


@
R1543
2

0.1U_0402_16V4Z
C694

3
4

IN
EN

GND

OUT
OUT

1
5
1

R1553
1
2
0_0805_5%

40mil

@
U74

+3VS

+VCC_4IN1

@
C901
2
1

+VCC_4IN1

@ C1334

G5250C2T1U_SOT23-5

@
R1562
150K_0402_5%

0.1U_0805_50V7M

1U_0603_10V4Z

+VCC_OUT

+VCC_4IN1

32
10
9
8
7
6
5
4

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

SDCMD_MSBS_XDWE#
XDWP#_SDWP#
XD_ALE
XD_CD#
XD_RB#
XD_RE#
XDCE#
XD_CLE

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31

7IN1 GND
7IN1 GND

100P_0402_25V8K 100_0402_5%

reserved power circuit

SD-VCC
MS-VCC

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_D4
XD_D5
XD_D6
XD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#

SD-WP-SW

XDWP#_SDWP#

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#

XD-VCC

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_D4
XD_D5
XD_D6
XD_D7

7 IN 1 CONN

+VCC_4IN1

R1544
R1545

41
42

XDWP#_SDWP#
2
10K_0402_5%
XD_RB#
2
10K_0402_5%

1
1

+VCC_4IN1

7IN1 GND
7IN1 GND
TAITW_R015-B10-LM

+1.8VS_CR

1109 Do not install R2030


@ R2030
@R2030
1

0.1U_0402_16V4Z
1
1
C892
C1326

C1327

+1.8VS

0_0805_5%

C893

Strap pin for JMicro


+3VS

1023 JMicro suggest to change


R1546

@ R1548

R1547

U73
15 CLK_PCIE_CR#
15 CLK_PCIE_CR
28 PCIE_TXN5
28 PCIE_TXP5

XD_ALE

28 PCIE_RXN5
28 PCIE_RXP5

1
200K_0402_5%

R114 2

XD_RE#

7,18,26,31,32,35 PLT_RST#

@
C1325
1
2

XIN
XOUT

+3VS
C695
1
2
0.1U_0402_16V4Z

4.7K_0402_5% R1556
1
2 XDCD1#_MSCD#

100_0402_5%

0.1U_0402_16V4Z

28 CR_CPPE#

100P_0402_25V8K
28 CR_WAKE#

@ R2087
1

0_0402_5%
2

D86
1

3
4

APCLKN
APCLKP

9
8

APRXN
APRXP

11
12

APTXN
APTXP

1 8.2K_0402_5% 7

1023 JMicro suggest to change

4.7K_0402_5% R1555
1
2XDCD0#_SDCD#

SDCLK

2 0.1U_0402_16V7K PCIE_RXN5_C
2 0.1U_0402_16V7K PCIE_RXP5_C

C693 1
C697 1

+3VS

@
R1541
1

XDCD1#_MSCD#
XDCD0#_SDCD#

38
39

APVDD
APV18

5
10

DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
XDWP#_SDWP#
XD_CLE
XD_D4
XD_D5
XD_D6
XD_D7
XD_RE#
XD_RB#
XD_ALE

TPA1P
TPBIAS_1
TREXT

34
35
36

TPA1+
TPBIAS1
TREXT

APREXT
TXIN
TXOUT

30

TAV33

1
2

XRSTN
XTEST

JMB380

13
14

SEEDAT
SEECLK

15
16

CR1_CD1N
CR1_CD0N

CH751H-40PT_SOD323-2

MSCLK

@
R1542
1

1109 Add D86 for card reader wake up


0125 Do not install
R2087 for Intel platform

@
C900
1
2

100_0402_5%

2
1000P_0402_50V7K

2
0.1U_0402_16V4Z

17

+VCC_OUT

use for PWR_EN#


CR_LED#

21

8mA sink current

APGND

TCPS
TPB1N
TPB1P
TPA1N

24
31
32
33

GND

49

CR1_PCTLN
CR1_LEDN

100P_0402_25V8K

C1328

XDCD1#_MSCD#
XDCD0#_SDCD#

C692

XD_CD#

1
3
1

DAN202U_SC70

0.1U_0402_16V4Z

R1554
1

2
0.1U_0402_16V4Z

D46

+3VS

XD_ALE

1
10K_0402_5%

XD_CLE

1
10K_0402_5%
1
10K_0402_5%

1212 Change XD_ALE to +3VS


0125 Add R2123
R2123

2
10U_0805_10V4Z

Power Circuit

C1329

C696
270P_0402_50V7K

+1.8VS_CR

C1330

0.1U_0402_16V4Z

SDCLK_MSCLK_XDCE#

R1550
R1551
R1552

2 22_0402_5%
2 22_0402_5%
2 22_0402_5%

1
1
1

SDCLK
MSCLK
XDCE#

2
12K_0402_1%
3

TPB1TPB1+
TPA1-

JMB380-QGAZ0A_QFN48_7X7

White LED: VF=3V, IF = 5mA, Res = 56ohm


CONN@
J1394A

1009 lower LED power consumption

+5VS

R1557
470_0402_5%

C899 1

2 220P_0402_50V8K

R1558 1

2
4.99K_0402_1%

TPBIAS1
1

22P_0402_50V8J

1 1

@ Q53
2N7002_SOT23-3

2 56_0402_5%
2 56_0402_5%

R1561
R290

1
1

2 56_0402_5%
2 56_0402_5%

1
2
3
4

TPBTPB+ GND
TPA- GND
TPA+

5
6

C1332
0.33U_0603_16V4Z

2
G

CR_LED#

For JM380

@
R2097
4.7K_0402_5%

2006/02/13

Issued Date

1212 Change to high active control


0125 Add R2124

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Compal Electronics, Inc.

Compal Secret Data

Security Classification

TPB1TPB1+
TPA1TPA1+

0_0402_5%

XOUT

R2124

1
2

C898
2
1

D47
HT-F196BP5_WHITE

R134
1M_0402_5%

X2
4

XIN

22P_0402_50V8J

1
1

SUYIN_020115FB004SX00ZL

24.576MHz_16P_3XG-24576-43E1
C897
2
1

R1560
R1559

Sheet

Thursday, January 08, 2009


E

33

of

61

1008 Change to +3V

C904

0.1U_0402_16V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

+3VS

0212_Change to +5VALW.

+3VAMP_CODEC

C725

0.1U_0402_16V4Z

+3VDD_CODEC
R885
1
2
BLM18BD601SN1D_0603

C727

C730

R886
1
1

+5VALW

W=40Mil

+VDDA_CODEC

0_1206_5%

C722

C731

+VDDA_CODEC
U28

2
0.1U_0402_16V4Z

32,40,43,46,48,49,50,52

(4.75V)
300mA

CODEC POWER

1019 Change Size to 1206 for IDT request

+3VS
R867
1
2
BLM18BD601SN1D_0603

1U_0603_10V4Z

+3VS_HDA

SUSP#

IN

GND

SHDN

OUT

BYP

G9191-475T1U_SOT23-5

C723
2.2U_0805_16V4Z
1

C732

0208_Change SLP_S3# to SUSP#.


2

0.1U_0402_16V4Z

U56
DVDD_CORE*

DVDD_CORE

25

AVDD1*

38

AVDD2**

32
HDA_BITCLK_CODEC

27 HDA_BITCLK_CODEC
27 HDA_SDOUT_CODEC
27 HDA_SDIN0

1106 Add EC_BEEP

27 HDA_SYNC_CODEC

27,40 HDA_RST#_CODEC
40 EC_BEEP

R2076
1

47K_0402_5%
2
17 DMIC_CLK

R520
28 SB_SPKR

2 47K_0402_5%

R521 1
C956

2 10K_0402_5%
1

31

MONO_OUT

GPIO 6

44

SPDIF OUT1 / GPIO 7

45

SPDIF_OUT_DOCK

SPDIF OUT0

48

SPDIF_OUT

VREFOUT-B

28

VREFOUT_B

VREFOUT-C

29

SDO

SDI_CODEC

HDA_SYNC_CODEC

10

HDA_RST#_CODEC

11

RESET#

46

DMIC_CLK

C955 1

1 1U_0603_10V4Z

MONO_INR
2
0.1U_0402_16V4Z

30

43

BITCLK

SYNC

R531 1
R916 1

2 5.1K_0402_1%
2 39.2K_0402_1%
C979
0.1U_0402_16V4Z

C744 1

SENSEB#

VC_REFA
2
10U_0805_10V4Z

SPDIF_OUT_DOCK 42
SPDIF_OUT 19

VREFOUT_B 36

13

SENSE
HP_OUTR

CAP2

PORTA_R

41

12

PCBEEP

PORTA_L

39

HP_OUTL

PORTB_R

22

MIC_EXT_R

PORTB_L

21

MIC_EXT_L

40

NC / OTP

34

SENSE_B / NC

37

NC

PORTC_R

24

MIC_IN_R

18

NC

PORTC_L

23

MIC_IN_L

19

NC
PORTD_R

36

LINE_OUT_R

20

NC
PORTD_L

35

LINE_OUT_L

R523
R526
R524
C951
@ R1599

1
2 5.1K_0402_1%
1
2 20K_0402_1%
1
2 39.2K_0402_1%
0.1U_0402_16V4Z
1
2
1
2 10K_0402_1%
HP_OUTR 36

MIC_EXT_R 36

Jack MIC

MIC_IN_R 36

Internal MIC

MIC_IN_L 36
LINE_OUT_R 36,37

Internal SPKR.

LINE_OUT_L 36,37

27

VREFFILT

PORTE_R

15

DOCK_MIC_R_CODEC

C2108

1 1U_0603_10V4Z

R2080

2 10K_0402_5%

DOCK_MIC_R 42

26

AVSS1*

PORTE_L

14

DOCK_MIC_L_CODEC

C2109

1 1U_0603_10V4Z

R2081

2 10K_0402_5%

DOCK_MIC_L 42

42

AVSS2**

DVSS**

PORTF_R

17

PORTF_L

16

R1573
1.21K_0402_1%

SENSE B

Port

Resistor

Port

Resistor

39.2K

39.2K

20K

20K

10K

10K

5.11K

5.11K

1107 HP request

2
1000P_0402_50V7K
C747
2
1000P_0402_50V7K
HDA_BITCLK_CODEC

C748
2
1000P_0402_50V7K
C749

R528
1

@
R525
47_0402_5%

2
1000P_0402_50V7K

R527
1

GND

R1574
1.21K_0402_1%

C746

@R2068
@
R2068
1

DOCK MIC

1/Av circuit

SENSE A

1023 change detection circuit to solve Speaker


can not work.

@
1

1107 Delete R515,R516,C916

INTMIC_DET# 36

MIC_EXT_L 36

92HD71B7X5NLGXA1X8_QFN48_7X7

EXTMIC_DET# 36
JACK_DET# 36,42

HP Jack & Dock

1106 Change C746,C747,C748,C749 to 1000PF


1

HP_OUTL 36

EAPD_CODEC_R 37

+3VAMP_CODEC

33

EAPD_CODEC_R

SENSE_A

2 0.1U_0402_16V4Z

+3VAMP_CODEC
42 SENSE_B#

EAPD_CODEC 40
DMIC_DAT 17

GPIO 5

C913

DVDD_IO

R517 1

L88
R1528
FBMA-L10-160808-301LMT_0603 22_0402_5%
2
1
1
2

VOL_DN/DMIC_1/GPIO 2

VREFOUT-E / GPIO 4

HDA_SDOUT_CODEC
2 33_0402_5%

R2060
1
0_0402_5%

0125 Add L for EMI

47

VOL_UP/DMIC_0/GPIO 1

GPIO 3

+3VS_HDA

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

+3VAMP_CODEC

+3VDD_CODEC

1 @
C745

2
0_0402_5%

33P_0402_50V8K
4

2
0_1206_5%

2
0_1206_5%

GNDA

GNDA 36,37,42

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

34

of

61

MDC 1.5 Conn.


Change type 4/25
CONN@
JP18

27 HDA_SYNC_MDC
27 HDA_SDIN1
27 HDA_RST#_MDC

1
3
5
7
9
11

HDA_SDOUT_MDC

27 HDA_SDOUT_MDC

HDA_SYNC_MDC
2 HDA_SDIN1_MDC
33_0402_5%

R529 1

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

13
14
15
16
17
18

+3VS

C752

4.7U_0805_10V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

C753

Mini Card 1---Robson

R803 1

2
4
6
8
10
12

1 @
C754

2 0_0603_5%

+3VS
D

+3VS
HDA_BITCLK_MDC 27
@ R530
2

GND
GND
GND
GND
GND
GND

ACES_88018-124G

@ C751
1
2

10_0402_5%

10P_0402_25V8K

Connector for MDC Rev1.5

+3VS_MINI

+1.5VS_MINI

+3VALW

0.01U_0402_16V7K 4.7U_0805_10V4Z
1
+3VS

C759

C760

C761

C755

C756

C757

CLKREQ#_11

0.1U_0402_16V4Z

+1.5VS_MINI

+3VALW
@ R2120
1
2
0_0805_5%

+3VS_MINI

CONN@
JP19

CLKREQ#_11

15 CLKREQ#_11
15 CLK_PCIE_MCARD1#
15 CLK_PCIE_MCARD1

28 PCIE_RXN2
28 PCIE_RXP2

R533
1
1
R534

0_0402_5%
2 PCIE_RX2N_R
2 PCIE_RX2P_R
0_0402_5%

28 PCIE_TXN2
28 PCIE_TXP2
+3VS_MINI

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2
GND1

54
56

1226 Add R to +3VALW

0.1U_0402_16V4Z

R2144
10K_0402_5%

1 @
C758

0.01U_0402_16V7K4.7U_0805_10V4Z

0.1U_0402_16V7K

+3VS

R1565
1
2
0_0805_5%
+1.5VS
R1566
1
2
0_0805_5%

0903 change from L to R


PLT_RST#
R469 1
@ R1583 1

0906 Add
2 0_0805_5%
2 0_0805_5%

PLT_RST# 7,18,26,31,32,33
+3VS_MINI
+3VALW

ICH_SMBCLK 15,28,32
ICH_SMBDATA 15,28,32

0125 R469,R1583 change to 0805

0903 update CIS to H5.2mm

FOX_AS0B226-S99N-7F~D

SP01000P700 S H-CONN ACES 88914-5204 52P P0.8

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

35

of

61

+5VS

1
10U_0805_10V4Z

37,40 EC_MUTE#

@
R904
4.7K_0402_5%

C2101
10U_0805_10V4Z

RS/D

RVDD

LS/D

LVDD

R1530

C772 1

2 0.1U_0402_16V7K

R946

C773 1

2 0.1U_0402_16V7K

R1531

C1324 1

34,37 LINE_OUT_L

2 0.1U_0402_16V7K

R947

1
2
7.5K_0402_1%
1
2
7.5K_0402_1%

16

RIN+

ROUT+

SPKR+

17

RIN-

ROUT-

SPKR-

1
2
7.5K_0402_1%
1
2
7.5K_0402_1%

12

LIN+

LOUT+

SPKL+

1224 Change value

@ C775

1212 Change to 1uF

1U_0805_25V6K

PV2 No install C765,C775

1
@C765
@
C765

13

LIN-

15

RBYPASS

11

LBYPASS

LOUT-

MIC INT In-L

20

NC

18

GND

NC

10

GND

NC

22U_0805_6.3VAM
@

5
6

C971

34 MIC_IN_R

SPKL-

NC

@
R900
0_0603_5%

INT_MIC_DET#
MICIN_L
MICIN_R

1
2
3
4

34 MIC_IN_L

CONN@
JP21

C970

34,37 LINE_OUT_R

2 0.1U_0402_16V7K

@
R905
4.7K_0402_5%

19

C770 1

2
1U_0603_10V4Z

1
2
3
4

GND1
GND2
ACES_88231-04001

22U_0805_6.3VAM

1108 Change C970,C971 to 22uF

+VDDA_CODEC

0906 Change pin define


TPA6020A2RGWR_QFN20_5x5

Audio & USB board conn

+3VS

@
R1597

14
2 0_0402_5%

@ C972 1

U30
R542 1

C2102

0_0402_5%
2
1

3/28 from
NC7SZ04P5X_SC70-5
change to 2N7002

@ R906
1

+VDDA_CODEC

2
0_1206_5%

R535
1

0906 Change

+5VAMP

2
10K_0402_5%

1U_0805_25V6K

6
34 INTMIC_DET#
3

HP_OUT_R
HP_OUT_L
EXTMIC_DET# 34

@ Q108B
EXTMIC_DET#
HP_DET#

2N7002DW-7-F_SOT363-6

INT_MIC_DET#
2
@
Q108A
2N7002DW-7-F_SOT363-6

40 ANA_MIC_DET

EXT_MIC_R
EXT_MIC_L

@
R1596
10K_0402_5%

CONN@
JP48
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14

Keep 10 mil
width

CIR_IN

CIR_IN 40,42

+5VL

1023 change to n channel FET to solve Speaker can


not work.

ACES_87213-1400G

SP02000D000 S W-CONN ACES 85204-04001 4P P1.25

SPEAKER
JP20
SPKL+
SPKLSPKR+
SPKR-

B+

1
2
3
4

1023 add R1012 to solve Speaker can


not work

1
2
3
4

34,42 JACK_DET#

R1011
330K_0402_5%

+3VALW
1
3

C958

C959

5
6

C960

GND1
GND2
3

ACES_88231-04001
CONN@

1108 Add 0.01uF


180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J

Q145B
2N7002DW-7-F_SOT363-6
5

0125 Add 180pF for ESD

C2112
0.01U_0402_16V7K

2
4

6 1

Q202
2N7002_SOT23-3

2
G
R1007
10K_0402_5%

R1012
10K_0402_5%

C957
180P_0402_50V8J

C2103
150U_Y_6.3VM

C2104
150U_Y_6.3VM

C1346
150U_Y_6.3VM

C1347
150U_Y_6.3VM

40.2_0603_1%
2

HP_OUT_R
HP_OUT_L

1U_0603_10V4Z
R1588
4.7K_0402_5%

DOCK_LOUT_R 42

R1589
4.7K_0402_5%

HP OUT For Docking

5
Q203B
2N7002DW-7-F_SOT363-6

R2083
1

C1358
1
2

2
0_0402_5%
1

40.2_0603_1%
2

R2082
1

R1587

2
3

34 HP_OUTL

34 HP_OUTR

34 VREFOUT_B

1107 Add R2082,R2083

Q147A
2N7002DW-7-F_SOT363-6

Q147B
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
Q145A

HP_DET#

DOCK_LOUT_L 42

Q203A
2N7002DW-7-F_SOT363-6

C1359
C1360

34 MIC_EXT_R
34 MIC_EXT_L

1U_0603_10V6K
1
2 EXT_MIC_R
1
2 EXT_MIC_L
1U_0603_10V6K

HP OUT For M/B

0125 Change to 150uF for Frequency Response (Band-Edge)

MV-1 Add dual type for headphone

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

36

of

61

@
R917

2 0_0603_5%

1107 Change C980,C984 from 5900p to 0.039u


1107 Change C983,C992 from 1000p to 100p

1107 Change C982 from 5900p to 0.039u


0125 Change C982 from 0.039u to 5900pF

C980
1

0.027uF_0603_16V
2

+VDDA_CODEC

C981
1
2

+VREF

OUT

+VDDA_CODEC

+VREF

+VREF

1224 C987 change from 0.47u to 0.056uF


Change C984, C980, C993, C990 to 0.027uF

U35C
10

OUT

+VREF

0.027uF_0603_16V

R931 1

R929
1
2
60.4K_0402_1%

D81
2

1
R934
1K_0402_5%

D82
2

@
R935
0_0402_5%

2 0_0402_5%
2 0_0402_5%
2 8.2K_0402_5%

1
1
1

1U_0805_25V4Z

INN

INP

VCC
VREF
BYPASS

GAIN0

GAIN1

SHUTDOWN

VCLAMP

C1011
1U_0603_16V4Z
R941
R942

1
2
51_0402_5%
1
2
51_0402_5%

PV2 Change C1014,C1015 to 25V

C1015
0.22U_0603_25V

B+

24
23
22

C1003
C1004

1U_0603_10V4Z
1
2
1

4.7U_0805_25V6K

1
2

BSN

COSC
ROSC

21
20

PVCC
PVCC

16
9

OUTP
OUTP

14
15

OUTN
OUTN

10
11

17

C1008

C1017

C1009
2

220P_0402_50V7K
C1010 1
2

@
R936
0_0603_5%
3

C1016
4.7U_0805_25V6K

1
1U_0805_25V4Z

1U_0805_25V4Z

R939 1
2
120K_0402_5%

1113 Remove L58,L60 for layout spacing


PV2 C1012,C1013 no install,L57 and L59 change to 0 ohm
MV-1 Add L57,L59,C1012,C1013
L57
L59

BSP

1
2
BLM31AJ260SN1L_1206~D
1
2
BLM31AJ260SN1L_1206~D

1
2
1

BAT54AW_SOT323-3~D

18
19

PGND
PGND
PGND

AGND
AGND

6
12
13

C1012

3
4

C1013

1
2
GND
GND
ACES_88231-02001

4700P_0402_25V7K
2

D38

Sub-woofer Connector
CONN@
JP49

2 0.1U_0402_10V6K

1107 Change C1008,C1009 to 1UF and no install R936

1U_0805_25V4Z

4700P_0402_25V7K
C1014
0.22U_0603_25V

2 0.1U_0402_10V6K

@ C1000 1

C1007

+V_WOOFER

U60

C1006

2.2U_0603_106K
R937 1
2
0_0402_5%
@ R938 1
2
0_0402_5%

2 0.1U_0402_10V6K

@ C999 1

+V_WOOFER

RLS4148_LL34-2

+V_WOOFER

2
0.47U_0603_10V7K
2
0.47U_0603_10V7K

2 0.1U_0402_10V6K

@ C998 1

2
4.7U_0805_25V6-K

C1005

RLS4148_LL34-2

C1002

2 0.1U_0402_10V6K

@ C997 1

1009 change Subwoofer power circuit

+VDDA_CODEC

BASS_OUT

@ C994 1

C996

B+

@ R2084
R2061
R2063

2 0_0805_5%

C1001

1107 Add pull down for Sub-Woofer


shutdown and EC_MUTE#
PV2 Change C1002,C1005 to X7R

TLV2464_TSSOP14

TLV2464_TSSOP14

C995

BASS_OUT

14

OUT

4.7U_0603_6.3V4Z~D

0.1U_0402_10V6K

1
2

R932
10K_0603_5%

36,40 EC_MUTE#
34 EAPD_CODEC_R

R926
1

10K_0603_5%

1U_0603_10V4Z

R928
10K_0402_1%

R930
1

13

10K_0402_1%

2
+VDDA_CODEC

U35D
12

0.027uF_0603_16V

C992
100P_0402_50V8J
C993
1
2

R927
1
2
30.1K_0402_1%

C988
1
2

+VREF

TLV2464_TSSOP14

C990
1
2

+VREF

+VDDA_CODEC

0.056uF_0603_16V

11

C991

4
OUT

C987
1
2

U35A
3

R925
1
2
20K_0402_1%

C985
R924
1
2
60.4K_0402_1%

11

34,36 LINE_OUT_L

C989
1
2
1U_0603_10V4Z

100P_0402_50V8J

34,36 LINE_OUT_R

R923
1
2
20K_0402_1%

+VDDA_CODEC

TLV2464_TSSOP14

R922
10K_0402_1%
C986
1
2
1U_0603_10V4Z

10K_0402_1%

10K_0402_1%

11

0.027uF_0603_16V
2

100P_0402_50V8J

10K_0402_1%

C984
1

R918
1

R919
1

R920
1
2
30.1K_0402_1%

U35B

11

R921
1

C983
100P_0402_50V8J

5600P_0402_25V7K
C982 5600P_0402_25V7K
1
2

2
HPA00304PWR_TSSOP24

1108 Change to dual package

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

Issued Date

Need check

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

37

of

61

Left side USB Connector

Left side

ESATA/USB combination Connector

+5VALW

USB_VCCC
USB_VCCC
U32

TPS2061IDGNR_MSOP8
2

4.7U_0805_10V4Z

1
+ C786
2

C788

USB_EN#

1000P_0402_50V7K

OUT
OUT
OUT
OC#

0.1U_0402_16V4Z

C787

GND
IN
IN
EN#

CONN@
JP27

W=60mils

8
7
6
5

150U_D_6.3VM

1
2
3
4

28 USB20_N10
28 USB20_P10

C789

1023 change to follow 14"

1
2
3
4

VCC
DD+
GND

5
6
7
8

GND
GND
GND
GND

CONN@
JP25

1023 change to follow 14"

1
2
3
4

28 USB20_N2
28 USB20_P2

5
6
7
8
9
10
11

SATA_TXP5
SATA_TXN5

27 SATA_TXP5
27 SATA_TXN5
C784
C785

27 SATA_RXN5_C
27 SATA_RXP5_C

1 0.01U_0402_16V7K SATA_RXN5
1 0.01U_0402_16V7K SATA_RXP5

2
2

B_VCC
B_DB_D+
B_GND

SUYIN_020173MR004M598ZL

GND
A+
AGND
BB+
GND

USB

ESATA
SHIELD
SHIELD
SHIELD
SHIELD

12
13
14
15

TYCO_1759576-1
R561

2 10K_0402_5%

@
D22

+5VALW
+5VALW
USB20_N10

VIN

IO1

IO2 GND

USB20_P10

@D15
@
D15
4 VIN

+5VALW
SATA_TXN5

PRTR5V0U2X_SOT143-4

IO1

IO2 GND

SATA_TXP5

PRTR5V0U2X_SOT143-4

1023 change to follow 14"

@D84
@
D84
4 VIN

+5VALW
SATA_RXN5

SATA_RXP5

IO1

USB20_N2

IO2 GND

@ D85
4 VIN

+5VALW

PRTR5V0U2X_SOT143-4

USB cable connector for Right side

Touch screen connector

CONN@
JP43
1
2
3
4
5
6
7
8
9
10

+5VALW
USB_EN#
28 USB20_N0
28 USB20_P0
28 USB20_N1
28 USB20_P1

1
2
3
4
5
6
7
8
9
10

USB20_P2

1020 change to meet correct power rail


CONN@
JP26
1
2
3
4
5
6
7

28 USB20_N11
28 USB20_P11

1023 change to follow 14"

1
2
3
4
5
GND1
GND2

5P connector

ACES_88266-05001
G11
G12

+5VS

@ D18
@D18
4 VIN

USB20_N11

1023 change to follow 14"

11
12

ACES_87213-1000G

1023 change to follow 14"

PRTR5V0U2X_SOT143-4

+5VS
C

IO1

IO2 GND

IO1

IO2 GND

USB20_P11

PRTR5V0U2X_SOT143-4

BT Connector

Finger printer

0125 Change BT connector from 88231-0800 to 87213-0800(SP02000CZ00)


ACES_87213-0800G

1212 Add soft start circuit

10

20070209 Add for FPR


@ R698

2 0_0603_5%

+3VS

@ Q34

SI2301BDS_SOT23

28 USB20_N7
28 USB20_P7

2 0_0402_5%
2 0_0402_5%

@ D25
4 VIN

+5VALW
USB20_N6_R

1
2
3
4
5
6
7
8

USB20_N7_R
USB20_P7_R

USB20_N7

1212 BT issue, change circuit

1
2
3
4
5
6
GND
GND

+3VALW

R2112
1

2
1

USB20_P6_R

PRTR5V0U2X_SOT143-4

+3VAUX_BT

0_0603_5%
2

Q24

1
2
@ R572 0_0603_5%

C790
1U_0603_10V4Z

1107 Change FPR pin assignment

IO1

IO2 GND

+3VS

SI2301BDS_SOT23

ACES_85201-06051

PRTR5V0U2X_SOT143-4

IO2 GND

1K_0402_5%
1K_0402_5%

2
2

USB20_P6 28
USB20_N6 28
BT_LED 41
CH_DATA 32
CH_CLK 32

0612 no install

@ R569 1
@R569
@R570
@
R570 1

1 0_0402_5%
1 0_0402_5%

2
2

USB20_P7

IO1

R567
R568

0.1U_0402_16V4Z

1023 change to follow 14"


@ D33
4 VIN

+3VAUX_BT
USB20_P6_R
USB20_N6_R

CONN@ JP30

C835

CONN@
JP41
R654 1
R655 1

+5VALW

2
0_0603_5%

8
7
6
5
4
3
2
1

40 USB_EN#

@C2121
@
C2121
0.1U_0402_16V4Z
@ R2113
47K_0402_5%
1
2

R653
1

+3VALW

GND 8
7
6
5
4
3
2
GND 1

1
C794

R2114
100K_0402_5%

C791
0.01U_0402_16V7K

C792
0.1U_0402_16V4Z

C793
4.7U_0805_10V4Z

1
2

0.1U_0402_16V4Z

MV1 Delete R582 for ESD issue


A

28 BT_OFF

2
10K_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

Issued Date

1
R574

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

38

of

61

LPC Debug
Port

1113 EC request
+3VL

+3VALW

1008 Change power rail

SPI ROM

@ R2091
0_0402_5%

@R2092
0_0402_5%

20mils

VCC

HOLD

SPI_FSEL#

SPI_CLK_R

SPI_FWR#

C796

0.1U_0402_16V4Z
2
1

1
@
U34

2
8
7
6
5

40,41,45 SMB_EC_CK1
40,41,45 SMB_EC_DA1

@
R575
100K_0402_5%

40 FSEL#

R576 1

40 SPI_CLK

R577 1

40 FWR#

R578 1

2
0_0402_5%
2
0_0402_5%
2
0_0402_5%

@ C795

VCC
WP
SCL
SDA

A0
A1
A2
GND

Removed +3VS. 6/13

U33
1

0.1U_0402_16V4Z

Change from +3VL to +3VS. 6/9

+3VL

VSS

4
B+
CONN@
JP32
15 CLK_DEBUG_PORT1

SPI_SO
1
R579

FRD#
2
0_0402_5%

27,32,40 LPC_FRAME#
FRD# 40
26,40 PCI_RST#

WIESON G6179 8P SPI

1
2
3
4

SP07000F500 S SOCKET WIESON G6179-100000 8P


SPIFLASH
WIESO_G6179-100000_8P

SPI_CLK_R
C798

27,32,40
27,32,40
27,32,40
27,32,40

AT24C16AN-10SI-2.7_SO8

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
ON/OFFBTNLED#

@
R580
100K_0402_5%

Connect pin3 & 23


together and pin 24
to GND in 6/29.

10P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

VCC1PWRGD
SPI_CLK_JP52
SPI_CS#_JP52
SPI_SI_JP52
SPI_SO_JP52
SPI_HOLD#_0

Ground
LPC_PCI_CLK
Ground
LPC_FRAME#
+V3S
LPC_RESET#
+V3S
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
VCC_3VA
PWR_LED#
CAPS_LED#
NUM_LED#
VCC1_PWRGD
SPI_CLK
SPI_CS#
SPI_SI
SPI_SO
SPI_HOLD#
Reserved
Reserved
Reserved
ACES_87216-2404_24P

0125 No-stuff

Acceleromter-1

+3VALW

R889 1
+3VS

+3VS_ACL

+3VS_ACL_IO

SPI_CLK

1
@ R584

2
0_0402_5%

SPI_CLK_JP52

FSEL#

1
@ R586

2
0_0402_5%

SPI_CS#_JP52

FWR#

1
@ R587

2
0_0402_5%

SPI_SI_JP52

1
@ R588

2
0_0402_5%

SPI_HOLD#_0

HOLD#
2
3.3K_0402_5%
FRD#

D45
2

R1535
1

2
0_0603_5%

40,41 ON/OFFBTN_LED#

1
@ R590

2
0_0402_5%

SPI_SO_JP52

ON/OFFBTN_LED#
1
@ R591

2
0_0402_5%

ON/OFFBTNLED#

VCC1_PWRGD

2
0_0402_5%

VCC1PWRGD

CH751H-40PT_SOD323-2

26 PCI_PIRQH#
B

R1538

+3VS_ACL

1
6

VDD_IO
VDD

8
9

INT 1
INT 2

12
13
14

13,14,15 CLK_SMBDATA
13,14,15 CLK_SMBCLK

1
@ R592

U72

LIS302DL
+3VS_ACL_IO
+3VS_ACL

40 VCC1_PWRGD

+3VS_ACL

0125 Swap +3VS_ACL and +3VS_ACL_IO


Change SM BUS to CLK SM BUS

7
1
10K_0402_5%

GND
GND
GND
GND

1
2
4
5
10

0.1U_0402_16V4Z

C1321

C1322
10U_0805_6.3V6M

SDO
SDA / SDI / SDO
SCL / SPC
RSVD
CS
RSVD

R1539
1

3
11

2
0_0603_5%

+3VS_ACL_IO

LIS302DLTR_LGA14_3X5~D

Must be placed in the center of the system.

U72 & U77 must be close

Acceleromter-2

need to update CIS

@
U77

BMA150

+3VS_ACL
A

@ 10K_0402_5%
R2052 1

CLK_SMBCLK

CLK_SMBDATA

VDDIO
VDD

9
2

PCI_PIRQH#

INT

G_CS#

CSB

GND

SCK

1
10

RSVD
RSVD

SDO
RSVD
RSVD

11
12

SDI

BMA150_LGA12

+3VS_ACL_IO
+3VS_ACL

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2006/03/10

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

39

of

61

MV-1 Remove C2129


+3VL_EC

0125 Add C on +3VL

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C809
C810
C811
C812
2
2
0.1U_0402_16V4Z

2
2
1000P_0402_50V7K

+3VL
C813

+3VL

+3VL_EC

+EC_AVCC

@
+ C2129
22U_A_4VM

1000P_0402_50V7K
R603
1

2 0_0805_5%

2
2
2
2

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%

1025 Add Pull


up for GPI

20080812 Add R2148 for 2F issue


GATEA20
KB_RST#
SIRQ

27 GATEA20
27 KB_RST#
28 SIRQ

@
C815
1

R2148
1
27,32,39 LPC_FRAME#
27,32,39 LPC_AD3
2
27,32,39 LPC_AD2
33_0402_5%
27,32,39 LPC_AD1
27,32,39 LPC_AD0

@
R609
1

15P_0402_50V8J
15 CLK_PCI_EC
+3VL

R610 1

26,39 PCI_RST#

2
47K_0402_5%

28 EC_SCI#

1
0.1U_0402_16V4Z

27,34 HDA_RST#_CODEC
C817

0205_Add Pull
down R402 for
SUSP#.

10_0402_5%
SIRQ_KBC
2
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
PCI_RST#
ECRST#
EC_SCI#
1
2
R2067
0_0402_5%

1102 Change HAD_RST#_CODEC


from KBC pin 36 to pin 38

J1
JOPEN

1105 Add resistor

1102 Change R615 to 8.2k ohm add pull down on SYSON


SUSP#

+3VL
PCI_RST#
1

MV-1 Chnage power


rail to +3VL

8.2K_0402_5%
R615

R619
100K_0402_5%

0214_Add Pull high


resistor for LID_SW# and
WL_BTN#.

LID_SW#

SYSON

R618
10K_0402_5%

1114 R620 no stuff, SB internal pull up


1212 Change power rail to +3VALW
MV1 Change power rail to +3VL

8.2K_0402_5%
R2062

39,41,45
39,41,45
4,20
4,20

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

12
13
37
20
38

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

INV_PWM
FAN_PWM
EC_BEEP
ACOFF

63
64
65
66
75
76

BATT_TEMP
BATT_OVP
ADP_I
ADP_ID
TP_BTN#
ANA_MIC_DET

PWM Output
AD

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

INV_PWM 17
FAN_PWM 4
EC_BEEP 34
ACOFF 46

68
70
71
72

DAC_BRIG
VCTRL
IREF
AC_SET

@ R624
1

2
0_0402_5%

EC_PME#

+3VL
1

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#
USB_EN#
I2C_INT
MUTE_LED_KBC
1
TP_CLK
R2121
TP_DATA
@ R2077 0_0402_5%
1
2

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT
EC_PME#
EC_THERM
CONA#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

R630
4.7K_0402_5%

42 CONA#

UTX
LANPWR#_R
ON/OFF

1106 Change LANPWR to KBC pin31

PS2 Interface

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

DOCK_VOL_UP#
DOCK_VOL_DWN#

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

FRD#
FWR#
SPI_CLK
FSEL#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

CIR_IN
VCC1_PWRGD
FSTCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
AC_IN

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

SLP_S4#
ENABLT

V18R

124

SPI Flash ROM

GPIO
SM Bus

NC

C584

+3VL_EC

15P_0402_50V8J
+EC_AVCC

Y4
32.768KHZ_12.5PF_9H03200413

L42
0_0603_5%

1019 change to
meet ME limit

1
C820

C822

1009 change
diode D53
direction

100P_0402_50V8J

TP_CLK 41
TP_DATA 41
@ R616
2
4.7K_0402_5%

0125 AC_LED connect to power


1102 For C0 -- R616 no stuff
Select SPI ROM or LPC
ROM

AGND

KB926QFB0_LQFP128_14X14

2
0.1U_0402_16V4Z

TP_BTN#

C2118
0.1U_0402_16V4Z

1212 For C
Revision
L43
1

2
0_0603_5%

NMI_DBG#
R625
10K_0402_5%

R1629
1
D52
1

SPI_CLK

+3VS

R642
2
1
10K_0402_5%

C828
15P_0402_50V8J

+5VL

1104 Change power rail from +3VL to +5VL

For EMI

1
10K_0402_5%

4.7U_0603_6.3V6K

CIR_IN

EC_RSMRST# 28
EC_LID_OUT# 28
EC_ON 47
1025 add
WL_BLUE_LED# 41
PM_PWROK 7,28 issue
BKOFF# 17
M_PWROK 7,28
TP_LED# 41
LAN_DSM#_KBC 31
SLP_S4# 28
ENABLT 20
EAPD_CODEC 34
THERM_SCI# 20,28
SUSP# 32,34,43,46,48,49,50,52
PWRBTN_OUT# 28

C821

R643
2
1
10K_0402_5%

CIR_IN 36,42
VCC1_PWRGD 39
FSTCHG 46
STD_ADP 46
CAPS_LED# 41
BAT_LED# 41
ON/OFFBTN_LED# 39,41
SYSON 32,41,43,49
VR_ON 51
2

2 4.7K_0402_5%
2 4.7K_0402_5%

MUTE_LED 42

AC_LED# 45
ISOLATEB 28,31
1

FRD# 39
FWR# 39
SPI_CLK 39
FSEL# 39

THERM_SCI#
SUSP#
PWRBTN_OUT#
NMI_DBG#

1212 Change power rail to +3VS


1025 Add Pull up
for ESB channel

R614 1
R617 1

DOCK_VOL_UP# 42
DOCK_VOL_DWN# 42

EC_ON
WL_BLUE_LED#
R2135 1
2
BKOFF# 100_0402_5%
M_PWROK
TP_LED#
LAN_DSM#_KBC

+3VS

2 4.7K_0402_5%
2 4.7K_0402_5%

ACIN 46

0125 Add R on MUTE_LED

EC_MUTE# 36,37
USB_EN# 38
I2C_INT 41
2
33_0402_1%

10K_0402_5%
2
+3VL

PCI_SERR# 26

KSO14
KSO11
KSO10
KSO15

to solve S4 can not work

KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

100P_1206_8P4C_50V8
@CP3
@
CP3
1
2
3
4

KSO2
KSO4
KSO7
KSO8

KSO0
KSI2
KSI3
KSO5

8
7
6
5

100P_1206_8P4C_50V8
@CP4
@
CP4
1
8
2
7
3
6
4
5
100P_1206_8P4C_50V8
@CP5
@
CP5
1
2
3
4

KSO1
KSI0

8
7
6
5

100P_1206_8P4C_50V8

G1
G2

KSI1
KSI7
KSI4
KSI5

27
28

CH751H-40PT_SOD323-2

0908 SWAP

EC_THERM

@CP6
@
CP6
1
2
3
4

8
7
6
5

100P_1206_8P4C_50V8

2
4,7,27 H_THERMTRIP#

8
7
6
5

KSO6
KSO3
KSO12
KSO13

ACES_85201-26051

R623
1

@CP1
@
CP1
1
2
3
4

100P_1206_8P4C_50V8
@CP2
@
CP2
1
8
2
7
3
6
4
5

17" INT_KBD
CONN.( TYPE "D"
CONN@
KB)
JP34

2
10K_0402_5%

2
B
E

Q5
MMBT3904_NL_SOT23-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

Deciphered Date

2006/03/10

Title

SCHEMATICS, MB A4082

1
1

+3VL

11
24
35
94
113

C551
15P_0402_50V8J

0_0402_5%
+5VL
2 LANPWR#_R

UTX

R639
R638

XCLK1
XCLK0

10M_0402_5%

ACES_85205-0400

ESB_CLK
ESB_DAT

122
123

69

CRY2
CRY1
CRY2

OSC

3
4

CRY1

OSC

2
3
4

GPI

LANPWR#_R
@ R455
1

EC
@
DEBUG
JP35
@
R2079
port
1 1
URX 1
2

2 33_0402_1%
DIM_LED

0125 Change R543 to 33 ohm

NC

31 LANPWR#

R543 1

SPI Device Interface

GND
GND
GND
GND
GND

R2078
1
2
0_0402_5%

41 ON/OFF
42 DOCK_SLP_BTN#
43 DIM_LED

+5V

ECAGND

26 PCI_PME#

D53
2

AC_IN

+3VL

CH751H-40PT_SOD323-2

DAC_BRIG 17
VCTRL 46
IREF 46
AC_SET 46

R621
28 SLP_S3#
28 SLP_S5#
28 EC_SMI#
41 LID_SW#
41 ESB_CLK
41 ESB_DAT

100P_0402_50V8J
ECAGND
1

C816 2
BATT_TEMP 45
BATT_OVP 45
ADP_I 46
ADP_ID 45
TP_BTN# 41
ANA_MIC_DET 36

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

100P_0402_50V8J

R1630
1
2
150K_0402_5%

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

C829

1106 Add EC_BEEP


21
23
26
27

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

1
2
3
4
5
7
8
10

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

+3VALW

R620
10K_0402_5%

AVCC

1
1
1
1

VCC
VCC
VCC
VCC
VCC
VCC

R605
R606
R607
R608

67

9
22
33
96
111
125

+3VS
U37

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

1212 Change to +3VL


+3VL

BATT_OVP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Thursday, January 08, 2009

Sheet

40

of

61

LED

WL_BLUE_LED# 40

HT-F196BP5_WHITE

+5VS_LED

+3VS
D

2
G

38 BT_LED

750_0402_5%

Cap Lock

40 CAPS_LED#

R1534
1

D35

White
1

Q114
2N7002_SOT23-3

1009 lower LED power consumption

R2098
10K_0402_5%
1

R505
100K_0402_5%

D28
ON/OFFBTN_LED#

R648
1

1212 Add R2098 for LED

System status LED

+5VALW_LED

+3VS

470_0402_5%

HT-F196BP5_WHITE

White

White
1

40 BAT_LED#

R631
1

2
HT-F196BP5_WHITE

Battery Charge LED

@
R2136
100K_0402_5%

+5VALW_LED

470_0402_5%

WL_LED#

32 WL_LED#

D91

D34

WL_BLUE_LED#

CH751H-40PT_SOD323-2

0125 Update WL_LED# circuit


White
2

R633

1
2
820_0402_5%

28 GPIO19

R2031

1
2
470_0402_5%

AMBER

HDD LED

+5VS_LED
+3VS

SWITCH BOARD.

1025 change to follow IBT00 design


1102 Change GSENSOR LED control pin from SB to KBC
1106 Delete R668, control by SB

ESB_CLK_CAP

@ R2116
2

C2123
2

C2124
2

33_0402_5%
@ R2117
ESB_DAT_CAP 2
2

+3VL_CAP

@
1

R2139

10K_0603_1%
1 @
C2126
1U_0603_10V4Z

SHDN#

GND

VIN

BP

VOUT

+5VS_LED

15P_0402_50V8J

FBMA-11-100505-801T 0402
39,40 ON/OFFBTN_LED#
2
2 FBMA-11-100505-801T 0402

Close to KBC

Updated @1029
R644 1
R646 1

39,40,45 SMB_EC_CK1
39,40,45 SMB_EC_DA1

APL5151-33BC-TRL SOT23 5P 3.3V

@
C2127
0.33U_0603_10V7K

CAP_CLK
CAP_DAT

2 0_0402_5%
2 0_0402_5%

40 I2C_INT
+5VALW_LED
40 LID_SW#
40 ON/OFF

1
2
R705
1.8K_0402_5%
1
2
R666 1K_0402_5%

@ D83

PJDLC05_SOT23~D

1212 Change TP power rail to +5VALW


0125 Add PJP6 and no-install Q29,Q31,R645

T/P Board (Inculde T/P_ON/OFF)


+5V

TP_BTN#
TP_LED#

+5VALW

1212 EMI request

+5VS_LED

TP_DATA
TP_CLK
2

@ Q29

D31
PSOT24C_SOT23-3

@ R645
10K_0402_5%

SI2301BDS-T1-E3_SOT23-3

0.1U_0402_16V4Z
1

D87
PSOT24C_SOT23-3
@

+5VS_LED

0125 Add D31 for ESD


TP_CLK 40
TP_DATA 40
TP_BTN# 40
TP_LED# 40

TP_BTN#
TP_LED#

ACES_85201-08051

@
C825
100P_0402_50V8J

SYSON

32,40,43,49 SYSON

CONN@
JP33
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
GND 9
GND 10

1 @
C824

ACES_85201-04051

+5V

PJP6
PAD-OPEN 2x2m
D

G1
G2

1
2
3
4

13
14

ACES_85201-1205N

1025 change Capactivity board pin defination

5
6

1
2
3
4

GND
GND

MV-1 HP request
@R2059
@R2059
1
2
0_0805_5%

1
2
3
4
5
6
7
8
9
10
11
12

0125 Add LDO for ENE cap. board power

K/B backlight
CONN@
JP51

CONN@
JP38
1
2
3
4
5
6
7
8
9
10
11
12

ESB_CLK_CAP
ESB_DAT_CAP

0125 Delete R640 for Cap. board issue


Change Conn to 12pin for ESB
3

C2122
4.7U_0805_10V4Z

R652 1
R641 1

40 ESB_CLK
40 ESB_DAT

+3VL_CAP

@U79
@
U79
2

+5VL

1225 Add R,C for EMI

PJP7
PAD-OPEN 2x2m

1212 Delete SW5,SW6

20080814 C2128,R641,R652 for ENE cap board

+3VL

+3VL_CAP

15P_0402_50V8J
@

33_0402_5%

for debug only

1224 Add Cap

0125 EMI request


Close to KBC
1009 Remove double pull up resisters

C2128
33P_0402_50V8K
ESB_CLK_CAP 2
1

1009 lower LED power consumption

Amber QSMF-C16E_AMBER-WHITE

27 SATA_LED#

D29
White

2
G

@
C826
100P_0402_50V8J

@
Q31
2N7002_SOT23-3

0226_Change package from 0603 to 0402.


SP01000H300 S H-CONN ACES 85201-0405N 4P P1.0
ACES_85201-0405N_4P

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


E

41

of

61

DOCKVIN

DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off
2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

Atlas/ Saturn Dock


CONN@
JP40

DOCKVIN

+5VS

43
44

43
44

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

41
42

41
42

SHIELD
SHIELD

45
46

C827
1000P_0402_50V7K

D43
DOCK_PWRON

1
3
+3VALW

DAN202U_SC70
2 1K_0402_5%

2
S

R593
10K_0402_5%

28
31
31
31
31
31
31
31
31

USB20_P3
RJ45_MIDI3+
RJ45_MIDI3RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI1+
RJ45_MIDI1RJ45_MIDI0+
RJ45_MIDI0-

GREEN
RED
D_DDCDATA
BLUE
D_HSYNC
D_DDCCLK
D_VSYNC
RJ45_MIDI3+
RJ45_MIDI3RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI1+
RJ45_MIDI1RJ45_MIDI0+
RJ45_MIDI0+V_BATTERY

CIR_IN
DOCK_PWRON
MUTE_LED
DOCK_SLP_BTN#
JACK_DET#
R_VOL_UP#
R_VOL_DWN#
SPDIFO_L
AUDIO_OGND
DOCK_LOUT_R
DOCK_LOUT_L
DOCK_MIC_R_C
DOCK_MIC_L_C
AUDIO_IGND
DOCK_PRESENT

FOX_QL1122L-H212AR-7F

need change to reverse type connector

C
@
Q112
MMBT3904_NL_SOT23-3

1 10K_0402_5%

C830
1000P_0402_50V7K

1000P_0402_50V7K

C895

R805
2K_0402_5%

C831

34 DOCK_MIC_R

1000P_0402_50V7K

34 DOCK_MIC_L

SPDIF_OUT_DOCK 34

R651
110_0402_5%

Need 600 Ohm 500 mA

MIC_Dock

R_VOL_DWN#

220_0402_5%
2

0.1U_0402_16V7K
R1622
1
2
0_0402_5%

220P_0402_25V8J

R647
1

220P_0402_50V7K

C902

C894
1
2

2
B

1
R_VOL_UP#

1
C924

C923

220P_0402_50V7K

C943

DOCK_MIC_R
DOCK_MIC_L

220P_0402_50V7K

Q14
2N7002_SOT23-3

R61
2K_0402_5%

220P_0402_50V7K

1
C942

1
1

DOCK_LOUT_R
DOCK_LOUT_L
1

L56
FBM-11-160808-601-T_0603
1
2

DOCK_MIC_R_C
DOCK_MIC_L_C

1
2
L55
FBM-11-160808-601-T_0603

1107 Delete C976,C977


C921

220P_0402_50V7K 2

C922

2 220P_0402_50V7K

+3VS

SENSE_B# 34

1009 Remove TV components


+3VS

R915
10K_0402_5%
R914
10K_0402_5%

Q100A
2N7002DW-7-F_SOT363-6

Q100B
2N7002DW-7-F_SOT363-6

10K_0402_5%
2

Q15

2
B
1

R913
47K_0402_5%

5
R912
DOCK_MIC_L_C 1

E
C978

MMBT3904_NL_SOT23-3

1U_0603_10V6K

22_0402_5%

1 10K_0402_5%

R595 2

@
R1621

SPDIFO_L

2
G
3

R594 2

DOCK_VOL_DWN#

+1.5VS

R804
2K_0402_5%

CONA# 40
R1570
1

DOCK_VOL_UP#

DOCK_LOUT_R 36
DOCK_LOUT_L 36

PAD-OPEN 2x2m

R62
10K_0402_5%

DOCK_PRESENT

+3VS

33_0402_5%

+3VL

1212 Change value

JACK_DET# 34,36
DOCK_VOL_UP# 40
DOCK_VOL_DWN# 40

2 200_0402_5%
2 200_0402_5%

1112 Change power rail from +3VALW to +3VL

R649 1
R650 1

B+

MUTE_LED 40
DOCK_SLP_BTN# 40

PJP3
1

1009 Add pull up


CIR_IN 36,40

Q36
2N7002_SOT23-3

2
G

43,50 SYSON#

GREEN
RED
D_DDCDATA
BLUE
D_HSYNC
D_DDCCLK
USB20_N3
D_VSYNC

R585 1

16
16
16
16
16
16
28
16

2 1K_0402_5%

1 1

R589 1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

Deciphered Date

2006/03/10

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Thursday, January 08, 2009

Sheet

42

of

61

+5VALW to +5VS Transfer


B+

+5VALW

+3VALW to +3VS Transfer

+5VS

B+

+3VALW

DIMM LED

+3VS
+5VALW

1212 For power sequence

C2119

2
DIM_LED#

2
1

2N7002DW-7-F_SOT363-6

C842

DIM_LED

40 DIM_LED

2N7002DW-7-F_SOT363-6

Q97
2N7002_SOT23-3

2
G

0.01U_0402_16V7K

0.01U_0402_16V7K

1009 Add for LED power

+1.8V to +1.8VS Transfer


+1.8V

+1.8VS

+5VL

+5VS

+5VS_LED

Q18

SI2301BDS-T1-E3_SOT23-3

+5VL

C962

IRF8113_SO8

SYSON#

42,50 SYSON#
2

Q96A
0.1U_0402_16V4Z
RUNON

R1932
1
2
150K_0402_1%

SUSP

SUSP 50

SYSON

32,40,41,49 SYSON

2N7002DW-7-F_SOT363-6

C294
0.1U_0402_16V4Z

DIM_LED#

Q96B

1212 Delete Q97B,R211

10U_0805_10V4Z

+1.8VS_ON
1

2
3

10U_0805_10V4Z

C1618

100K_0402_5%

C961

100K_0402_5%

R659

R658
1

220U_6.3VM_R15

1
2
3
4

S
S
S
G

D
D
D
D

C963

U59
8
7
6
5

C905
0.1U_0402_16V4Z

470_0402_5%
Q89A

SUSP

470_0402_5%

R877
10K_0402_5%

10U_0805_10V4Z

R2100
Q89B

C840

R657

RUNON_5VS

SUSP

0.1U_0402_16V4Z

2
RUNON

C839

10U_0805_10V4Z

3
1

330K_0402_5%

1
0.1U_0402_16V4Z

C838

1
2

C837

330K_0402_5%

R656
1

+5VALW_LED

Q66

SI2301BDS-T1-E3_SOT23-3
D

R2099
D

U40
8 D
S 1
7 D
1
S 2
C836
6 D
S 3
5 D
4
G
10U_0805_10V4Z
2
AO4466_SO8

U39
8 D
S 1
7 D
1
S 2
C841
6 D
S 3
5 D
4
G
10U_0805_10V4Z
2
AO4466_SO8

SUSP#

SUSP# 32,34,40,46,48,49,50,52

2N7002DW-7-F_SOT363-6

C2100

D78
2

0.1U_0402_16V4Z
H38
HOLEA

H37
HOLEA

1SS355_SOD323-2

H36
HOLEA

1212 Outline modify

H21
HOLEA

H22
HOLEA

H23
HOLEA

H24
HOLEC

H19
HOLEA

H25
H26
H27
HOLEC HOLEC HOLEC

H20
HOLEA

H29
HOLEC

2006/03/10

Deciphered Date

1
H34
HOLEA

H35
HOLEA

FM4
1

FM3

FM2

Compal Electronics, Inc.

Compal Secret Data


2006/02/13

H33
HOLEA
FM1

H32
HOLEA

H31
HOLEA

Security Classification

1
S

2
G

2N7002_SOT23-3

Issued Date

2
1
SUSP

2N7002DW-7-F_SOT363-6

H10
HOLEA

Q99
D

3
SUSP

Q95B

Q95A

2N7002DW-7-F_SOT363-6

SUSP

2N7002DW-7-F_SOT363-6

SUSP

2N7002DW-7-F_SOT363-6

SYSON#

2N7002DW-7-F_SOT363-6

SUSP

2
1

SUSP

2N7002DW-7-F_SOT363-6

Q94B

H17
HOLEA

H9
HOLEA

1
2

470_0603_5%

Q94A

H8
HOLEA

R697

470_0603_5%

R665

470_0603_5%

Q93B

H16
HOLEA

H7
HOLEA

R664

470_0603_5%
2

R663

470_0603_5%
2

R662

470_0603_5%
2

R661

470_0603_5%
2

R660

Q93A

H15
HOLEA

+1.8VS

H14
HOLEA

+0.9V

H13
HOLEA

+VCCP

+1.5VS

H12
HOLEA

H6
HOLEA

+1.8V

+3VS

+5VS

H5
HOLEA

H11
HOLEA

Discharge circuit

H3
HOLEA

H2
HOLEA

H1
HOLEA

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

43

of

61

@ R2104
1
2
0_0402_5%
L70

HDMI_R_CLK+

HDMI_TX1-

19 HDMI_TX1-

HDMI_TX1+

19 HDMI_TX1+

1
D79
BAT54AW_SOT323-3~D

HDMI_R_TX0+

WCM-2012-900T_0805
@ R2107
1
2
0_0402_5%
@ R2108
1
2
0_0402_5%
L72
HDMI_R_TX11 1
2 2
4

19 HDMI_TX219 HDMI_TX2+

HDMI_TX2+ 4

HDMI_HPD

0.1U_0402_16V4Z

2
R1571
1

C1349

R1572
2

+3VS

HDMIDAT
HDMICLK

2.2K_0402_5%

HDMI_R_CLK-

100K_0402_5%
4

U75
SN74AHCT1G125GW_SOT353-5

HDMI_R_CLK+
HDMI_R_TX0-

HDMI_DETECT 20

HDMI_R_TX0+
HDMI_R_TX1HDMI_R_TX1+
HDMI_R_TX2HDMI_R_TX2+

HDMI_R_TX2+

WCM-2012-900T_0805
@ R2111
1
2
0_0402_5%

HDMI_R_TX0HDMI_R_TX0+

@ C1249 1
@C1249
@C1250
@
C1250 1

2 100P_0402_50V8J
2 100P_0402_50V8J

HDMI_R_TX1HDMI_R_TX1+

@ C1251 1
@C1251
@C1252
@
C1252 1

2 100P_0402_50V8J
2 100P_0402_50V8J

HDMI_R_TX2HDMI_R_TX2+

@ C1253 1
@C1253
@C1254
@
C1254 1

2 100P_0402_50V8J
2 100P_0402_50V8J

RB411D T146 _SOT23-3

R1035
2.2K_0402_5%

2
C1348

HDMI_R_TX1+

WCM-2012-900T_0805
@ R2109
1
2
0_0402_5%
@ R2110
1
2
0_0402_5%
L73
HDMI_TX2- 1
HDMI_R_TX21
2 2
4

0.1U_0402_16V4Z

D41

R1036
2.2K_0402_5%

+5VS

HDMI_TX0+

19 HDMI_TX0+

1009 update correct CIS & P/N

5
1

19 HDMI_TX0-

+5VS

P
OE#

HDMI_TX0-

HDMI Connector

WCM-2012-900T_0805
@ R2105
1
2
0_0402_5%
@ R2106
1
2
0_0402_5%
L71
HDMI_R_TX01 1
2 2

HDMI_CLK+

HDMI_R_CLK-

CONN@
JHDMI

19 HDMI_CLK+

1212 Add 0 ohm

HDMI_CLK-

19 HDMI_CLK-

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

SUYIN_100042MR019SX53ZL
C

HDMI ESD
2

+3VS

20 HDMIDAT_VGA

Q98A
6

HDMIDAT

2N7002DW-7-F_SOT363-6

+3VS

20 HDMICLK_VGA

Q98B
3

HDMICLK

2N7002DW-7-F_SOT363-6
B

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

44

of

61

BATT
1

499K_0402_1% 340K_0402_1%
PR4 1
PR1 1
2
2

PL2
SMB3025500YA_2P
2
1

PC5
1000P_0402_50V7K
2
1

PC4
100P_0402_50V8J
2
1

PC3
1000P_0402_50V7K

PD1

2
1
PC2
100P_0402_50V8J

@PJSOT24C_SOT23-3

PJP1

PU1A
LM358ADT_SO8

BATT_OVP 40

0
-

PR5
10K_0402_5%
2
1

105K_0402_1%
PR6 1
2

ADPIN

1
PL1
SMB3025500YA_2P
1
2

DOCKVIN

1
2
PR3
10K_0402_5%

VIN

0.01U_0402_25V7K
PC6

ADP_SIGNAL

PC7
@100P_0402_50V8J

ACES_88334-057N

PD4
RLZ3.6B_LL34

PR8
100_0402_5%

PR2
10K_0402_5%

2 1

ADP_ID 40

AC_LED# 40

+5VALW
0.01U_0402_25V7K
PC1

1
2

100K_0402_5%
PR18

PQ3
TP0610K-T1-E3_SOT23-3

5
4
3
2
1

+3VL

+3VALW

5
4
3
2
1

PH1 under CPU botten side :


CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

PL4
HCB2012KF-121T50_0805

PH1
10K_TH11-3H103FT_0603_1%

SMB_EC_DA1

PR15
150K_0402_1%

PR11
150K_0402_1%
PR12
2.55K_0402_1%

PC10
0.22U_0603_10V7K

PD3
@SM24.TC_SOT23-3

1
1
PR14
100_0402_5%

PR13
100_0402_5%

+5VALW

SUYIN_200275MR008GXOLZR

EN0_TRIP 47

PR10
15K_0402_1%
1
2

PC9
0.01U_0402_50V4Z

PC8
1000P_0402_50V7K

0
G

1
2

PD2
@SM05_SOT23

CPU

EC_SMD
EC_SMC

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
GND
GND

PR7
47K_0402_1%
1
2

+5VS

BATT

PQ1
SSM3K7002FU_SC70-3

2
G

PU1B
LM358ADT_SO8

PC11
1000P_0402_50V7K

PJP2

PL3
HCB2012KF-121T50_0805
2
1

VMB

ENTRIP2 47

SMB_EC_DA1 39,40,41

SMB_EC_CK1

PQ2
@SSM3K7002FU_SC70-3

2
G

SMB_EC_CK1 39,40,41

BAT_ID 46

PR16
6.49K_0402_1%
1
2

+3VL

PR17
1K_0402_5%

Compal Secret Data

Security Classification
Issued Date

BATT_TEMP 40

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Sheet

Thursday, January 08, 2009


D

45

of

61

P4

B+

BATT
VIN

P2
PQ102
FDS6675BZ_SO8

4
DH_CHG

11

VDAC

PH

25

LX_CHG

12

VADJ

REGN

24

REGN

LODRV

23

DL_CHG

1
1
3
PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2

5
6
7
8
1
PQ110
AO4468_SO8
1

EXTPWR

22

3
2
1

PC119

1
2

1
2

PC124
0.1U_0603_25V7K

BATT
1

IREF 40

PC122
@0.1U_0603_25V7K

BAT_ID 45

PR122
1M_0402_5%
1
2

VIN_1

PR120
2
1
133K_0402_1%
PR121
200K_0402_1%

PD104
RLS4148_LL34-2

PC123
0.1U_0402_10V7K

20

19

18

17

16

21

PR119
47K_0402_5%
2
G
PQ111
SSM3K7002FU_SC70-3

VIN

BQ24740VREF

PC121
100P_0402_50V8J
2
1

PC120
0.22U_0603_10V7K
2
1

40 ADP_I

PR117
100K_0402_5%
1
2

IADAPT

15

2
PR118
10K_0402_5%
1
2

Charge Detector

PC118
0.1U_0402_10V7K

1U_0603_10V6K

DPMDET

CELLS

PGND
SRP

IADAPT

PR116
29.4K_0402_1%

SRN

ISYNSET

14
PR115
100K_0402_1%

BATT

PR112
0.015_1206_1%
1
2

PC116
4.7U_0805_25V6-K

26

VREF

PQ106
DTC115EUA_SC70-3

PQ108
AO4466_SO8

PC115
4.7U_0805_25V6-K
2
1

HIDRV

10

PC111
0.1U_0402_10V7K
1
2
4

BST_CHG

27

PC114
4.7U_0805_25V6-K

28

BTST

PR123
1M_0402_5%
1
2

+3VL

PR124
1K_0402_5%
1
2

VIN

VIN

PACIN

LM393DG_SO8

8
P
G

PR133
10K_0603_0.1%

PU102B

PR134
10K_0402_5%

PD103
RLZ4.3B_LL34

S
FSTCHG#
1

VIN_1

PQ113
SSM3K7002FU_SC70-3
3

STD_ADP 40

PR136
60.4K_0402_1%
1
2

2
G

40 FSTCHG

1.24VREF

PQ112
SSM3K7002FU_SC70-3

PU102A
LM393DG_SO8

2
G

PC126
0.047U_0402_16V7K

PR127
10K_0402_1%

PR135
10K_0603_0.1%

PR132
100K_0402_5%
2
1

1
-

PR130
2.15K_0402_1%
1
2

PR128
100K_0402_5%
2
1

1
2

CHGEN#

PC125
0.1U_0603_25V7K

PR129
10K_0402_1%
2
1

1
PR131
133K_0402_1%

PR126
133K_0402_1%
+3VL

ACIN 40

+3VL
PR125
47_1206_5%

VIN

ACOFF 40

5
6
7
8

1
CHGEN

2
ACN

3
ACP

PVCC

AGND
PU101
BQ24740RHDR_QFN28_5X5

PC110
1U_0805_25V6K
1
2

RLS4148_LL34-2

PC117
1U_0603_6.3V6M

1
2

PC105
4.7U_0805_25V6-K

1
2

PC104
4.7U_0805_25V6-K

1
2

1
2

1
2

PC103
4.7U_0805_25V6-K

PC108
0.1U_0603_25V7K
5

4
LPMD

29

40 VCTRL

TP

PC113
4.7U_0805_25V6-K
2
1

PD101
RLS4148_LL34-2

CHG_B+

IADSLP

13

VIN

PR105
10K_0402_5%

PR108
10_1206_5%
1
2

PR114
@0_0402_5%
1
2

PR103
47K_0402_5%
1
2

ACOFF#

PD102
VADJ

PR113
143K_0402_1%

PC109
@0.1U_0603_25V7K

BAT

PC102
1U_0603_6.3V6M

+3VL

ACOFF#

8
7
6
5

CHG_B+

3
2
1

2
PQ109
SSM3K7002FU_SC70-3

1
2
3

PL101
HCB2012KF-121T50_0805
2

BQ24740VREF

PC112
1
2
1U_0603_6.3V6M

2
G
3

PACIN

PR111
3K_0402_1%
1
2

ACDET

LPREF

7
SUSP#

1
1

32,34,40,43,48,49,50,52
PR109
150K_0402_5%

PACIN_1 47

PR110
0_0402_5%
1
2

2
G

CHGEN#

ACSET

PC107
@0.01U_0402_16V7K

2
1
PR106
200K_0402_5%

PC106
0.22U_0603_16V7K
2
1

DTA144EUA_SC70-3
PQ104

ACSET

SRSET

1
ACDET

PR104
0_0402_5%
1
2

PQ105
DTC115EUA_SC70-3

PQ107
SSM3K7002FU_SC70-3

PR102
0.012_2512_1%
1
2

8
7
6
5

40 AC_SET

1
2
3

PR101
47K_0402_5%
1
2

PC101
47P_0402_50V8J
PR107
47K_0402_1%
1
2

PQ103
AM4835EP-T1-PF_SO8

1
2
3

8
7
6
5

100K_0402_5%
PR139

PQ101
AM4835EP-T1-PF_SO8

S
PU104
4

ACDET

22P_0402_50V8J
2

100K_0402_1%
PR138

PC127
PR137
20K_0402_1%

REF

NC

NC

1.24VREF

ANODE

LMV431ACM5X_SOT23-5

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CATHODE

Compal Electronics, Inc.


SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Thursday, January 08, 2009
D

Sheet

46

of

61

PR304
20K_0402_1%
1
2

20

LX_5V

12

DRVL2

DRVL1

19

LG_5V

5
6
7
8

1
2

4.7U_0805_25V6-K
PC313
2
1

4.7U_0805_25V6-K
PC305

5
6
7
8

PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

+5VALWP
PC310
150U_D_6.3VM

21

LL1

TPS51125RGER_QFN24_4X4

18

EN0

3
2
1

DRVH1

LL2

PR308
PC308
0_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2

UG1_5V

DRVH2

11

VCLK

10

13

PC304
2200P_0402_50V7K

1
ENTRIP1

VFB1

VREF

VFB2

22

3
2
1
B++

2
G

PQ305
SSM3K7002FU_SC70-3

2VREF_51125
D

PQ306
SSM3K7002FU_SC70-3

2
G

PC311
10U_0805_10V6K

45 ENTRIP2

PR316
1
2
0_0805_5%

PR312
@0_0402_5%

2
1
PC312
0.1U_0603_25V7K

ENTRIP1

PQ304
FDS6690AS_NL_SO8

VL

PR317
0_0402_5%

PR311
@620K_0402_5%
2
1

45 EN0_TRIP

1
2
3

ENTRIP2

23

VBST1

PQ303
AO4468_SO8

PC309
220U_6.3VM_R15

LG_3V

PGOOD

VBST2

VREG5

UG_3V

PQ302
AO4466_SO8

VREG3

VIN

17

16

8
7
6
5

PL302
3.3UH_SIQB74B-3R3PF_5.9A_20%
2
1

BST_3V

PR306
110K_0402_1%
2

24

GND

1
2
3

UG1_3V

+3VALWP

PR307
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V

B++

VO1

SKIPSEL

VO2

TONSEL

7
4
PR309
0_0402_5%
1
2

P PAD

15

PQ301
AO4466_SO8

PU301

25
2

PC306
10U_0805_6.3V6M

8
7
6
5

1
2

PC303
4.7U_0805_25V6-K

1
2

PR305
115K_0402_1%
1
2

ENTRIP1

PR303
20K_0402_1%
1
2

+3VLP

2
PC301
2200P_0402_50V7K

PR302
30.9K_0402_1%
1
2

ENTRIP2

PL301
HCB2012KF-121T50_0805

PR301
13.7K_0402_1%
1
2

14

B++

B+

PC302
0.22U_0603_10V7K

2VREF_51125

R_EC_RSMRST# 28
3

+5VL

VL
PJP302
@ PQ308
SSM3K7002FU_SC70-3

VL

PR313
100K_0402_5%
PQ307
2
G
SSM3K7002FU_SC70-3

+5VALWP

PJP304

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALWP

+3VL

+3VLP
+3VALW

PJP301

(3A,120mils ,Via NO.= 6)


2

PAD-OPEN 4x4m

1
PAD-OPEN 2x2m
4

100K_0402_5%
PR314

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

1
PAD-OPEN 2x2m

PAD-OPEN 4x4m
PJP303

EC_ON 40

1
3

@
4

2
G
2
1
PC314
0.022U_0402_16V7K

46 PACIN_1

@ PR315
604K_0402_1%
1
2

Compal Electronics, Inc.


SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Thursday, January 08, 2009

Sheet
E

47

of

61

VFB

15
TP

DH_1.5V

12

LX_1.5V

TRIP

11

V5DRV

10

DRVL

PL402
3.3UH_PCMC063T-3R3MN_6A_20%
1
2

1
+5VALW

2
PR406
13K_0402_1%

PQ402
AO4468_SO8

DL_1.5V

4
2

PC406
4.7U_0805_10V6K

+1.5VSP

3
2
1

PR407
1
2
10K_0402_1%

PGOOD

13

LL

PC409
220U_B2_2.5VM

DRVH

V5FILT

VBST

PGND

VOUT

TON

+1.5VSP

EN_PSV

2
PC405
1U_0603_10V6K

PR405
2
1
0_0402_5%

AO4466_SO8
PQ401

GND

PU401
PR404
255K_0402_1%
1
2

PC402
0.1U_0402_10V7K

14

1
PR403
316_0402_1%

+1.5VSP

BST1_1.5V 1

PR402
0_0402_5%

1
2
BST_1.5V
1

5
6
7
8

+5VALW

3
2
1

PR409
@10K_0402_5%

5
6
7
8

1
1
2

PC401
0.1U_0402_10V7K

PC404
2200P_0402_50V7K

B++

PR401
4.7K_0402_5%
1
2

PC403
4.7U_0805_25V6-K

,50,52 SUSP#

TPS51117RGYR_QFN14_3.5x3.5

PJP401
+1.5VSP

PR408
10K_0402_1%

+1.5VS

(4A,160mils ,Via NO.=8)

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Thursday, January 08, 2009
D

Sheet

48

of

61

PR501
29.4K_0402_1%
+1.05V_VCCP

B+++

B+++

B+
PL502
HCB2012KF-121T50_0805
2
1

2
0_0402_5%

1
PR508

LX_1.05V

11

LL2

LG_1.05V

12

DR VL2

BST_1.8V

21

UG_1.8V

20

LX_1.8V

19

LG_1.8V

2
UG1_1.8V

1
PR509
0_0402_5%

1
2

1
2

+1.8VP

PL503
1.8U_D104C-919AS-1R8N_9.5A_30%

+1.8VP

PR510
12.1K_0402_1%

330U_2V_M_R15M

S
S
S

3
2
1

1
2
3

PR511
13.7K_0402_1%
1
2

PC510
4.7U_0805_6.3V6K

1
+

PC517

PQ504
FDS6670AS_NL_SO8

D
D
D
D

TRIP1

PGND1
18

TPS51124RGER_QFN24_4x4

17

V5IN
16

15

13

V5FILT

5
6
7
8

LL1
DR VL1

PC507
0.1U_0402_10V7K

PR507
0_0402_5%
2
1

5
6
7
8

1
VO1

VFB1

22

DR VH1

PGND2

1
PC509
4.7U_0805_6.3V6K

VBST1

DR VH2

PQ503
AO4468_SO8

GND

VBST2

2200P_0402_50V7K
PC505

10

23

PC519
4.7U_0805_25V6-K

UG_1.05V

24

EN1

PC518
4.7U_0805_25V6-K

BST_1.05V

PGOOD1

PC504
4.7U_0805_25V6-K

EN2

TONSEL

PGOOD2

TRIP2

UG1_1.05V

8
7
6
5

PL501
2.2UH_PCMC063T-2R2MN_8A_20%
+1.05V_VCCP
2
1

VO2

PQ502
AO4466_SO8

3
2
1

PC506
PR506
0.1U_0402_10V7K
0_0402_5%
2
1 2
1

1
2
3

+1.05V_VCCP

+1.8VP

1
4

VFB2

AO4466_SO8

P PAD

14

8
7
6
5

1
2

2200P_0402_50V7K
PC502

1
2

PC516
@4.7U_0805_25V6-K

PC501
4.7U_0805_25V6-K

PU501

25

PR504
14.3K_0603_0.1%
1
2

PC503
@0.022U_0402_16V7K

PQ501

PR503
10.2K_0603_0.1%
1
2

PR505
0_0402_5%

PR502
75K_0402_1%

B+++

PC508
220U_D2_4VM

PR513
0_0402_5%
2

32,34,40,43,46,48,50,52 SUSP#

1
1

PR512
0_0402_5%
2

SYSON 32,40,41,43

+5VALW

1
2

PC515
4.7U_0805_10V6K

PC512
@0.1U_0402_16V7K

PC514
1U_0603_10V6K

PC513
@0.1U_0402_10V7K

PR514
3.3_0402_5%

PJP501

+1.05V_VCCP

+VCCP

(6A,240mils ,Via NO.=12)

+1.8V

(7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m
PJP502

+1.8VP

2
PAD-OPEN 4x4m

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Thursday, January 08, 2009

Sheet
1

49

of

61

+1.8V

VCNTL

GND

NC

VREF

NC

VOUT

NC

TP

+5VALW

1
2

PR601
1K_0402_1%

PC601
10U_0805_10V4Z

VIN

2
1

PU601

PC603
1U_0603_10V6K

G2992F1U_SO8

+0.9VP
1

2
G

PR603
1K_0402_1%

1
PR604
0_0402_5%

43 SUSP

PQ601
SSM3K7002FU_SC70-3

PR602
@0_0402_5%

2
1
PC604
0.1U_0402_10V7K

42,43 SYSON#

PC605
10U_0805_6.3V6M

PC606
@0.1U_0402_16V7K

+5VALWP

PR606
0_0402_5%

PJP603

EN

PC611
@0.01U_0402_16V7K

+PCIE

(3A,120mils ,Via NO.= 6)

1
5
9

VOUT

VOUT

FB

PC610
10U_0805_6.3V6M

VIN

+1.1V_PCIE
PC612
22U_0805_6.3V6M

+1.1V_PCIE

VIN

2
1

32,34,40,43,46,48,49,52 SUSP#

POK

PU603

(2A,80mils ,Via NO.= 4)

+0.9V

PR607
40.2K_0402_1%

PAD-OPEN 3x3m

PC613
47P_0402_50V8J

APL5913-KAC-TRL_SO8

2
PAD-OPEN 3x3m

VCNTL

GND

+0.9VP

+1.5VS

PC609
1U_0603_10V6K

PJP601

PR608
105K_0402_1%

Compal Secret Data

Security Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Thursday, January 08, 2009

Sheet
1

50

of

61

23

ISEN1

PWM2

26

PC204
10U_1206_25V6M
2
1

@100P_0402_50V8J
PC247
1
2

2
PR230
4.7_1206_5%

PR202
4.7_1206_5%
2

DL_CPU1

1
PR207
@0_0402_5%

VSUM

VO

ISEN1

+CPU_B+

PR209

UGATE2

PHASE2

LGATE2

BST_CPU2_1

BST_CPU2_2
PC217
0.22U_0603_16V7K
1
2

0_0402_5%

PQ203
SI4684DY-T1-E3_SO8

ISL6210CRZ-T_QFN16_4X4

PC241
10U_1206_25V6M
2
1

ISEN1

10

4
3
2
1

PWM1

BOOT2

27

TP

PWM1

LGATE1

5
6
7
8

EN

PGND

40

39

18
VIN

FCCM

17
SOFT

13

PC242
10U_1206_25V6M
2
1

PWM2

12

PHASE1

+VCC_CORE

PC212
2200P_0402_50V7K
2
1

1
6

PGOOD

NTC

3V3

19

20

VSS

VDD

RBIAS

PR203
10_0402_1%

PC208
0.22U_0603_16V7K
2
1

PR206
5.11K_0402_1%

PC240
@2200P_0402_50V7K
2
1

PWM1

16

UGATE1

PR204
10K_0402_1%
1
2

1
15

PC209
2200P_0603_50V7K
2
1
1

PVCC

1U_0603_10V6K

ISL6260CCRZ_QFN40_6X6

3
2
1
BOOT1

3
2
1

14
VCC

11

D
D
D
D

G
S
S
S

VGATE 15,28

4
3
2
1
5
6
7
8

PQ202
FDS6676AS_SO8

GND

PR208
1.91K_0603_1%

PC200
68U_25V_M_R0.36

D
D
D
D
2

PQ201
FDS6676AS_SO8

+5VS

PU201

PC216
2
1

1
5
6
7
8

PR205
10_0603_5%
2
PC210
1U_0603_10V6K
2
1

LX_CPU1

PC224

VR_TT#

0.36H_ETQP4LR36WFC_24A_20%

PR210 1
2
147K_0402_1%

PC205
1U_0603_10V6K
2
1

PR252
1_0402_5%

PL201

DH_CPU1

+3VS

PU200

B+

G
S
S
S

BST_CPU1_1

+5VS

PL200
SMB3025500YA_2P
1
2

PQ200
SI4684DY-T1-E3_SO8

PR200
PC206
0_0402_5%
0.22U_0603_16V7K
2
1BST_CPU1_2 1
2

0.01U_0402_25V7K
PC207
2
1

PR201
10_0603_5%

PC203
10U_1206_25V6M
2
1

PC239
1500P_0402_50V7K
2
1

5
6
7
8

+CPU_B+

PC202
2200P_0402_50V7K
2
1

+CPU_B+

PC201
68U_25V_M_R0.36

PL202

0.015U_0402_16V7K

PR246
1K_0402_1%
2
1

1
PC237
0.01U_0402_16V7K

PC238
1

PC230
@0.22U_0603_16V7K
1
2

PU203
VCC

BOOT

FCCM UGATE

DH_CPU3

PWM PHASE

LX_CPU3

GND

2
PC243
@4.7U_0805_25V6-K
2
1

PC244
@4.7U_0805_25V6-K
2
1
1

@ISL6208CRZ-T_QFN8
PQ207
@AO4456_SO8

PQ208
@AO4456_SO8

DL_CPU3

Issued Date

PR243
@10K_0402_1%
1
2

PR248
@5.11K_0402_1%

+VCC_CORE

Compal Secret Data


2005/03/10

Deciphered Date

2006/03/10

Title

Date:

PC235
@0.22U_0603_16V7K
2
1

PR241
@10_0402_1%

1
PR249
@0_0402_5%

VSUM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC227
@4.7U_0805_25V6-K
2
1

PC226
@4.7U_0805_25V6-K
2
1

PL203
@0.36H_ETQP4LR36WFC_24A_20%

LGATE

Security Classification

PC225
@2200P_0402_50V7K
2
1

5
6
7
8
D
D
D
D

PQ206
@SI4684DY-T1-E3_SO8

330P_0402_50V7K

2
1

2
PR233
4.7_1206_5%
1
1
2

PC248
@100P_0402_50V8J

PR218
4.7_1206_5%
2
PC219
2200P_0603_50V7K
2
1
1

5
6
7
8
3
2
1

3
2
1
2

PR245
5.11K_0402_1%
2
1

+CPU_B+

1000P_0402_50V7K
PR242
2
1
6.98K_0402_1%

VO

VO

PC233
1

5
6
7
8

PC228
51K_0402_1%
0.022U_0402_16V7K

220P_0402_25V8J

GND

1
PR225
@0_0402_5%

VSUM

PR251
@4.7_1206_5%

PR244
1K_0402_1%
1

PC232
1
2

2 PR238

17

VW

14

VSUM

VSUM

PC246
@2200P_0402_50V7K
2
1

41

1.2K_0402_1%

COMP

PR232
@0_0402_5%
2
1

PR240
PC236
@4.7_1206_5%
@2200P_0603_50V7K
1
2
2
1
1
2

1
0_0402_5%

5
6
7
8

PR235
2

PR231
2
1
11.5K_0402_1%

3
2
1

PC222
1800P_0402_50V7K
1
2
2 PR236

PR224
5.11K_0402_1%

ISEN2

G
S
S
S

PR234
180_0402_1%
2
1

PC218
0.22U_0603_16V7K
2
1

+5VS

BST_CPU3_2

5 VSSSENSE

OCSET

PR221
10K_0402_1%
1
2

ISEN3

4
3
2
1

FB

21

5
6
7
8

10

ISEN3

+VCC_CORE
PR219
10_0402_1%

PWM3

3
2
1

VDIFF

DL_CPU2

2
1
@0_0402_5%

PC245
@82n_0402_10V7K

+5VS

PR229

BST_CPU3_1

RTN

11

25

13

2
1
0_0402_5%
PWM3

PC223
@1U_0603_10V6K

VSEN

1000P_0402_50V7K

VR_ON

12

FDS6676AS_SO8

PR227

PC221
1

35

24

FCCM

CLK_EN#

1000P_0402_50V7K

PMON

38

PR237
3K_0402_1%

PC220
2
1

PSI#

PQ205

FDS6676AS_SO8

DPRSLPVR

2 PR228 1
0_0402_5%

5 VCCSENSE

PQ204

0.1U_0402_10V7K

15 CLK_ENABLE#
40 VR_ON

1 0_0402_5%

ISEN2

ISEN2

22

PC231
0.22U_0603_10V7K
1
2

2 PR226

PR250
0_0402_5%

PH200
10KB_0603_5%_ERTJ1VR103J
2
1
PR247
@1K_0402_1%

499_0402_1%

2 PR223 1
0_0402_5%

5 H_PSI#

DPRSTP#

0.36H_ETQP4LR36WFC_24A_20%

LX_CPU2

PC234
2
1

7,28 DPRSLPVR
D

37
36

PWM2

PC229
1000P_0402_50V7K

2 PR222

VO

16

2 PR220
0_0402_5%

5,7,27 H_DPRSTP#

VID0
VID1
VID2
VID3
VID4
VID5
VID6

PR239
4.53K_0402_1%
2
1

DH_CPU2

28
29
30
31
32
33
34

DFB

15

DROOP

2 PR212
0_0402_5%
2 PR214
0_0402_5%
2 PR216
0_0402_5%

PR2111
0_0402_5%
2 PR213 1
0_0402_5%
2 PR215 1
0_0402_5%
2 PR217 1
0_0402_5%
2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

5
5
5
5
5
5
5

VO

Compal Electronics, Inc.

SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Thursday, January 08, 2009

Sheet

51
1

of

61

PR719
0_0402_5%
2
1

PR702
47K_0402_5%
1
2

+6269_VCC

PC707
2.2U_0603_10V6K

15

LX_VGA

UG

14

DH_VGA

BOOT

13

BST_VGA 1

1
2

1
@680P_0603_50V7K

1
+
2

1
+
2

PC718
330U_2V_Y_D2_LESR9M

PC709

PC714
330U_2V_Y_D2_LESR9M

1
PR703
2.2_0402_5%

PR722

+6269_VCC

6269_PVCC

1_0603_5%

PJP701
+NVVDDP

(12A,480mils ,Via NO.= 24)

+NVVDD

PAD-OPEN 4x4m
PJP702

GPUID0
0
1
0

1
1

+5VS
PQ704
SSM3K7002FU_SC70-3

PC701
2.2U_0603_10V6K

GPUID1
0
0
1

+NVVDDP

PC713
330U_2V_Y_D2_LESR9M

3
2
1

3
2
1

PC708
330U_2V_Y_D2_LESR9M

12

11

10

PR709
2
1
0_0402_5%

FDS6676AS_SO8

1
1
2

PQ702 PR710
@4.7_1206_5%

PQ703
6269_PVCC

2 2

PC706
0.22U_0603_16V7K

10K_0402_1%

PL702
0.33UH_PCMC063T-R33MN_20A_20%
1
2

PR708
2.2_0402_5%

BST1_VGA1

2
G
1

PR718
10K_0402_1%
3

+NVVDDP

G
S
S
S
2

DH_VGA_1

PR705
1
2
8.25K_0402_1%

PC711
0.01U_0402_16V7K

20 GPU_VID0

PR713
10.7K_0402_1%

PR716
2

PQ705
SSM3K7002FU_SC70-3

1
PR715
10K_0402_1%
PR717
10K_0402_1%

2
G
3

20 GPU_VID1

1
2
1
PC712
0.022U_0402_16V7K

PC705
@680P_0402_50V7K

4
3
2
1

PR711
0_0402_5%
1
2

5
6
7
8

LG

PVCC

VO

PR704
4.32K_0402_1%

2
1
PC715
0.01U_0402_16V7K 8

PGND

PR714
6.81K_0402_1%

ISEN

PHASE

PQ701
SI4684DY-T1-E3_SO8

5
6
7
8

2
1
PR706
49.9K_0402_1%

1
VIN

FCCM

16

FDS6676AS_SO8

FSET

PGOOD
PU701
ISL6269ACRZ-T_QFN16_4X4

5
6
7
8

17

D
D
D
D
FB

VCC

4
EN
6

GND

+NVVDDP

1
2
PR707
2.1K_0402_1%

COMP

B+

PC710
2200P_0402_50V7K

PR712
10_0402_5%
1
2

PC704
10U_1206_25V6M

PR721
2
1
0_0402_5%

18 VDD_SENSE

PC703
10U_1206_25V6M

2
1
PC716
22P_0402_50V8J
PR720
2
1
2
1
PC717
90.9K_0402_1%
6800P_0402_25V7K

PL701
HCB2012KF-121T50_0805
2
1

VGA_B+

PC702
0.1U_0402_10V7K

32,34,40,43,46,48,49,50 SUSP#

NB9P-GS
0.89V
1.0V
1.05V

2
PAD-OPEN 4x4m
PJP703

2
PAD-OPEN 4x4m

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATICS, MB A4082
Document Number

Rev
G

401540
Thursday, January 08, 2009
D

Sheet

52

of

61

Version Change List ( P. I. R. List ) for Power Circuit


Item Page#
D

43

Date

Request
Owner

Issue Description

Solution Description

Cut in
D

44
50

DCIN/
BATTERY CONN
2006/09/07 HP R.L.
Charger
ADP_OCP

Change charger control from HW to FW

All the related components

50

ADP_OCP

2006/10/12 HP R.L.

Identify 65W adapter as "light"

Change PR223 from 180K to 147K

DB2

51

VDD_CORE
/PCIE_VDD

2006/10/12 HP R.L.

Change VGA chipset from ATi M62S to M64S

Change PR355 from 11K to 9.76K


Change PR392 from 33.2K to 24.9K

DB2

52

+1.25VMP/
+1.05V_VCCP

2006/10/12 HW

For HW's requirement, fine tune +1.05V_VCCP sequence

Change PR249 from 0 to 47K


Add PC186 as 47pF
Install PD45

DB2

51

VDD_CORE
/PCIE_VDD

2006/10/12 PWR

Fine tune PCIE_VDD

Change PR358 from 47K to 49.9K


Change PR359 from 150K to 100K

DB2

51

VDD_CORE
/PCIE_VDD

2006/11/08 HW

Fine tune the GPU "Power Play" sequence

Add PC196 as 1uf

VDD_CORE
/PCIE_VDD

2006/11/08 HW

Fine tune the power sequence of PCIE_VDD

Change PU31 pin5, 9 source from VDD_MEM18 to +1.8V

Charger

2006/11/08 PWR

Base on "Energy STAR" spec, reduce S5 and S3


power consumption (AC mode)

Uninstall PQ11

SI

Add PR387

SI

For HW's requirement, fine tune +2.5VS sequence

Change PR243 to 47K,


Change PC170 to 0.1uF

SI

6
C

8
9

Title

51
44

Tony J

Francis H
Tony J
Tony J

DB1B

SI
C

SI

10

48

1.8V/0.9V

Francis H
2006/11/08 HP
Add PM_SLP_M# sequence

11

52

+1.25VMP/
+1.05V_VCCP

2006/11/20 HW

12

52

+1.25VMP/
+1.05V_VCCP

2007/2/28

HW
Tony J

Fine tune the +2.5VS power level to 2.57V (typ)

Change PR244 from 13K to 13.7K

SI2

13

50

ADP_OCP

2007/2/28

HP R.L.

System identity

Change PR223 from 147K to 137K

SI2

Tony J

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/02/13

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

53

of

61

Item

<2007.10.08>

Fixed Issue

Fix Audio disappear

Reason for change

PAGE

Modify List

follow Intel SB design suggestion to separate HDA Bus

27

Add R439, R440, R442, R444

Add to determine board type and project

28

Add R777, R776, R774, R775

28

non-stuff R419, R695

follow Intel SB design suggestion

29

Change power rail from +1.5v to +3v

meet SW debug request

32

Add Debug CLK and PLT_RST#

Meet EC request

M.B. Ver.

0.2

0.2

Fix Audio disappear

3
4

0.2

Fix Audio disappear

follow Intel HDA bus design for Discrete platform

34

Change codec power rail from +1.5v to +3v

0.2

Fix can not power on issue

Meet EC and SPI access sequence

39

change SPI power rail from+3valw to +3VL

0.2

Change R30 value

0.2

change HDMI I2C channel to I2C B channel

0.2

<2007.10.09>

0.2

Follow Intel design guide

follow Nvidia design request

18

Meet HP request to remove TV

18

Remove TV all components at VGA side

update ODD footprint

30

update JODD footprint

lower system power consumption

33

change Card Reader LED power rail

Meet Sub-woofer pwoer request

37

change D81, D82

Solve EC always damage

40

change D53 direction

Double pull up and pwoer rail is different

41

Remove pull up resisters

lower system power consumption

Meet HP request to remove TV

10

lower system power consumption and meet LED status

11

solve HDMI pull up

Fix HDMI can not detect

0.2

0.2

Fix ODD wrong pins

5
6

Solve EC always damage

41

<2007.10.19>

<2007.10.20>

<2007.10.22>

Meet ME limit area at KBC

0.2
0.2
0.2

change Cap-lock, HDD LED power rail

0.2

42

Remove TV all components at Dock side

0.2

43

Add +5VS_LED (Inculde DIM function)

0.2

update D79 footprint

0.2

27

Change Y4 material

0.2

44

0.2

Follow IDT suugestion

35

change R886 to 1206

0.2

Follow Nvidia suggestion

25

Change R193, R196 size to 0603

0.2

follow correct power rail

38

change Touch screen power rail

0.2

Meet HP request

39

Change ST G-sensor P/N & package

0.2

Meet HP request for WLAN &TV slot swap

32

Swapped WLAN and TV all support components

0.2

Change LAN chip to meet Energy star spec

31

change LAN brand to Realtek

0.2

2
A

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

54

of

61

Item

<2007.10.23>

Fixed Issue

Fix USB loading of SB

Reason for change

PAGE

follow 14" Blade USB channel design

Modify List

M.B. Ver.

28

Chnage all USB channel

17

Change USB channel of Camera

32

Change USB channel of WLAN & TV Tuner & New card

0.2

38

Change USB channel of Left side, Right side, E-SATA

38

Change USB channel of Touch screen, Finger print

42

Change USB channel of Dock

Follow JMicro CardReader Vendor Suggestion

33

Change R114 & R1546 value

Solve Speak no sound issue

36

add pullup at HP_DET#

36

Change Q203 to N-channel FET

34

Change R524 pin2 connect to JACK_DET#

add GTLREF and XDP circuits

Meet HP request for QC and DC co-lay

0.2

0.2

<2007.10.25>

0.2

<2007.10.31>

<2007.11.02>

Meet Intel request for CLK request

Solve G-sensor LED control

Follow Capactivity board design

Add R127 to meet Intel CLK design

0.2

change G-sensor LED control to GPIO19 of SB

0.2

41

change Pin7 & 7 NET

0.2

34

Use Audio Codec GPIO5 to shutdoown Sub-woofer

40

Connect HDA_RST#_CODEC to EC

34

Separate SPDIF out to VGA and Docking

15
28, 41

Common design

16

R204,R205 no stuff

0.3

Change +5VS_LOGO resistor size to 0805

17

R642 size to 0805

0.3

Double pull up

20

R2046,R2047 no stuff

0.3

For card reader power

33

install R1553

0.3

For KBC C0 version

40

R616 no stuff

0.3

Add pull down resistor for SUSP# and SYSON

40

Change R615 to 8.2k and add R2062

0.3

Change HAD_RST#_CODEC from KBC pin 36 to pin 38

40

Change GSENSOR LED control pin from SB to KBC

41

Install R668, no install R667

0.3

Add pull down for sub-woofer power-down

37

Add R2063

0.3

2006/02/13

2006/03/10

Deciphered Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

0.3

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

55

of

61

Item

<2007.11.04>

Fixed Issue

Reason for change

PAGE

Modify List

M.B. Ver.

Move resistor from LS4086P to MB

41

Add R2064

0.3

Change to dual type for layout space

16

Change Q69,Q70 to dual type

0.3

Only use LIS302DLTR

39

U77, R2025 no install

0.3

Change CIR_IN power rail

40

Connect R642.1 to +5VL

0.3

nVIDIA suggestion for NB9M-GS/GE

22

R1005 change to 475 ohm

0.3

nVIDIA suggestion -- add Pull up 2.2K on


HDMIDAT_VGA and HDMICLK_VGA to
+3VS. at VGA side

18

Add R2065,R2066

0.3

CRT add resistor for EMI

16

Add R2069,R2070,R2071

0.3

HP suggestion

34

Change C746,C747,C748,C749 to 1000PF

0.3

USB camere power and add GPO pin for shutdown

17

Add PJP5,R2072,R2073

0.3

LAN DSM support

31

1. USB camera SB GPIO20


2. ISOLATE SB GPIO18
3. LAN OGPIO SB GPIO14

0.3

EC_BEEP

34

Add R2076

0.3

G-sensor LED control by SB

41

Delete R668

0.3

Modify FPR connector pin assignment

38

Modify JP41 pin assignment

0.3

Modify Audio

34
36
37
42

<2007.11.05>

<2007.11.06>

EMI request

<2007.11.07>

<2007.11.08>

<2007.11.09>

1.
2.
3.
4.
5.
6.
7.
8.

Add C2108,C2109,R2080,R2081
Add R2082,R2083
Change C1008,C1009 to 1UF
Delete C976,C977
Delete R515,R516,C916
Change C982,C980,C984 from 5900p to 0.039u
Change C983,C992 from 1000p to 100p
Add EC_MUTE# to sub-woofer shutdown pin and R2084

0.3

nVIDIA suggestion

20

1. Delete strap pin


2. Change R1020, R1015, R1010 to 475 ohm
3. Swap THERMDN and THERMDP

0.3

EMI request

17

Add C2100,C2111

0.3

Audio

Change C970,C971 to 22uF, add C2112, change D38 to dual type

0.3

nVIDIA suggestion

Change HDMI DDC to I2CD


R387,R388,R415,R422,R427 -- install
Change R415 to 10 ohm and no install
Delete R99, Change +IFPC_PLLVDD to +PCIE

0.3

0.3

0.3

36
37
19
20

JMicron suggestion

33

Do not install R2030


Add D86 for card reader wake up
Add SB GPIO22 for wake up event

HP request

Add EMC1403 for Qaud core

<2007.11.12>

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

56

of

61

Item

<2007.12.12>

Fixed Issue

Reason for change

PAGE

Modify List

M.B. Ver.

MV DG for VDDC_QDAC

10

Chagne VCCD_QDAC to +1.5VS

0.4

WLAN issue

32

Change XMIT_OFF#,WL_LED# and component to WLAN connector

0.4

PCIE issue

28

Swap GLAN and NewCard PCIE port

0.4

Modify CardReader LED

33

Use 2N7002 to control LED

0.4

0.4

KBC

40

Change SMB_EC_DA1,SMB_EC_CK1 power rail from +5VL to +3VL


Add C2118 for KBC pin124
Chagne EC_THERM power rail to +3VS

WL_BLUE_LED# issue

41

Add R2089 pull up for WL_BLUE_LED#

0.4

Power sequence

43

Add R2099,R2100,C2119 and Q89 change to dual type

0.4

DIM_LED

43

Delete Q97B,R211

0.4

EC_PME#

40

Change EC_PME# power rail to +3VALW

0.4

10

WLAN issue

28

Add R2101

0.4

11

Change TP power rail

41

Change TP power rail to +5VALW

0.4

12

G-sensor

41

G-sensor -- R2031 change to 470 ohm and pull up to +3VS

0.4

13

For Dock present

42

R1570 change to 22 ohm,R61 change to 2K ohm

0.4

14

Clock generator

15

Add series R2102,R2103 for 27M_SSC and 27M_CLK

0.4

15

HDCP ROM

19

R951 pull up,R959 no install

0.4

C272,C273,C2120 -- 470pF
C828,C798 -- 10pF
C2111 -- 220pF
Add D87

16

EMI request

17

17

Modify BT/FPR circuit

38

<2007.12.24>

HP request

<2007.12.25>

For ENE cap board EMI issue

<2007.12.26>

For Mini PCI

36
37
40
32
35

0.4

0.4

Change value

0.4

Add R and C

0.4

Add R2118,R2119,R2120

0.4

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

57

of

61

Item

<2008.01.25>

Fixed Issue

Reason for change

PAGE

G-sensor power rail

39

G-sensor SM BUS

Modify List

M.B. Ver.

Swap +3VS_ACL and +3VS_ACL_IO

0.5

Change G-sensor SM BUS to CLK SM BUS -- +3VS power rail

40

KBC pin 97 connect to power


Change R543 to 33 ohm
Add R2121 33 ohm

0.5

Cap. board INT issue

41

Delete R640 for Cap. board issue

0.5

Current issue

32
32
35

Change R464 and R1582 to 0805


R466,R468 change to 0805
R469,R1583 change to 0805

0.5

KBC EEprom issue

39

Do not install KBC EE prom

0.5

Frequency Response (Band-Edge)

36

Change C2103,C2104,C1346,C1347 to 150uF

0.5

D3E function

33

Do not install R2087 for Intel platform

0.5

Change BT connector(JP30)

38

Change BT connector from 88231-0800 to 87213-0800(SP02000CZ00)

0.5

Audio circuit

37

Change C982 from 0.039u to 5900pF

0.5

10

BKOFF# issue

39

Add R2122 on BKOFF# and no-stuff

0.5

11

TP LED

41

Add PJP6 and no-install Q29,Q31,R645

0.5

12

RTC timing

27

Change C548,C549 to 18PF

0.5

13

Change LED control signal

33

Add R2123 and R2124


No-install R1548,Q53,R2097

0.5

14

Quad Core CPU

4,6

R2125,R2126,R2127,C2125,R2128-R2134

0.5

ESD

36
41
38

Add D31 for TP --- OK


Change D33 to PRTR5V0U2X_SOT143-4 and install -- Check P/N
Add C957,C958,C959,C960 -- 180pF

0.5

KBC PIN97 -- AC in LED issue


For DOCK_SLP_BTN#
For Mute_LED

15
B

<2008.03.16>

16

PM_PWROK timing

28

Add D90 and R2135 for PM_PWROK timing

0.5

17

ENE cap. board

41

Change JP38 to 12pin


Change R641,R652 to 800 ohm bead

0.5

18

Reduce 0 ohm

Delete R622, R404, R407, R429, R438, R667, R970

0.5

19

change WLAN LED circuit

41

Need to change R2098 value, Add D91, R2136

0.5

20

ESB LDO CIRCUIT

41

Add U79,R2139,C2126,C2127,PJP7 for ENE cap. board power

0.5

nVIDIA suggestion

19

Change R951 and R953 to 2.2K ohm

0.6

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

58

of

61

Item

<2008.04.06>

Fixed Issue

Reason for change

PAGE

Modify List

M.B. Ver.

Docking headphone issue

36

Change Q147 to dual tpye and add Q203

1.0

For 2nd source thermal sensor

Add resistor R2140on pin6

1.0

EMI request

16

Add 4.7pF for C317,C318,C319

1.0

LED brightness

41

R705 : from 150ohm to 1.8K ohm


R1534 : from 470ohm to 750ohm
D29 : from SC500005400 to SC500006R00

1.0

HP request

41

Remove R2059 for KB backlight

1.0

Clock generator -- CLKREQ#

Add R2141-R2145 for CLKREQ#

1.0

ESD issue

38

Delete R582

1.0

Cap board auto trigger issue

40

R618.1 connect to +3VL

1.0

Intel Check list

10

Remove C2129 for ENE cap. board

40

Remove C2129

1.0

Solve VGA thermal issue

20

Reserve R2146 and R2147

1.A

Debug card 2F issue

28

Add C2130

40

Add R2148

<2008.08.01>

No-stuff R59,R67,R65,R77,R66

1.0

1.A

2006/02/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/03/10

Deciphered Date

Title

SCHEMATICS, MB A4082

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

59

of

61

2007/11/24

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2007/11/24

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS, MB A4082
Rev
G

401540

Date:

Thursday, January 08, 2009

Sheet

60

of

61

50mA

50mA
177mA

ICH9

25mA

Finger printer

PC Camera
+3VS_DVDD
ALC268

300mA

LAN

60mA

0.3A

AC

INVPWR_B+

1.7A
2A

+3VALW

MDC 1.5
New card

+3VALW_EC

10mA

VIN

1A

+3VAUX_BT

20mA

LVDS CON

35mA

278mA

SPI ROM

5.89A

5.39A

+3VS

1.5A

ICH9
+LCDVDD

LVDS CON

B++
250mA

+3VS_CK505

0.58A

+5VALW

35mA

1.3A

+5VS

+VDDA
IDT 9271B7

B+
10mA

1.8A

+5VAMP
ODD

3.7 X 3=11.1V

DC

3.7A

700mA

MCH

SATA

BATT
B+++

12.11A

+1.8V

8 A

DDR2

50mA

800Mhz

4G x2

+0.9V
1.17A

1.05V_B+

1.26A

+VCCP

2.3A

ICH9
MCH
CPU

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/26

Deciphered Date

2007/09/26

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATICS, MB A4082
Rev
G

401540

Date:

Sheet

Thursday, January 08, 2009


1

61

of

61

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