Chapter 4: 4.

2 A and B
4.2) Let's extend the SRC instruction set by adding the instruction "swap ra, rb". Let's say it uses opcode 7. Its function is exactly what you expect.
a) give me the abstract RTN. It should start with "swap (:= op=7)"
b) Now, look at the data path, and write the concrete RTN. I want to see steps with the T#'s marked, but
you can show the abbreviated fetch portion.
HINT: The ALU can hold a value straight off the bus! Just as it's legal to clock a value on the bus into A,
the bus value can also be stored directly into C.
You can do this! Look at the Concrete RTN for SRC's Add (slide 18) to see how to move data in-to/outof registers.

Answer:
a) swap(:=op=7) (R[ra]R[rb] : R[rb]R[ra]):

b) Concrete RTN:

STEP
T0
T1
T2
T3
T4
T5
T6

RTN
MAPC: CPC+4;
MDM[MA] : PCC;
IRMD;
MDR[ra];
CR[rb];
R[ra]C;
R[rb]MD;

Note: This homework only produced two results: Three people got it right. Everyone else made exactly
the same mistake: instead of dumping one of the registers to MD, they put it in A. The problem, then,
becomes getting the value out of A. Register A cannot write a value onto the bus; it would have to go
through C. This would mean having to put a known zero value on the bus, and setting the accumulator to
add (so that C = A + 0 C = A) to get As data into C. Only then could we bring that value to the other
register.
Looking at any of the block diagrams for the data path should have revealed this limitation, and we
discussed this when we mentioned the limits of the 1-Bus architecture. These limitations came up two or
three times. This error was worth 1.5 points.