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A20
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Datasheet

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Revision 1.1
March 21, 2013

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

A20

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Declaration
THIS A20 DATASHEET IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER
TECHNOLOGY (ALLWINNER). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN
APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.

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THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE.


ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND
LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE
THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR
OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF ALLWINNER. THIS DATASHEET NEITHER
STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS FOR ANY PARTICULAR APPLICATION.

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THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD PARTY
LICENCES. ALLWINNER SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS COVERED UNDER ANY REQUIRED
THIRD PARTY LICENCE.

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

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Allwinner Technology Co., Ltd.

4th Floor, B6 Building, NO.1, Software Road,


Zhuhai, Guangdong Province, China

Contact Us: service@allwinnertech.com


Home Page: www.allwinnertech.com

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 2

A20

Revision

Date

Author

1.0

Feb 27, 2013

Allwinner

1.1

March 21, 2013

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Revision History
Description

Initial version

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Revize the logo

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 3

A20

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Table of Contents
CHAPTER 1 OVERVIEW.................  4

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CHAPTER 2FEATURES................................  5

CHAPTER 3 BLOCK DIAGRAM...................  10

CHAPTER 4 PIN DESCRIPTION.................  11

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4.1. PIN CHARACTERISTICS.................. 11


4.2. GPIO MULTIPLEXING FUNCTIONS................. 20
4.3. DETAILED PIN/SIGNAL DESCRIPTION..........  24

CHAPTER 5

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4.4. POWER SIGNAL DESCRIPTION.....................  29

ELECTRICAL CHARACTERISTICS....  31

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5.1. ABSOLUTE MAXIMUM RATINGS.............................................................................  31


5.2. RECOMMENDED OPERATING CONDITIONS.......................................................  31
5.3. DC ELECTRICAL CHARACTERISTICS..................................................................................  32
5.4. OSCILLATOR ELECTRICAL CHARACTERISTICS......................................................................  32

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5.4.1. 24MHZ OSCILLATOR CHARACTERISTICS  32


5.4.2. 32768HZ OSCILLATOR CHARACTERISTICS 33
5.5. POWER UP/DOWN SEQUENCE33

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CHAPTER 6 PIN ASSIGNMENT35


6.1. PIN MAP35

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6.2. PACKAGE DIMENSION36

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 4

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Overview

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OVERVIEW

Allwinner A20 processor is a dual-core ARM Cortex-A7 mobile application solution designed for tablet and smart
TV applications.

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A20 processor is based on a dual-core ARM Cortex-A7 CPU architecture, which is the most energy efficient application processor from ARM so far and incorporates all the features of Cortex-A15. It also integrates the powerful
ARM Mali400 MP2 GPU, delivering a reliable system performance as well as good game compatibility. Besides,
A20 supports 2160p video decoding and H.264 HP 1080p video encoding.

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Additionally, A20 processor features a wide range of interfaces and connectivity, including 4-CH CVBS in, 4-CH
CVBS out, HDMI with HDCP, VGA, LVDS/RGB LCD, SATA, USB, and GMAC, etc. More importantly, A20 processor is pin-compatible with its predecessor A10, which greatly simplifies the product design process and makes the
upgrade of a design much easier.

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 5

Feature

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FEATURE

Dual-Core CPU

SDRAM

Support
DDR3/DDR3L/DDR2

Dual Cortex-A7

Support
32-bit bus width

ARMv7
ISA standard ARM instruction set

Support
2GB address space

Thumb-2

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Jazeller
RCT

NAND Flash

NEON
Advanced SIMD

Comply
to ONFI 2.3 and Toggle 1.0

VFPv4
floating point

Support
64 bits ECC per 512 bytes or 1024 bytes

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Hardware
virtualization support

Large
Physical Address Extensions(LPAE)

Support
8bits data bus width

JTAG
debug

Support
1.8V/3.3V signal voltage

One
general timer for individual CPU

Support
up to 8 CE and 2 RB

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32KB
Instruction and 32KB Data L1 Cache for

individual CPU

Support
1K/2K/4K/8K/16K page size

Support
system boot from NAND flash

Support
SLC/MLC NAND and EF-NAND

Support
SDR/DDR NAND interface

Graphic Engine
3D

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Mali400
MP2 GPU

Support
OpenGL ES 2.0 / OpenVG 1.1 standard

2D

SD/MMC Interface
Comply
with eMMC standard specification V4.3

Comply
with SD physical layer specification V3.0

Comply
with SDIO card specification V2.0

Support
90 /180 /270 rotation

Support
1/4/8 bits bus width

Support
mirror/ alpha (plane and pixel alpha) /

color key

Support
HS/DS/SDR12/SDR25 bus mode

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Support
BLT and ROP2/3/4

Format
conversion: ARGB 8888/4444/1555,

RGB565, MONO 1/2/4/8bpp, Palette 1/2/4/8bpp

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(input only), YUV 444/422/420

Support
four independent SD/MMC/SDIO

controllers
Support
SDSC/SDHC/SDXC/MMC/ RS-MMC card

Support
eMMC/iNand Flash

Memory

Internal BROM

Support
system boot from NAND Flash, SPI Nor

Flash (SPI0), SD Card/TF card (SDC0/2)


Support
system code download through USB

OTG (USB0)

A20 Datasheet (Revision 1.1)

Support
eMMC mandatory and alternative boot

operations

Support
1GB/2GB/4GB/8GB/16GB/32GB/64GB

/128GB SD/MMC card


Support
SDIO interrupt detection

Support
descriptor-based internal DMA controller

for efficient scatter and gather operations

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 6

Feature

System Resources

Alpha
blending

Thumb
generation

Two
33-bit AVS counters

Watchdog
to generate reset signal or interrupt

Real
time counter for second, minute, hour, day,

month, and year

4x2
scaling ratio from 1/16 to 64 arbitrary non
integer ratio

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6
timers: clock source can be switched over
24M/32K for all timers, and external signals can be
used as clock source for Timer4/5

Display Engine

Four moveable and size-adjustable layers, each


layer size up to 8192x8192 pixels
Ultra-Scaling engine

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Timer

8-tap
scale filter in horizontal and 4 tap in vertical

4
channels
Clock
source is fixed to AHB, and the pre-scale

ranges from 1 to 16
56-bit
counter that can be separated to 24-bit high

register and 32-bit low register

Source
image size from 8x4 to 8192x8192

resolution and destination image size from 8x4 to


8192x8192 resolution
Support multiple image input formats
mono
1/2/4/8 bpp

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High Speed Timer

palette
1/2/4/8 bpp

6/24/32
bpp color

16
channels
Support
data width of 8/32 bits

Output color correction: luminance/hue/saturation,


etc

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Support
linear and IO address modes

YUV444/420/422/411

Support alpha blending/color key/gamma/harware


cursor/sprite

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DMA

Support de-interlace

CCU

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8PLLs,
a main 24MHz oscillator, an on-chip RC

oscillator and a 32768Hz oscillator (optional)


GIC

Support
16 SGIs, 16 PPIs, and 128 SPIs

Support
ARM architecture security extensions

Video enhancement: lum peaking/DCTi/black and


white level extension
3D input/output format conversion and display

Video Output
HDMI 1.4 transmitter with HDCP
LVDS/Sync RGB/CPU LCD interface up to
1920x1200 resolution

Support
uniprocessor and multiprocessor

environments

Support 4-channel CVBS, or 2-channel S-video, or


1-channel YPbPr/VGA (YPbPr/VGA up to 1080p)

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Support
ARM architecture virtualization extensions

Video Engine (Phoenix 3.0)


Video Decoding

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Support
picture size up to 3840x2160

Support
decoding speed up to 1080p@60fps

Supported
formats: Mpeg1/2, Mpeg4 SP/ASP

GMC, H.263 including Sorenson Spark, H.264 BP/


MP/HP, VP6/8, AVS jizun, Jpeg/Mjpeg, etc.

Video Encoding

Video Input
Support TV decoder: 4-ch analog CVBS or 1-ch
YPbPr(480i/576i/480p/576p) signal input
Dual CMOS sensor parallel interfaces that support
YUV format only
CSI0
up to 1080p@30fps

CSI1
up to 720p@30fps

Support BT656 interface

H.264
HP up to 1080p@30fps

Jpeg
baseline: picture size up to 4080x4080

A20 Datasheet (Revision 1.1)

Support two-channel independent display

Support 24-bit YUV444/RGB interface

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 7

Feature
GMAC

Analog Audio Output

Comply
with the IEEE 802.3-2002 standard

Stereo audio DAC


Up
to 100dB SNR during DAC playback

Support
10/100/1000Mbps data transfer rates

RGMII interface to communicate with an external


Gigabit PHY

Support
8KHz~192KHz DAC sample rate

One low-noise analog microphone bias


Dedicated headphone outputs
Output
mixer for LINEINL/R, FMINL/R, MIC1/2

and Stereo DAC output


ADC
record mixer for LINEINL/R, FMINL/R,

MIC1/2 and Stereo DAC output

Analog Audio Input

One
I2S compliant audio interface, supporting

8-channel and 2-channel input


One
PCM, supporting linear sample(8-bit or 16
bit), 8-bit u-law and A-law companded sample

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Two
microphone inputs

Transport Stream Controller

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Differential
or stereo line-in input

Support
both SPI and SSI

Stereo audio ADC

Speed
up to 150Mbps for both SPI and SSI

96dBA
SNR

RTP

Support
32-channel PID filter

Support
hardware PCR packet detect

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Support
8KHz ~ 48KHz ADC sample rate

Open-Drain TWI

12-bit SAR ADC

Up
to 5 TWIs compliant with TWI protocol

Dual touch detection

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Sampling frequency up to 2MHz

USB2.0 OTG

Digital Audio In/Out

One
AC97 audio codec, supporting 2-channel and

6-channel audio data output

Support four analog audio inputs

Connectivity

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Support
10/100Mbps MII PHY interface

Two mixers to meet different requirements

Stereo
FM-in input

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Programmable
frame length to support Standard

or Jumbo Ethernet frames with size up to 16KB

Stereo capless headphone drivers

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Support
High-Speed (HS, 480-Mbps), Full
Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5Mbps) in Host mode
Support
High-Speed (HS, 480-Mbps), Full
Speed (FS, 12-Mbps) in Device mode

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Support
up to 5 user-configurable endpoints for

Bulk , Isochronous, Control and Interrupt

USB EHCI/OHCI

Two
EHCI/OHCI-compliant hosts

EMAC

Smart Card Reader


One
smart card reader controller supporting ISO/

IEC 7816-3 and EMV2000 specifications


Support
synchronous and any other non-ISO 7816

and non-EMV cards


SPI
Master/Slave
configurable

Up
to 4 independent SPI controllers: SPI0 with
one CS signal for system boot, SPI1/2/3 each with
two CS signals
UART
Up
to 8 UART controllers:UART0 with two wires
for debug tools, UART1 with 8 wires, UART2/3
each with 4 wires, and others each with 2 wires

Support
10/100Mbps MII data transfer rate

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 8

Feature

Two
PS2 compliant to IBM PS2 and AT
compatible keyboard and mouse interface
Dual-role
controller: a PS2 host or a PS2 device

IR

Security System
Support
AES, DES, 3DES, SHA-1, MD5

S
upport ECB/CBC/CNT modes for AES/
DES/3DES
128-bit,
192-bit and 256-bit key size for AES

160-bit
hardware PRNG with 192-bit seed

Security JTAG

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Two
IR controllers supporting CIR, MIR and FIR

modes

Security System

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PS2

SATA

Power Management

One
SATA Host controller

Flexible PLL clock generator and OSC for 32KHz

Support
SATA 1.5Gb/s and SATA 3.0Gb/s

Flexible clock gate

Comply
with SATA spec 2.6

Support DVFS for CPU frequency and voltage adjustment

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Support
external SATA(eSATA)

Support standby mode (only DDR+RTC-Domain


power exist)

One
CAN bus controller

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CAN
Support
the CAN2.0 A/B protocol specification

Programmable
data rate up to 1Mbps

FBGA 441 balls,0.80mm ball pitch, 19x19x1.4mm

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Keypad

Package

One
keypad matrix interface up to 8 rows and 8

colums
Interrupt
for key press or key release

LRADC
6-bit
resolution

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Internal
debouncing filter to prevent switching

noises

PWM

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Voltage
input range between 0V to 2V

2
PWM outputs

Support
cycle mode and pulse mode

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The
pre-scale is from 1 to 64

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 9

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BLOCK DIAGRAM

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Block Diagram

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 10

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PIN DESCRIPTION

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Pin Description

4.1. PIN CHARACTERISTICS

Following table describes the A20 pin characteristics from seven aspects: BALL#, Pin Name, Default
Function1, Type2, Reset State3, Default Pull Up/Down4, and Buffer Strength5.
Default
Function

SDQ0
SDQ1

DRAM
DRAM

AC8

SDQ2

DRAM

AB5
AB7
AB8
AB4
AC3
AA1
AC1
Y1
AB2
AC2
W2
AB3
Y2
T2
N2
U2
P1
T1
U1
N1

SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22

DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM

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Note:

Reset State

Default Pull
Up/Down

Buffer
Strength (mA)

I/O
I/O

Z
Z

I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

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SDRAM
AC7
AC4

Type

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Pin Name

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BALL#

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1 Default function defines the default function of each pin, especially for pins with multiplexing functions;

2 There are five pin types here: O for output, I for input, I/O for input/output, A for analog,P for power and G for
ground;
3 Reset state defines the state of the terminal at reset: Z for high-impedance.
4 Default Pull up/down defines the presence of an internal pull up or pull down resistor. Unless otherwise specified, the pin is default to be floating, and can be configured as pull up or pull down;
5 Buffer strength defines the driver strength of the associated output buffer. It is tested in the condition that VCC=
3.3V, strength=MAX;

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 11

Pin Description

Z
Z
Z
Z
Z
Z
Z
Z
Z

I/O

DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM

I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

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inn

SDQS2
SDQS2B
SDQS3
SDQS3B
SDQM3
SCKB
SCK
SCK1
SCK1B
SCKE
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SBA0
SBA1
SBA2
SWE
SCAS
SRAS
SCS

rA

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
I/O
I/O
O
I/O
I/O
O
O

P2
K1
J2
G1
V2
V1
J4
J3
N3
W4
R4
U4
M4
Y4
N4
V4
M3
AA3
P4
L3
W3
P3
Y3
R3
AA4
K3
L4
K4
T3
U3
T4
V3

Fo

Z
Z
Z
Z
Z
Z
Z

DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM

Function

R1

A20 Datasheet (Revision 1.1)

Buffer
Strength (mA)

Reset State

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SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SVREF
SDQS0
SDQS0B
SDQM0
SDQS1
SDQS1B
SDQM1
SDQM2

Default Pull
Up/Down

Type

hO

M2
J1
L1
H1
K2
L2
G2
M1
H2
H3/H4/Y5/AA8
AB6
AC5
AC6
AB1
AA2
W1
R2

Default

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Pin Name

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BALL#

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 12

Pin Description

BALL#

Pin Name

AA5
AA7
AA6
N8
P8
R8
M8/N9/P9
G5/H5/L5/W5/

SODT
SZQ
SRST
SADBG
SDDBG0
SADBG1
VDD-DLL

W6/W7/M5/R5/

Default Pull
Up/Down

Buffer
Strength (mA)

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
-

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
-

Reset State

DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
POWER

O
A
O
A
A
A
P

Z
Z
Z
Z
Z
Z
-

VCC-DRAM

POWER

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
VCC-PA

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
POWER

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P

inn

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Function

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Type

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T5/Y6
GPIO A
D5
E5
D6
E6
D7
E7
D8
E8
D9
E9
D10
E10
D11
E11
D12
E12
D13
C13
H10/J10
GPIO B
A15
B15
A14
B14
A13
B13
A12
B12
A11
C12
C11
C10
C9

Default

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL

20
20
20
20
20
20
20
20
20
20
20
20
20

B11

PB13

GPIO

I/O

NO PULL

20

A10
B10
A9
B9

PB14
PB15
PB16
PB17

GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O

Z
Z
Z
Z

NO PULL
NO PULL
NO PULL
NO PULL

20
20
20
20

Fo

rA

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 13

Pin Description

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O

Z
Z
Z
Z
Z
Z

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
POWER

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16

Fo
A20 Datasheet (Revision 1.1)

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Buffer
Strength (mA)

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL

20
20
20
20
20
20

hO
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-

NO PULL
NO PULL
NO PULL
PULL UP
PULL UP
NO PULL
PULL UP
PULL UP
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
PULL DOWN
PULL UP
PULL UP
NO PULL
NO PULL
NO PULL
NO PULL
PULL UP
NO PULL
-

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
-

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

ec

Function

Default Pull
Up/Down

nly

Reset State

ert

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
VCC-PC

Type

inn

PB18
PB19
PB20
PB21
PB22
PB23

Default

rA

A8
B8
C8
C7
A7
B7
GPIO C
M23
M22
L23
L22
K23
K22
J23
J22
H23
H22
G23
G22
H21
H20
G21
G20
M21
F23
F22
L21
K21
J21
J20
G19
F21
H19/J19
GPIO D
AB15
AC15
AB14
AC14
AB13
AC13
AB12
AC12
AB11
AC11
Y15
AA15
Y14
AA14
Y13
AA13
Y12

Pin Name

llw

BALL#

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 14

Pin Description

PF0
PF1
PF2
PF3
PF4
PF5
VCC-PF

Buffer
Strength (mA)

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL

20
20
20
20
20
20
20
20
20
20
20

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
-

20
20
20
20
20
20
20
20
20
20
20
20
-

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
POWER

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P

hO

ec

Function

nly

Reset State

ert

PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
VCC-PE

Default Pull
Up/Down

Type

inn

PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27

Default

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
POWER

I/O
I/O
I/O
I/O
I/O
I/O
P

Z
Z
Z
Z
Z
Z
-

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
-

20
20
20
20
20
20
-

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
VCC-PG

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
POWER

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
-

20
20
20
20
20
20
20
20
20
20
20
20
-

PH0
PH1
PH2

GPIO
GPIO
GPIO

I/O
I/O
I/O

Z
Z
Z

NO PULL
NO PULL
NO PULL

20
20
20

Fo

rA

AA12
Y11
AA11
Y10
AA10
AB10
AC10
Y9
AA9
AB9
AC9
GPIO E
E23
E22
D23
D22
C23
C22
B23
B22
A23
A22
B21
A21
F19
GPIO F
M20
M19
L20
L19
K20
K19
N19
GPIO G
F20
E21
E20
D21
D20
C21
E19
C20
D19
C19
D18
C18
E18
GPIO H
A6
B6
C6

Pin Name

llw

BALL#

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 15

Pin Description

rA

Fo
A20 Datasheet (Revision 1.1)

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

Default Pull
Up/Down

Buffer
Strength (mA)

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

nly

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

PULL UP

llw

GPIO I
A20
PI0
B20
PI1
A19
PI2
B19
PI3
A18
PI4
B18
PI5
A17
PI6
B17
PI7
A16
PI8
B16
PI9
C17
PI10
D17
PI11
C16
PI12
D16
PI13
C15
PI14
D15
PI15
E17
PI16
E16
PI17
E15
PI18
D14
PI19
E14
PI20
E13
PI21
SYSTEM CONTROL
W8
BOOTSEL

Function

Reset State

hO

PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PH16
PH17
PH18
PH19
PH20
PH21
PH22
PH23
PH24
PH25
PH26
PH27

Type

ec

A5
B5
C5
A4
B4
C4
D4
A3
B3
C3
A2
B2
A1
B1
C1
C2
D1
D2
D3
E1
E2
E3
E4
F3
F4

Default

ert

Pin Name

inn

BALL#

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 16

Pin Description

Pin Name

T10
H16
F5
C14

JTAGSEL
TEST
NMI#
RESET#

N20
N21
P20
P21
L16/L15
K16
R20
R21
SATA
T20
T21
U20
U21
V21
M15/M16
N15/N16
P19
R19
TP
Y22
AA22
Y23
AA23
AUDIO CODEC
AC23
AC22
Y21
Y20
AA21
AC21
AC20
W20
V20
T19
W21
AB21
AB20
U19
W19
Y19
V19
AA19
AA20
AC19
AB19

Default Pull
Up/Down

Buffer
Strength (mA)

PULL UP
PULL DOWN
NO PULL
NO PULL

Reset State

I
I
I
I

H
L
Z
Z

DM0
DP0
DM1
DP1
VCC-USB
VDD-USB
DM2
DP2

A
A
A
A
P
P
A
A

SATA-TXP
SATA-TXM
SATA-RXM
SATA-RXP
REXT-SATA
VDD-SATA
VDD25-SATA
SATA-CLKM
SATA-CLKP

Fo
A20 Datasheet (Revision 1.1)

hO

ert

A
A
A
A

A
A
A
A
P
A
A
A
A
P
A
A
A
G
A
A
G
A
A
P
P

llw

MICOUTN
MICOUTP
FMINR
FMINL
VMIC
MICIN2
MICIN1
VRA1
VRA2
AVCC
VRP
LINEINR
LINEINL
AGND
HPR
HPL
GND-HP
HPCOM
HPCOMFB
HPBP
VCCHP

A
A
A
A
A
P
P
A
A

inn

TPX1
TPX2
TPY1
TPY2

Function

nly

Type

rA

USB

Default

ec

BALL#

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 17

Pin Description

Function

L9/K9/K10/K15/

Reset State

A
A

TVOUT0
TVOUT1
TVOUT2
TVOUT3
VCC-TVOUT

A
A
A
A
P

TVIN0
TVIN1
TVIN2
TVIN3
VCC-TVIN
VCC25-TVIN
VRP-TVIN
VRN-TVIN

A
A
A
A
P
P
A
A

HTX0P
HTX0N
HTX1P
HTX1N
HTX2P
HTX2N
HTXCP
HTXCN
VCC-HDMI
HSCL
HSDA
HHPD
HCEC
HVREG1

Default Pull
Up/Down

Buffer
Strength (mA)

hO

LRADC0
LRADC1

ert

ec

A
A
P
A
A
A
P
A
A

VDD-CPU

VDD-SYS

inn

A
A
A
A
A
A
A
A
P
I/O
I/O
I
I/O
A

X32KI
X32KO
VDD-RTC
X24MI
X24MO
PLLVREG
VCC-PLL
PLLTEST
PLLDV

Fo
H12/H13/H14
T8/R9/R10/L8/

Type

nly

Default

rA

LRADC
AB23
AB22
TV-OUT
AC16
AB16
AC17
AB17
W15
TV-IN
AC18
AB18
AA17
Y17
W16
W17
AA16
Y16
HDMI
V23
V22
U23
U22
T23
T22
W23
W22
T13
R23
R22
P22
P23
T14
CLOCK
F1
F2
K8
N23
N22
R15
P16
T15
T16
POWER
J12/J13/H11/

Pin Name

llw

BALL#

J15/J16

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 18

Pin Description

Pin Name

J5/K5/N5/P5/U5/

Default

Type

Function

Reset State

V5/Y7/Y8/G3/G4/
L10/L11/L12/L13/
L14/K11/K12/
M10/M11/M12/
M13/M14/N10/
GND

VCC

VCC-LVDS
NC

N14/P10/P11/
P12/P13/P14/
P15/R11/R12/
W9/W10/W11/

VDDQE

Buffer
Strength (mA)

P
-

Fo

rA

llw

inn

H15
W12/W13/W14
R14/R16
EFUSE
T9

ert

V19/W18/Y18/
AA18
H8/H9/J8/J9/J14/

ec

R13/T11/T12/

hO

K13/K14J11/M9/

N11/N12/N13/

Default Pull
Up/Down

nly

BALL#

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 19

4.2. GPIO MULTIPLEXING FUNCTIONS

nly

Pin Description

Following table provides a description of the GPIO multiplexing functions of A20.


Default
IO Type
Function

Default
Default IO
Pull-up/
State
down

Multi2

Multi3

PA0

GPIO

I/O

ERXD3

SPI1-CS0

PA1

GPIO

I/O

ERXD2

SPI1-CLK

PA2
PA3
PA4
PA5
PA6
PA7
PA8

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O

I
I
I
I
I
I
I

Z
Z
Z
Z
Z
Z
Z

ERXD1
ERXD0
ETXD3
ETXD2
ETXD1
ETXD0
ERXCK

SPI1-MOSI
SPI1-MISO
SPI1-CS1
SPI3-CS0
SPI3-CLK
SPI3-MOSI
SPI3-MISO

PA9

GPIO

I/O

ERXERR

PA10

GPIO

I/O

ERXDV

PA11

GPIO

I/O

PA12

GPIO

I/O

PA13

GPIO

I/O

PA14

GPIO

I/O

PA15

GPIO

I/O

PA16

GPIO

I/O

PA17

GPIO

I/O

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

UART2RTS
UART2CTS
UART2-TX
UART2-RX
-

Multi5

Multi6

Multi7

GRXD3

GRXD2

ec

GRXD1
GRXD0
GTXD3
GTXD2
GTXD1
GTXD0
GRXCK
GNULL/ERXSPI3-CS1
ERR
GRXCTL/
UART1-TX
RXDV
UART1-RX GMDC
UART1UART6-TX
GMDIO
RTS
UART1GTXCTL/
UART6-RX
CTS
ETXEN
UART1GNULL/
UART7-TX
DTR
ETXCK
UART1GTXCK/
UART7-RX
DSR
ECRS
UART1GCLKIN/
CAN-TX
DCD
ECOL
UART1GNULL/ETXCAN-RX
RING
ERR
AC97-MCLK AC97-BCLK AC97-SYNC AC97-DO
AC97-DI
JTAG-MS0
JTAG-CK0
JTAG-DO0
JTAG-DI0
-

ert
EMDC

EMDIO

inn

ETXEN

ETXCK

ECRS

ECOL

llw

ETXERR

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

TWI0-SCK
TWI0-SDA
PWM0
IR0-TX
IR0-RX
I2S-MCLK
I2S-BCLK
I2S-LRCK
I2S-DO0
I2S-DO1
I2S-DO2
I2S-DO3
I2S-DI
SPI2-CS1
SPI2-CS0
SPI2-CLK
SPI2-MOSI
SPI2-MISO
TWI1-SCK
TWI1-SDA
TWI2-SCK

rA

Fo
A20 Datasheet (Revision 1.1)

Multi4

hO

Port

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

I2S1-MCLK -

I2S1-BCLK I2S1-LRCK I2S1-DO

I2S1-DI

Page 20

Pin Description

Default
IO Type
Function

PB21
PB22
PB23
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

PC19

GPIO

I/O

PC20
PC21
PC22
PC23
PC24
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Multi2

Multi3

Multi4

Z
Z
Z
Z
Z
Z
Pull-Up
Pull-Up
Z
Pull-Up
Pull-Up
Z
Z
Z
Z
Z
Z
Z
Z
Pull-Down
Pull-Up
Pull-Up

TWI2-SDA
UART0-TX
UART0-RX
NWE#
NALE
NCLE
NCE1
NCE0
NRE#
NRB0
NRB1
NDQ0
NDQ1
NDQ2
NDQ3
NDQ4
NDQ5
NDQ6
NDQ7
NWP
NCE2
NCE3

IR1-TX
IR1-RX
SPI0-MOSI
SPI0-MISO
SPI0-CLK
SDC2-CMD
SDC2-CLK
SDC2-D0
SDC2-D1
SDC2-D2
SDC2-D3
-

NCE4

SPI2-CS0

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Z
Z
Z
Pull-Up
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

NCE5
NCE6
NCE7
NDQS
LCD0-D0
LCD0-D1
LCD0-D2
LCD0-D3
LCD0-D4
LCD0-D5
LCD0-D6
LCD0-D7
LCD0-D8
LCD0-D9
LCD0-D10
LCD0-D11
LCD0-D12
LCD0-D13
LCD0-D14
LCD0-D15
LCD0-D16
LCD0-D17
LCD0-D18
LCD0-D19
LCD0-D20
LCD0-D21
LCD0-D22
LCD0-D23
LCD0-CLK
LCD0-DE
LCD0-HSYNC
LCD0-VSYNC

SPI2-CLK
SPI2-MOSI
SPI2-MISO
SPI0-CS0
LVDS0-VP0
LVDS0-VN0
LVDS0-VP1
LVDS0-VN1
LVDS0-VP2
LVDS0-VN2
LVDS0-VPC
LVDS0-VNC
LVDS0-VP3
LVDS0-VN3
LVDS1-VP0
LVDS1-VN0
LVDS1-VP1
LVDS1-VN1
LVDS1-VP2
LVDS1-VN2
LVDS1-VPC
LVDS1-VNC
LVDS1-VP3
LVDS1-VN3
CSI1-MCLK
SMC-VPPEN
SMC-VPPPP
SMC-DET
SMC-VCCEN
SMC-RST
SMC-SLK
SMC-SDA

Multi6

Multi7

ec

hO

ert

inn

llw

rA

Fo
A20 Datasheet (Revision 1.1)

Multi5

nly

Default
Default IO
Pull-up/
State
down

Port

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 21

Pin Description

Default
Default IO
Pull-up/
State
down

Port

Default
IO Type
Function

PE0
PE1
PE2
PE3

GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O

I
I
I
I

PE4

GPIO

I/O

PE5
PE6
PE7
PE8
PE9
PE10
PE11
PF0
PF1
PF2
PF3
PF4
PF5
PG0
PG1
PG2
PG3
PG4

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Multi3

Multi4

Z
Z
Z
Z

TS0-CLK
TS0-ERR
TS0-SYNC
TS0-DVLD

CSI0-PCLK
CSI0-MCLK
CSI0-HSYNC
CSI0-VSYNC

TS0-D0

CSI0-D0

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

TS0-D1
TS0-D2
TS0-D3
TS0-D4
TS0-D5
TS0-D6
TS0-D7
SDC0-D1
SDC0-D0
SDC0-CLK
SDC0-CMD
SDC0-D3
SDC0-D2
TS1-CLK
TS1-ERR
TS1-SYNC
TS1-DVLD
TS1-D0

CSI0-D1
CSI0-D2
CSI0-D3
CSI0-D4
CSI0-D5
CSI0-D6
CSI0-D7
CSI1-PCLK
CSI1-MLCK
CSI1-HSYNC
CSI1-VSYNC
CSI1-D0

JTAG-MS1
JTAG-DI1
UART0-TX
JTAG-DO1
UART0-RX
JTAG-CK1
SDC1-CMD
SDC1-CLK
SDC1-D0
SDC1-D1
SDC1-D2

I/O

I/O
I/O

I
I

Z
Z

PG8

GPIO

I/O

PG9

GPIO

I/O

PG10
PG11
PH0
PH1

GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O

I
I
I
I

PH2

GPIO

I/O

PH3

GPIO

I/O

PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PH16
PH17
PH18
PH19

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Multi7

CSI0-D8

TS1-D1

CSI1-D1

SDC1-D3

CSI0-D9

TS1-D2
TS1-D3

CSI1-D2
CSI1-D3

CSI0-D10
CSI0-D11

TS1-D4

CSI1-D4

CSI0-D12

TS1-D5

CSI1-D5

CSI0-D13

Z
Z
Z
Z

TS1-D6
TS1-D7
LCD1-D0
LCD1-D1

CSI1-D6
CSI1-D7
-

CSI0-D14
CSI0-D15
-

EINT0
EINT1

CSI1-D0
CSI1-D1

LCD1-D2

EINT2

CSI1-D2

LCD1-D3

EINT3

CSI1-D3

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

LCD1-D4
LCD1-D5
LCD1-D6
LCD1-D7
LCD1-D8
LCD1-D9
LCD1-D10
LCD1-D11
LCD1-D12
LCD1-D13
LCD1-D14
LCD1-D15
LCD1-D16
LCD1-D17
LCD1-D18
LCD1-D19

ERXD3
ERXD2
ERXD1
ERXD0
ETXD3
ETXD2
ETXD1
ETXD0
ERXCK
ERXERR

UART3-TX
UART3-RX
UART3RTS
UART3CTS
UART4-TX
UART4-RX
UART3-TX
UART3-RX
UART3RTS
UART3CTS
UART4-TX
UART4-RX
UART5-TX
UART5-RX
KP-IN0
KP-IN1
KP-IN2
KP-IN3
PS2-SCK1
PS2-SDA1
KP-IN4
KP-IN5
KP-IN6
KP-IN7
KP-OUT0
KP-OUT1

SMC-RST
SMC-VPPEN
SMC-VPPPP
SMC-DET
SMC-VCCEN
SMC-SLK
SMC-SDA

EINT4
EINT5
EINT6
EINT7
EINT8
EINT9
EINT10
EINT11
EINT12
EINT13
EINT14
EINT15
EINT16
EINT17
EINT18
EINT19

CSI1-D4
CSI1-D5
CSI1-D6
CSI1-D7
CSI1-D8
CSI1-D9
CSI1-D10
CSI1-D11
CSI1-D12
CSI1-D13
CSI1-D14
CSI1-D15
CSI1-D16
CSI1-D17
CSI1-D18
CSI1-D19

llw

rA

Fo
A20 Datasheet (Revision 1.1)

Multi6

hO

ec

ert

GPIO
GPIO
GPIO

inn

PG5
PG6
PG7

Multi5

nly

Multi2

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 22

Pin Description

Default
Default IO
Pull-up/
State
down

Port

Default
IO Type
Function

PH20
PH21
PH22
PH23
PH24
PH25

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O

I
I
I
I
I
I

PH26

GPIO

I/O

PH27

GPIO

PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

Multi3

Multi4

Z
Z
Z
Z
Z
Z

LCD1-D20
LCD1-D21
LCD1-D22
LCD1-D23
LCD1-CLK
LCD1-DE

ERXDV
EMDC
EMDIO
ETXEN
ETXCK
ECRS

CAN-TX
CAN-RX
KP-OUT2
KP-OUT3
KP-OUT4
KP-OUT5

SDC1-CMD
SDC1-CLK
SDC1-D0
SDC1-D1

EINT20
EINT21
-

LCD1-HSYNC ECOL

KP-OUT6

SDC1-D2

I/O

LCD1-VSYNC ETXERR

KP-OUT7

SDC1-D3

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I
I
I
I
I
I
I
I
I
I

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

PWM1
SDC3-CMD
SDC3-CLK
SDC3-D0
SDC3-D1
SDC3-D2
SDC3-D3

I/O

I/O

PI12

GPIO

I/O

PI13

GPIO

I/O

PI14
PI15
PI16
PI17
PI18
PI19
PI20
PI21

GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I
I
I
I
I
I
I
I

SPI0-CS0

UART5-TX

SPI0-CLK

UART5-RX

SPI0-MOSI

SPI0-MISO

SPI0-CS1
SPI1-CS1
SPI1-CS0
SPI1-CLK
SPI1-MOSI
SPI1-MISO
PS2-SCK0
PS2-SDA0

llw

Z
Z
Z
Z
Z
Z
Z
Z

Multi6

hO

ec

ert

GPIO
GPIO

TWI3-SCK
TWI3-SDA
TWI4-SCK
TWI4-SDA
-

CLK-OUTUART6-TX
A
CLK-OUTUART6-RX
B
PS2-SCK1
TCLKIN0
PS2-SDA1
TCLKIN1
UART2-RTS UART2-CTS UART2-TX
UART2-RX
UART7-TX
HSCL
UART7-RX
HSDA

inn

PI10
PI11

Multi5

Multi7

nly

Multi2

CSI1-D20
CSI1-D21
CSI1-D22
CSI1-D23
CSI1-PCLK
CSI1-FIELD
CSI1HSYNC
CSI1VSYNC
-

EINT22

EINT23

EINT24

EINT25

EINT26
EINT27
EINT28
EINT29
EINT30
EINT31
-

rA

4.3. DETAILED PIN/SIGNAL DESCRIPTION


DRAM
SDQ[31:0]
SVREF
SDQS[3:0]
SDQSB[3:0]
SDQM[3:0]
SCK
SCKB
SCK1
SCK1B

Description

Type

DRAM DQ[31:0]
DRAM Reference Input
DRAM Data Strobe DQS[3:0]
DRAM Data Strobe DQSB[3:0]
DRAM DQ Mask[3:0]
DRAM Clock
DRAM CKB
DRAM Clock
DRAM CKB

I/O
P
I/O
I/O
O
O
O
O
O

SCKE
SA[15:0]

DRAM Clock Enable


DRAM Data Address[15:0]

O
O

Fo

Pin/Signal

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 23

Pin Description

Pin/Signal

Type

hO

ec

inn

ert

Port A Bit[17:0]
Port A Power Supply
Port B Bit[23:0]
Port C Bit[23:0]
Port C Power Supply
Port D Bit[27:0]
Port E Bit[11:0]
Port E Power Supply
Port F Bit[5:0]
Port F Power Supply
Port G Bit[11:0]
Port G Power Supply
Port H Bit[27:0]
Port I Bit[21:0]

I/O
P
I/O
I/O
P
I/O
I/O
P
I/O
P
I/O
P
I/O
I/O

Boot Mode Select


JTAG Mode Select
Test Signal
Non-Maskable Interrupt
Reset Signal

I
I
I
I
I

External Interrupt

JTAG Data Output


JTAG Data Input
JTAG Mode Select
JTAG Clock Signal

O
I
I
I

PWM

Clock Input of 32768Hz Crystal


Clock Output of 32768Hz Crystal
RTC Power Supply
Clock Input of 24MHz Crystal
Clock Output of 24MHz Crystal
PLL Power
PLL Power
PLL Power
PLL Test Signal

A
A
P
A
A
P
P
P
A

llw

Fo
A20 Datasheet (Revision 1.1)

O
O
O
O
O
O
A
O
A
A
A
P
P

nly

Description

DRAM Bank Address[2:0]


DRAM Write Enable
DRAM Column Address Strobe
DRAM Row Address Strobe
DRAM Chip Select
DRAM ODT Control
DRAM ZQ Calibration
DRAM Reset
DRAM Analog Debug
DRAM Digital Debug
DRAM Analog Debug
DLL Power Supply
DRAM Power Supply

rA

SBA[2:0]
SWE
SCAS
SRAS
SCS
SODT
SZQ
SRST
SADBG
SDDBG0
SADBG1
VDD-DLL
VCC-DRAM
GPIO
PA[17:0]
VCC-PA
PB[23:0]
PC[24:0]
VCC-PC
PD[27:0]
PE[11:0]
VCC-PE
PF[5:0]
VCC-PF
PG[11:0]
VCC-PG
PH[27:0]
PI[21:0]
SYSTEM CONTROL
BOOTSEL
JTAGSEL
TEST
NMI#
RESET#
INTERRUPT
EINT[31:0]
JTAG
JTAG-DO[1:0]
JTAG-DI[1:0]
JTAG-MS[1:0]
JTAG-CK[1:0]
PWM
PWM[1:0]
CLOCK
X32KI
X32KO
VDD-RTC
X24MI
X24MO
PLLVREG
VCC-PLL
PLLDV
PLLTEST

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 24

Pin Description

Pin/Signal

Type

Description

Clock OUT A
Clock OUT B
Clock

I/O
I/O
I/O

LVDS Channel0 Data Positive Signal Output[3:0]


LVDS Channel0 Data Negative Signal Output[3:0]
LVDS Channel0 Clock Positive Output
LVDS Channel0 Clock Negative Output

A
A
A
A

LVDS1-VP[3:0]

LVDS Channel1 Data Positive Signal Output[3:0]

LVDS1-VN[3:0]
LVDS1-VPC
LVDS1-VNC
VCC- LVDS
HDMI
HTX0P
HTX0N
HTX1P
HTX1N
HTX2P
HTX2N
HTXCP
HTXCN
VCC-HDMI
HSCL
HSDA
HHPD
HCEC
TV-OUT
TVOUT[3:0]
VCC-TVOUT
CSI (x=[1:0])
CSI0-D[15:0]
CSI1-D[23:0]
CSIx-PCLK
CSIx-MCLK

LVDS Channel1 Data Negative Signal Output[3:0]


LVDS Channel1 Clock Positive Output
LVDS Channel1 Clock Negative Output
LVDS Power Supply

A
A
A
P

HDMI Data0 Positive


HDMI Data0 Negative
HDMI Data1 Positive
HDMI Data1 Negative
HDMI Data2 Positive
HDMI Data2 Negative
HDMI Clock Positive
HDMI Clock Negative
HDMI Power Supply
HDMI DDC Clock
HDMI DDC Data
HDMI Hot Plug Detection
HDMI CEC

A
A
A
A
A
A
A
A
P
I/O
I/O
I
I/O

TV-out Output[3:0]
TV-out Power Supply

A
P

CSI0 Data Bit[15:0]


CSI1 Data Bit[23:0]
CSI Pixel Clock
CSI Master Clock

I
I
I
O

Fo

ec

rA

llw

inn

ert

LCD Data Bit[23:0]


LCD Clock Signal
LCD Data Enable
LCD Horizontal SYNC
LCD Vertical SYNC

A20 Datasheet (Revision 1.1)

I/O
O
O
O
O
O
I
O
I/O

hO

NAND Flash Data Bit[7:0]


NAND Flash Chip Select[7:0]
NAND Flash Write Enable
NAND Flash Address Latch Enable
NAND Flash Command Latch Enable
NAND Flash Read Enable
NAND Flash Ready/Busy Bit
NAND Flash Write Protection
NAND Flash Data Strobe

nly

CLK-OUT-A
CLK-OUT-B
TCLKIN[1:0]
NAND FLASH
NDQ[7:0]
NCE[7:0]
NWE#
NALE
NCLE
NRE#
NRB[1:0]
NWP
NDQS
LCD (x=[1:0])
LCDx-D[23:0]
LCDx-CLK
LCDx-DE
LCDx-HSYNC
LCDx-VSYNC
LVDS (x=[1:0])
LVDS0-VP[3:0]
LVDS0-VN[3:0]
LVDS0-VPC
LVDS0-VNC

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

O
O
O
O
O

Page 25

Pin Description

Pin/Signal

Type

Description

I
I

nly

CSI Horizontal SYNC


CSI Vertical SYNC

A
P
P
A
A

hO

TV-in Input[3:0]
TV-in Power Supply
TV-in Power Supply
TV-in Reference
TV-in Reference
USB DM[2:0] Signal
USB DP[2:0] Signal
USB Power Supply
USB Power

ec

TP ADC Input
TP ADC Input

A
A
P
P

LRADC Input [1:0]

inn

ert

A
A
A
A
A
A
A
A
P
A
A
A
G
A
A
G
A
A
A

llw

Fo
A20 Datasheet (Revision 1.1)

A
A

MIC Negative Output


MIC Positive Ouput
FM Right Channel Input
FM Left Channel Input
MIC Power Supply
MIC Input
Reference (1.5V)
Reference (1.5V)
Analog Power Supply
Reference (3.0V)
Linein Right Channel Input
Linein Left Channel Input
Analog Ground
Headphone Right Channel Output
Headphone Left Channel Output
Headphone Ground
Headphone Common Referene
Headphone Common Reference Feedback
Headphone Bypass Output

rA

CSIx-HSYNC
CSIx-VSYNC
TV-IN
TVIN[3:0]
VCC-TVIN
VCC25-TVIN
VRP-TVIN
VRN-TVIN
USB
DM[2:0]
DP[2:0]
VCC-USB
VDD-USB
TP
TPX[2:1]
TPY[2:1]
AUDIO CODEC
MICOUTN
MICOUTP
FMINR
FMINL
VMIC
MICIN[2:1]
VRA1
VRA2
AVCC
VRP
LINEINR
LINEINL
AGND
HPR
HPL
GND-HP
HPCOM
HPCOMFB
HPBP
LRADC
LRADC[1:0]
EMAC
ERXD[3:0]
ETXD[3:0]
ERXCK
ERXERR
ERXDV
EMDC
EMDIO
ETXEN
ETXCK
ECRS
ECOL
ETXERR
GMAC
GRXD[3:0]

EMAC MII Receive Data Nibble Data Bit[3:0]


EMAC MII Transmit Data Nibble Data Bit[3:0]
EMAC MII Receive Clock
EMAC MII Receive Error
EMAC Receive Data Valid
EMAC MII Management Data Clock
EMAC MII Management Data Input/Output
EMAC MII Transmit Enable
EMAC MII Transmit Clock
EMAC MII Carrier Sense
EMAC MII Collision Detect
EMAC MII Transmit Error

I
O
I
I
I
O
I/O
O
I
I
I
O

GMAC Receive Data[3:0]

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 26

Pin Description

Type

Description

GMAC Transmit Data[3:0]


RGMII Null / MII Receive Error
RGMII Receive Control / MII Receive Data Valid
GMAC Management Data Clock
GMAC Management Data Input/Output
RGMII Transmit Control/ MII Transmit Enable
RGMII Null / MII Transmit Clock
RGMII Transmit Clock / MII Carrier Sense
RGMII Clock in / MII Collision Detect
RGMII Null / MII Transmit Error

ec

SPI Chip Select Signal


SPI Clock Signal
SPI Master Data Out, Slave Data In
SPI Master Data In, Slave Data Out

O
I
I, I
O
I/O
O,O
I
O,I
I,I
O

hO

GTXD[3:0]
GNULL/ERXERR
GRXCTL/RXDV
GMDC
GMDIO
GTXCTL/ETXEN
GNULL/ETXCK
GTXCK/ECRS
GCLKIN/ECOL
GNULL/ETXERR
SPI (x=[3:0])
SPIx-CS[1:0]
SPIx-CLK
SPIx-MOSI
SPIx-MISO
UART (x=[7:0])
UARTx-TX
UARTx-RX
UARTx-RTS
UARTx-CTS
UARTx-DTR
UARTx-DSR
UARTx-DCD
UARTx-RING
TWI (x=[4:0])(Open-Drain)
TWIx-SCK
TWIx-SDA
SD/MMC (x=[3:0])
SDCx-D[3:0]
SDCx-CLK
SDCx-CMD
KEYPAD
KP-IN[7:0]
KP-OUT[7:0]
IR(x=[1:0])
IRx-TX
IRx-RX
PS2
PS2-SCK[1:0]
PS2-SDA[1:0]
I2S

nly

Pin/Signal

I/O
I/O
I/O
I/O
O
I
O
I
O
I
I
I

TWI Clock Signal


TWI Data Signal

I/O
I/O

SD/MMC/SDIO Data Bit[3:0]


SD/MMC/SDIO Clock
SD/MMC/SDIO Command Signa

I/O
O
I/O

Keypad Data Input


Keypad Data Output

I
O

IR Data Transmit
IR Data Receive

I/O
I/O

PS2 Clock Signal


PS2 Data Signal

I/O
I/O

I2S-DO[3:0]

I2S Data Output

I2S-DI
I2S-MCLK
I2S-BCLK
I2S-LRCK
I2S1-DO
I2S1-DI
I2S1-BCLK
I2S1-LRCK
I2S1-MCLK
AC97

I2S Data Input


I2S Mater Clock
I2S Bit Clock
I2S Left/Right Select Clock
I2S1 Data Output
I2S1 Data Input
I2S1 Bit Clock
I2S1 Left/Right Select Clock
I2S1 Mater Clock

I
O
I/O
I/O
O
I
I/O
I/O
O

Fo

rA

llw

inn

ert

UART Data Transmit


UART Data Receive
UART Data Request to Send
UART Data Clear to Send
UART Data Terminal Ready
UART Data Set Ready
UART Data Carrier Detect
UART Data Ring Indicator

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 27

Pin Description

Pin/Signal

Type

Description

O
I
O
I/O
I/O

CAN Data Transmit


CAN Data Receive

I
I
I
I
I

hO

Transport Stream Data Bit[7:0]


Transport Stream Clock
Transport Stream Error Indicate
Transport Stream SYNC
Transport Stream Data Valid

nly

AC97 Data Output


AC97 Data Input
AC97 Master Clock
AC97 Bit Clock
AC97 SYNC Signal

O
I

ert

ec

Smart Card Reset


Smart Card Program Voltage Enable
Smart Card Program Control
Smart Card Detect
Smart Card Power Enable
Smart Card Clock
Smart Card Data

O
O
O
I
O
O
I/O
A
A
A
A
A
P
P
A
A

eFuse Power Supply

CPU Power Supply


System Power Supply
Ground
IO Power Supply

P
P
G
P

llw

inn

SATA Positive Transmit


SATA Negative Transmit
SATA Positive Receive
SATA Negative Receive
Reference
SATA Power Supply
SATA Power Supply
SATA Negative Clock
SATA Positve Clock

rA

AC97-DO
AC97-DI
AC97-MCLK
AC97-BCLK
AC97-SYNC
TS (x=[1:0])
TSx-D[7:0]
TSx-CLK
TSx-ERR
TSx-SYNC
TSx-DVLD
CAN
CAN-TX
CAN-RX
SMC
SMC-RST
SMC-VPPEN
SMC-VPPPP
SMC-DET
SMC-VCCEN
SMC-SLK
SMC-SDA
SATA
SATA-TXP
SATA-TXM
SATA-RXP
SATA-RXM
REXT-SATA
VDD-SATA
VDD25-SATA
SATA-CLKM
SATA-CLKP
eFUSE
VDDQE
POWER
VDD-CPU
VDD-SYS
GND
VCC

4.4. POWER SIGNAL DESCRIPTION


DESCRIPTION

BALL#

DRAM Power Supply


DLL Power Supply

G5/H5/L5/W5/W6/W7/M5/R5/T5/Y6
M8/N9/P9

Port A Power Supply


Port C Power Supply

H10/J10
H19/J19

Fo

SIGNAL
DRAM
VCC-DRAM
VDD-DLL
GPIO
VCC-PA
VCC-PC

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 28

Pin Description

L16/L15
K16

MIC Power Supply


Reference(1.5V)
Reference (1.5V)
Analog Power Supply
Reference (3.0V)
Analog Ground

AA21
W20
V20
T19
W21
U19

hO

nly

USB Power Supply


USB Power Supply

W15

ec

TVOUT power supply

HDMI Power Supply


LVDS Power Supply

inn

RTC Power Supply

W16
W17
AA16
Y16

ert

TVIN Power Supply


TVIN Power Supply
TVIN BIAS
TVIN BIAS

T13
W12/W13/W14
K8

PLL Power Supply

P16

eFUSE Power Supply

T9

CPU Power Supply

J12/J13/H11/H12/H13/H14

System Power Supply

Ground

IO power supply

T8/R9/R10/L8/L9/K9/K10/K15/J15/J16
J5/K5/N5/P5/U5/V5/Y7/Y8/G3/G4/L10/L11/
L12/L13/L14/K11/K12/K13/K14J11/M9/M10/
M11/M12/M13/M14/N10/N11/N12/N13/N14/
P10/P11/P12/P13/P14/P15/R11/R12/R13/
T11/T12/W9/W10/W11/W18/Y18/AA18
H8/H9/J8/J9/J14/H15

Fo

VCC

BALL#
F19
N19
E18

rA

GND

DESCRIPTION
Port E Power Supply
Port F Power Supply
Port G Power Supply

llw

SIGNAL
VCC-PE
VCC-PF
VCC-PG
USB
VCC-USB
VDD-USB
AUDIO CODEC
VMIC
VRA1
VRA2
AVCC
VRP
AGND
TV-OUT
VCC-TVOUT
TV-IN
VCC-TVIN
VCC25-TVIN
VRP-TVIN
VRN-TVIN
HDMI
VCC-HDMI
LVDS
VCC- LVDS
RTC
VDD-RTC
CLOCK
VCC-PLL
EFUSE
VDDQE
CPU
VDD-CPU
SYSTEM
VDD-SYS
CORE POWER

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 29

Electrical Characteristics

nly

5.1. ABSOLUTE MAXIMUM RATINGS

hO

ELECTRICAL CHARACTERISTICS

ec

Functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

PARAMETER

Tg

Storage Temperature

II/O

In/Out current for input and output

MIN

MAX

UNIT

C
mA

ert

SYMBOL

HBM(human body model)

CDM(charged device model)

2.7

3.6

ESD stress voltage

VCC

DC Supply Voltage for I/O

VDD

DC Supply Voltage for Internal Digital Logic

1.4

AVCC

DC Supply Voltage for Analog Part

2.8

3.3

VCC-DRAM

Power Supply for DRAM

1.2

2.5

VCC-USB

Power Supply for USB PHY

2.7

3.6

VCC-TVOUT

Power Supply for TV-OUT DAC

2.7

3.6

VCC-PLL

Power Supply for PLL

3.0

3.0

VDD-RTC

Power Supply for RTC

3.0

3.0

VDD-CPU

Power Supply for CPU

0.7

1.4

VDD-SYS

Power Supply for System

0.7

1.4

rA

llw

inn

VESD

VESD

5.2. RECOMMENDED OPERATING CONDITIONS


SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

-20

+70

NA

NA

NA

GND

Ground

VCC

DC Supply Voltage for I/O

1.8

3.3

3.6

VDD

DC Supply Voltage for Internal Digital Logic

1.0

1.4

AVCC

DC Supply Voltage for Analog Part

2.8

3.0

3.3

Fo

Ambient Operating Temperature[Commercial]

Operating Temperature[Extended]

Ta

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 30

Electrical Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

Power Supply for DRAM

1.2

2.5

VCC-USB

Power Supply for USB PHY

2.7

VCC-TVOUT

Power Supply for TV-OUT DAC

2.7

VCC-TVIN

Power Supply for TV-in

2.7

VCC25-TVIN

Power Supply for TV-in

VCC-PLL

Power Supply for PLL

3.0

VCC-LVDS

Power Supply for LVDS

VDD-RTC

Power Supply for RTC

VDD-CPU

Power Supply for CPU

VDD-SYS

Power Supply for System

nly

SYMBOL
VCC-DRAM

3.3

3.6

3.3

3.6

3.3

3.6

2.5

3.0

3.0

3.0

3.0

1.0

1.4

1.0

1.4

ec

hO

3.3

3.0

5.3. DC ELECTRICAL CHARACTERISTICS


TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-Level Input Voltage

VCC=3.3V

2.1

3.3

3.6

Low-Level Input Voltage

VCC=3.3V

-0.3

0.7

VHYS

Hysteresis Voltage

mV

IIH

High-Level Input Current

VCC=3.3V, VI=3.3V

TBD

TBD

TBD

uA

IIL

Low-Level Input Current

VCC=3.3V, VI=0V

TBD

TBD

TBD

uA

VOH

High-Level Output Voltage

VCC=3.3V

2.7

3.3

NA

VOL

Low-Level Output Voltage

VCC=3.3V

NA

0.4

IOZ

Tri-State Output Leakage Current

VCC=3.3V

TBD

TBD

TBD

uA

CIN

Input Capacitance

NA

NA

pF

COUT

Output Capacitance

NA

NA

pF

llw

VIH
VIL

inn

ert

SYMBOL PARAMETER

rA

5.4. OSCILLATOR ELECTRICAL CHARACTERISTICS


The A20 contains two oscillators: a 24MHz oscillator and a 32768Hz oscillator. Each oscillator requires a
specific crystal.
The A20 device operation requires following two input clocks:
The 32768Hz frequency is used for low frequency operation.

Fo

The 24MHz frequency is used to generate the main source clock of the A20 device.

5.4.1. 24MHz OSCILLATOR CHARACTERISTICS


The 24.0MHz crystal is connected between the HOSCI (amplifier input) and HOSCO (amplifier output).

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 31

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

1/(tCPMAIN)

Crystal Oscillator Frequency Range

24

MHz

tST

Startup Time

Frequency Tolerance at 25C

-50

Oscillation Mode

Fundamental

Maximum Change Over Temperature Range

-50

PON

Drive Level

CL

Equivalent Load Capacitance

nly

Electrical Characteristics

CL1,CL2

Internal Load Capacitance(CL1=CL2)

RS

Series Resistance(ESR)

Duty Cycle

30

CM

Motional Capacitance

CSHUT

Shunt Capacitance

RBIAS

Internal Bias Resistor

ms

+50

ppm
-

+50

ppm

50

uW

pF

pF

50

70

pF

pF

ert

ec

hO

5.4.2. 32768HZ OSCILLATOR CHARACTERISTICS

The 32768Hz crystal is connected between the LOSCI (amplifier input) and LOSCO (amplifier output).
PARAMETER

TYP

MAX

UNIT

Crystal Oscillator Frequency Range

MIN

32768

Hz

tST

Startup Time

ms

Frequency Tolerance at 25C

-50

+50

ppm

Oscillation Mode

Fundamental

inn

SYMBOL
1/(tCPMAIN)

Maximum Change Over Temperature Range -50

+50

ppm

Drive Level

50

uW

Equivalent Load Capacitance

pF

CL1,CL2

Internal Load Capacitance(CL1=CL2)

pF

CM
CSHUT

30

50

70

Motional Capacitance

pF

Shunt Capacitance

pF

Internal Bias Resistor

Fo

RBIAS

Series Resistance(ESR)
Duty Cycle

rA

RS

llw

PON
CL

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 32

Electrical Characteristics

nly

5.5. POWER UP/DOWN SEQUENCE

Fo

rA

llw

inn

ert

ec

hO

The external voltage regulator and other power-on devices must provide the processor with a specific sequence of
power and resets to ensure proper operations.

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 33

Pin Assignment

6
6.1. PIN MAP

nly

PIN ASSIGNMENT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

PH15

PH13

PH10

PH6

PH3

PH0

PB22

PB18

PB16

PB14

PB8

PB6

PB4

PB2

PB0

PI8

PI6

PI4

PI2

PI0

PE11

PE9

PE8

PH16

PH14

PH11

PH7

PH4

PH1

PB23

PB19

PB17

PB15

PB13

PB7

PB5

PB3

PH17

PH18

PH12

PH8

PH5

PH2

PB21

PB20

PB12

PB11

PB10

PB9

PA17

PH19

PH20

PH21

PH9

PA0

PA2

PA4

PA6

PA8

PA10

PA12

PA14

PH22

PH23

PH24

PH25

PA1

PA3

PA5

PA7

PA9

PA11

PA13

PA15

X32KI

X32KO

PH26

PH27

NMI#

SDQM3

SDQ29

GND

GND

VCCDRAM

SDQ26

SDQ31

SVREF

SVREF

VCCDRAM

VCC

VCC

VCCPA

VDDCPU

VDDCPU

VDDCPU

VDD-CPU

VCC

SDQ24

SDQS3B

SCK1B

SCK1

GND

VCC

VCC

VCCPA

GND

VDDCPU

VDDCPU

VCC

SDQS3

SDQ27

SBA0

SBA2

GND

VDD-RTC

VDDSYS

VDDSYS

GND

GND

GND

GND

SDQ25

SDQ28

SA10

SBA1

VCCDRAM

VDD-SYS

VDDSYS

GND

GND

GND

GND

SDQ30

SDQ23

SA7

SA3

VCCDRAM

VDD-DLL

GND

GND

GND

GND

SDQ22

SDQ17

SCKE

SA5

GND

SADBG

VDDDLL

GND

GND

SDQ19

SDQS2B

SA12

SA9

GND

SDDBG0

VDDDLL

GND

SDQS2

SDQM2

SA14

SA1

VCCDRAM

SDDBG1

VDDSYS

SDQ20

SDQ16

SWE

SRAS

VCCDRAM

SDQ21

SDQ18

SCAS

SA2

SCK

SCKB

SCS

SDQM1

SDQ13

SA11

SDQ10

SDQ15

SA13

AA

SDQ8

SDQS1B

SA8

AB SDQS1

SDQ11

SDQ14

AC

SDQ9

SDQ12

A20 Datasheet (Revision 1.1)

hO

PI9

PI7

PI5

PI3

PI1

PE10

PE7

PE6

RESET#

PI14

PI12

PI10

PG11

PG9

PG7

PG5

PE5

PE4

PA16

PI19

PI15

PI13

PI11

PG10

PG8

PG4

PG3

PE3

PE2

PI21

PI20

PI18

PI17

PI16

VCCPG

PG6

PG2

PG1

PE1

PE0

VCC-PE

PG0

PC24

PC18

PC17

PC23

PC15

PC14

PC11

PC10

TEST

VCC-PC

PC13

PC12

PC9

PC8

VDD-SYS

VDD-SYS

VCC-PC

PC22

PC21

PC7

PC6

VDD-SYS

VDD-USB

PF5

PF4

PC20

PC5

PC4

GND

VCC-USB

VCC-USB

PF3

PF2

PC19

PC3

PC2

GND

GND

VDD-SATA VDD-SATA

PF1

PF0

PC16

PC1

PC0

GND

GND

GND

VDD25SATA

VDD25SATA

VCC-PF

DM0

DP0

X24MO

X24MI

GND

GND

GND

GND

GND

VCC-PLL

SATACLKM

DM1

DP1

HHPD

HCEC

VDDSYS

GND

GND

GND

NC

PLLVREG

NC

SATACLKP

DM2

DP2

HSDA

HSCL

JTAGSEL

GND

GND

VCCHMDI

HVREG1

PLLTEST

PLLDV

AVCC

SATA-TXP

SATATXM

HTX2N

HTX2P

GND

AGND

SATARXM

SATARXP

HTX1N

HTX1P

SA6

GND

GND-HP

VRA2

REXTSATA

HTX0N

HTX0P

SA0

VCCDRAM

llw

inn

ert
ec

PB1

rA

VDD-SYS VDDQE

VCCDRAM

VCCBOOTSEL
DRAM

GND

GND

GND

VCCLVDS

VCCLVDS

VCCLVDS

VCCTVOUT

VCC-TVIN

VCC25TVIN

GND

HPR

VRA1

VRP

HTXCN

HTXCP

HPL

FMINL

FMINR

TPX1

TPY1

VMIC

TPX2

TPY2

AA

LRADC0

AB

SVREF

VCCDRAM

GND

GND

PD24

PD20

PD18

PD16

PD14

PD12

PD10

VRN-TVIN

TVIN3

GND

SA15

SODT

SRST

SZQ

SVREF

PD25

PD21

PD19

PD17

PD15

PD13

PD11

VRP-TVIN

TVIN2

GND

SDQ6

SDQ3

SDQS0

SDQ4

SDQ5

PD26

PD22

PD8

PD6

PD4

PD2

PD0

TVOUT1

TVOUT3

TVIN1

VCC-HP

LINEINL

LINEINR

LRADC1

SDQ7

SDQ1

SDQS0B

SDQM0

SDQ0

SDQ2

PD27

PD23

PD9

PD7

PD5

PD3

PD1

TVOUT0

TVOUT2

TVIN0

HPBP

MICIN1

MICIN2

MICOUTP

10

11

12

13

14

15

16

17

18

19

20

21

22

Fo
SA4

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

HPCOM HPCOMFB

MICOUTN AC
23

Page 34

Pin Assignment

Fo

rA

llw

inn

ert

ec

hO

nly

6.2. PACKAGE DIMENSION

A20 Datasheet (Revision 1.1)

Copyright 2013 Allwinner Technology Co., Ltd. All Rights Reserved.

Page 35