So9ware
Hardware
Parallel
Requests
Warehouse
Smart
Phone
Scale
Computer
Assigned
to
computer
e.g.
search
Garcia
Leverage
Pipelining Hazards
Achieve
High
Performance
Computer
Parallel InstrucNons
Core
Input/Output
Core
Parallel
Data
>
1
data
item
@
one
Nme
e.g.
add
of
4
pairs
of
words
Core
Memory
InstrucNon Unit(s)
FuncNonal
Unit(s)
A0+B0
A1+B1
A2+B2
A3+B3
Hardware descripNons
Logic Gates
Cache Memory
IF
ID
EX
MEM WB
IF
ID
EX
MEM WB
IF
ID
EX
MEM WB
IF
ID
EX
MEM WB
IF
ID
EX
MUX
+4
1.
InstrucNon
Fetch
MEM WB
rd
rs
rt
Register
File
Data
memory
EX
PC
ID
instrucNon
memory
Time
IF
ALU
imm
5.
Write
Back
ID
Reg
EX
ALU
Mem
WB
D$
Reg
Equality
only
achieved
if
stages
are
balanced
(i.e.
take
the
same
amount
of
Nme)
ALU
Reg
Reg
D$
Reg
I$
Reg
ALU
I$
D$
ALU
Reg
ALU
I$
ALU
Store
O
r Sub
d
e Or
r
D$
Reg
8
Single-cycle
Tc
=
800
ps
Instr
Instr
fetch
Register
read
ALU op
Memory
access
Register
write
Total
time
lw
200ps
100 ps
200ps
200ps
100 ps
800ps
sw
200ps
100 ps
200ps
200ps
R-format
200ps
100 ps
200ps
beq
200ps
100 ps
200ps
700ps
100 ps
600ps
500ps
Pipelined
Tc
=
200
ps
10
Pipelining Hazards
11
1. Structural Hazards
2)Data hazard
3)Control hazard
13
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
ALU
D$
Reg
14
O Instr 2
r
d Instr 3
e
r Instr 4
Reg
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
ALU
I$
I$
D$
ALU
Reg
Reg
ALU
D$
I$
ALU
Reg
I
n
s Load
t
r Instr 1
ALU
Reg
ALU
I$
Trying
to
read
same
memory
twice
in
same
clock
cycle
D$
ALU
Reg
ALU
O Instr 2
r
d Instr 3
e
r Instr 4
I$
ALU
I
n
s Load
t
r Instr 1
D$
Reg
15
add
sub
and
or
xor
$t0,
$t4,
$t5,
$t7,
$t9,
$t1,
$t0,
$t0,
$t0,
$t0,
$t2
$t3
$t6
$t8
$t10
16
18
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
D$
and $t5,$t0,$t6
or $t7,$t0,$t8
Reg
I$
WB
D$
Reg
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
ALU
I$
sub $t4,$t0,$t3
EX MEM
ALU
Reg
Reg
ALU
D$
ID/RF
I$
ALU
Reg
IF
ALU
D$
ALU
I$
add $t0,$t1,$t2
Reg
ALU
Reg
WB
ALU
I$
EX MEM
ALU
and $t5,$t0,$t6
O
r or $t7,$t0,$t8
d
e xor $t9,$t0,$t10
r
ID/RF
ALU
I
n add $t0,$t1,$t2
s
t sub $t4,$t0,$t3
r
IF
D$
xor $t9,$t0,$t10
19
Reg
20
21
22
I$
sub $t3,$t0,$t2
lw $t0, 0($t1)
WB
D$
Reg
Reg
D$
bub
ble
How
to
stall
just
part
of
pipeline?
bub
ble
Reg
bub
ble
I$
Reg
D$
Reg
Reg
ALU
I$
D$
D$
24
bub
ble
bub
ble
bub
ble
I$
Reg
ALU
D$
Reg
I$
Reg
ALU
D$
Reg
I$
Reg
ALU
ALU
bub bub
ble ble
D$
or $t7,$t0,$t6
Reg
and $t5,$t0,$t4
Reg
D$
sub $t3,$t0,$t2
D$
23
nop
I$
EX MEM WB
ALU
or $t7,$t0,$t6
Reg
and $t5,$t0,$t4
I$
ID/RF
I$
sub $t3,$t0,$t2
Reg
lw $t0, 0($t1)
IF
ALU
Reg
I$
EX MEM
ALU
ID/RF
ALU
lw $t0,0($t1)
IF
26
Summary
Stall!
# Method
lw $t1,
lw $t2,
add $t3,
sw $t3,
lw $t4,
add $t5,
sw $t5,
1:
0($t0)
4($t0)
$t1, $t2
12($t0)
8($t0)
$t1, $t4
16($t0)
13 cycles
# Method
lw $t1,
lw $t2,
lw $t4,
add $t3,
sw $t3,
add $t5,
sw $t5,
2:
0($t0)
4($t0)
8($t0)
$t1, $t2
12($t0)
$t1, $t4
16($t0)
Structural
Hazards
Conict
in
use
of
datapath
component
Data
Hazards
Need
to
wait
for
result
of
a
previous
instrucNon
Control Hazards
11
cycles
27
32