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SoC/ASIC/SoC-FPGA/S-ASIC
Design and Verification
Methodology

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Courtesy of Cadence design

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Challenges in Embedded Systems Design

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Critical Issues

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Verification Effort size

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Overview of Verification Methodologies

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Software Simulation

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Software Simulation

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Hardware Acceleration

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Emulation

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Overview of Verification Methodologies

Formal Verification

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Formal Verification : equivalence Check

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Formal Verification : equivalence Check

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Theorem Proving

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Formal Verification : Model Check

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Formal Verification : Model Checking

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Formal Verification : Challenges

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Semi-Formal Verification : Assertion

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Semi-Formal Verification : Coverage

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Semi-Formal Verification : Coverage

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Semi-Formal Verification : Coverage

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Semi-Formal Verification

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Design Complexity

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Language Heritage for SoC Design

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SystemC in SoC Design

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SystemC in SoC Design

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Abstraction Levels of SystemC

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Vera (Synopsys)

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Vera (Synopsys)

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System Verilog

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System Verilog

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Key Components of System Verilog

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System Design Language Summary

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SoC Verification

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Embedded Processor Cores in SoC

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Models of Embedded Processor

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Models of Embedded Processor

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Models of Embedded Processor

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Verification with Embedded Processor

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Verification with Embedded Processor

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Simultaneous SoC design Flow

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Tool utilized in HW-SW Co-Verification

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Tool utilized in Co-Simulation

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Conclusion

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Conclusion