University
Faculty of engineering
-: Name
Mohammed Abdel-Fattah
. Abdel-Hameed Halaby
. Sec. :- 5
. ID :- 198
-1
cost
-2
Resolution
-3
speed
-4
conversio
n time
Counter
Flash type Tracking Pipeline
Type ADC ADC
type ADC d ADC
type
Low because of Expensive
low
low
less complexity
.in design
we could build
that ADC type
with any
precision we
need
Min. 4 bit
Max. 10 bit
Medium
resolution
(8-12 bits)
Low, start
from zero
every time
is varied
2n Clock Period
for Full Scale
input
Ultra high
speed
-5
T * ( 2n - 1 )
Conversion Also it's max.
.time equ
conv. Time
-6
effect of
noise
Min. 8 bit
Max. 14 bit
speed
T * ( 2n - 1 )
Also it's
max. conv.
Time
Parallel
Sigma
-Delta
Low cost
come in 16 to
24-bit
resolution
high
High
resolution
(10-20 bits)
Low
Higher cost
than dual
slope
integrating
Medium
resolution
(8-16 bits)
-2
Resolution
speed
2n 2
Excellent
Noise
Rejection
cost
Higher speed -3
maximum
Fixed
conversion of conversion
2 2n clock
time
cycles, n is no.
of bits
has
better noise
rejection than
many others
-1
-4
conversio
n time
-5
Conversion
.time equ
Highly
susceptible to
,noise
must pre-filter
-6
effect of
noise
Serial