Chapter 3

8051/8031 Family Architecture

Lesson 1

8051/8031Architecture
overview

2011

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

CPU Feature and Special

Function Registers

2011

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

8051 Special Function Registers

CPU (A, B, SP, PSW, DPL,

DPH)
Registers associated with the,
Internal-devices, Ports

2011

Microcontrollers-... 2nd Ed. Raj Kamal

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CPU Registers
8- bit A (Accumulator) Register
8-bit B Register
8- bit PSW (Processor Status
Word)
8-bit Stack Pointer SP
2011

Microcontrollers-... 2nd Ed. Raj Kamal

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CPU Registers Common Uses

A as Accumulator in instructions
B for MUL and DIV
PSW for Processor Status Word
for flag bits and register-bank
selection bits
SP for stack at internal memory
2011

Microcontrollers-... 2nd Ed. Raj Kamal

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Pointer 16-bit Registers

16-bit Program Counter PC to
point to instruction byte in program
memory
16-bit Data Pointer DPTR points a
byte in external data memory
DPTR two bytes in DPH and DPL
SFRs
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Microcontrollers-... 2nd Ed. Raj Kamal

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Execution Unit- ALU

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Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

Execution Unit
IR
ID
Control
and
Sequencer
Circuits

SP
A
B
2011

Temp 1

Temp 2

ALU
+, ,
or
Rotate

DAA

OR,
AND,
XOR

PSW

SFRs, Internal RAM

and ROM, RAM,
Microcontrollers-... 2nd Ed. Raj Kamal
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 Instructions have 8 -bit data

types

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10

PSW
PSW.0
PSW.1
PSW.2
PSW.3
PSW.4
PSW.5
PSW.6
PSW.7
2011

P
F1
OV
RS0

Zero flag
User Flag1

Default value
= All 0s

Overflow flag

Register bank select bit0

RS1 Register bank select bit1
F0 Flag 0 of user
AC Auxiliary Carry
C Carry flag
Microcontrollers-... 2nd Ed. Raj Kamal
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11

PC
Default value
= 0000H

2011

Not an
SFR

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

Increases by
01H for next
instruction
fetch

12

Internal bus

Fetch
Decode
Execution

IR
ID
Control
and
Sequencer
Circuits

Control memory micro codes based Implementation

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Microcontrollers-... 2nd Ed. Raj Kamal

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13

Instruction Execution
Instruction
STAGE 1
Fetch
STAGE 2

Instruction
Decode

STAGE 3 to n

Instruction
Execute

2011

Microcontrollers-... 2nd Ed. Raj Kamal

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clock
cycle (s)

Time

14

MCU Architecture overview

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Microcontrollers-... 2nd Ed. Raj Kamal

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15

Buses and Cycle Time

8-bit and 16-bit internal buses

separate for data memory and SFRs,
and program memory
16 bit address and 8 bits external data
buses to program and data memoy

12 MHz XTAL- Clock rate 1MHz,

1 s single instruction cycle time.
2011

Microcontrollers-... 2nd Ed. Raj Kamal

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16

 8051 separate 16-bit internal bus for

the 16-bit addressing and separate 8-bit

data bus
Harvard architecture bus
Bus interface for 16-bit/8-bit address,
data and instructions.
Two Maskable Interrupt requests INT1
at P3.3 Interrupt and INT0
PC initialization 0000H
Reset

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Microcontrollers-... 2nd Ed. Raj Kamal

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17

Internal and External Buses

MDR
MAR

SFRs
Internal RAM
Program
memory

AD0 AD7

A8-A15
Buses
Ports P0
Interface and P2
option Unit

ALE
PSEN
Internal Bus 16-bit
RD
Internal Bus
Address
WR
8-bit
Microcontrollers-...
2nd
Ed.
Raj
Kamal
2011
Pearson Education
Bus 16-bit
PC

program
memory
or data
memory
18

Internal Devices

Timers T0 andT1 timer with

reset, internal/external clocking
inputs and load/auto reload
A watchdog timer
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Microcontrollers-... 2nd Ed. Raj Kamal

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19

Internal Devices
Serial Interface SI-option UART full
duplex or half duplex serial
synchronous bits with separate clock
bits

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Microcontrollers-... 2nd Ed. Raj Kamal

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20

8051 Architecture view

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Microcontrollers-... 2nd Ed. Raj Kamal

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21

P0

T0

SI

T1

IR
ID
Reset
Osc
Interrupt
Control

Execution
unit
Condition test
branch logic

Internal
ROM

A8-A15
P2

WDT
IO and internal
devices SFRs

Port P3

Port P1

AD0-AD8

A, B,PSW, SP
DPTR
Register Banks of 8
registers and
internal RAM

PC

Control and Sequencing Circuit

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Microcontrollers-... 2nd Ed. Raj Kamal

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22

Special Function Registers (SFRs)

and Internal RAM

SFR A, B, PSW bytes also have the 8-bit

address for each bit like an internal
device or port

An SFR address space is distinct from

an Internal RAM address.Byte at SFR
has an 8-bit address.

Select bits at SFR and select bits at internal

RAM are individually addressable

2011

Microcontrollers-... 2nd Ed. Raj Kamal

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23

Bit- Addresses
PSW.7
D7H
PSW.6
D6H
D5H
D4H
D3H

PSW.5
PSW.4

D2H

PSW.2

D1H
D9H
2011

PSW

Default value
= All 0s

PSW.7

Byte
Address
= D0H

PSW.3

PSW.1
PSW.0

PSW.7PSW.0
PSW.0
Microcontrollers-... 2nd Ed. Raj Kamal
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24

Accumulator

A and B
A

Default
value
= 00H

SFR
Address
E0H

Bit-Addresses
E0-E7H

2011

For
MUL
and DIV

SFR
Address
F0H

Default
value
= 00H

Bit-Addresses
F0-F7H

Microcontrollers-... 2nd Ed. Raj Kamal

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25

SP
Default value
= 07H

2011

SFR
Address
81H

Microcontrollers-... 2nd Ed. Raj Kamal

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Increases by
01H before
push,
decreases
after pop by
01H
26

Lower byte

Default
value
= 0000H
2011

DPTR

Higher byte

DPL

DPH

SFR
Address
82H

SFR
Address
83H

Data Memory address

Pointer
Microcontrollers-... 2nd Ed. Raj Kamal
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27

Program Memory Architecture

64 kB separate address spaces for
program from data memory
Program Memory
Program,
Address

8051

Internal ROM
External ROM
Internal ROM Addresses
Used when EA = 1
2011

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

constants
and
stored
tables
Memory

28

Internal Data and SFRs Architecture Internal

RAM and
Address CPU, IO and internal
SFRs
devices SFRs,
separate
Address

Bank-registers and
Internal RAM

2011

8051
special
feature

Separate 64 kB External data Memory

Microcontrollers-... 2nd Ed. Raj Kamal

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29

8051 Family Programming Model

IO and internal
devices SFRs, SP
Internal
and/or
External
ROM

Internal RAM
including 4
Registers Banks
External RAM

A,B, PSW

8 registers
each
bank

Linear Distinct 16-bit addresses from

Microcontrollers-... 2nd Ed. Raj Kamal
program
2011
Pearson Education

30

8051 Pins

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Microcontrollers-... 2nd Ed. Raj Kamal

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31

RST
P3.7 to P3.0
XTAL2
XTAL1
VSS

VDD
P0.0 to P0.7
EA
ALE
8051 PSEN
P2.7 to P2.0

AD0 AD7

options

P1.0 to P1.7

A8-A15

P3 options
WR, RD, T1, T0, INT1/GT1, INT0/GT0,
TxD/CLK, RxD/Data
2011

Microcontrollers-... 2nd Ed. Raj Kamal

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32

EA, ALE, PSEN

EA is made 0 by user to enable use of
external program memory space in place
of the internal program memory space
Control signal ALE = 1 to enable
latching of address A0-A7 bits from AD0AD7
Control signal PSEN = 0 to enable read of
program memory bits from external
program memory
2011

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

33

Oscillator Circuit, Supply circuit

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Microcontrollers-... 2nd Ed. Raj Kamal

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34

Oscillator Circuit
XTAL
XTAL1
C-Osc

8051
XTAL2
C-Osc

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Microcontrollers-... 2nd Ed. Raj Kamal

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35

Supply circuit
< 1cm

VSS

8051
VDD
Cd
decoupling
capacitor
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Microcontrollers-... 2nd Ed. Raj Kamal

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36

Reset circuit

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Microcontrollers-... 2nd Ed. Raj Kamal

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37

Internal Resistance
VDD

< 1cm

RST

8051
VSS
Cd
decoupling
capacitor
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Microcontrollers-... 2nd Ed. Raj Kamal

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38

VDD

8051

< 1cm
Push
button
for
manual
reset

RST

VSS
Cd
decoupling
capacitor
2011

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

39

Summary

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Microcontrollers-... 2nd Ed. Raj Kamal

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40

We learnt

2011

8051 family 8-bit processor

PC, SP, PSW
Harvard architecture
8 bit data types
Little endian 16-bit word alignment
Interrupts Maskable Interrupt requests
(INT0, INT1)
PC 0000H at reset
Microcontrollers-... 2nd Ed. Raj Kamal
Pearson Education

41

We learnt

Internal SFR Addresses

2011

IO/Devices Control and Status

SFRs, SP
Internal RAM Addresses
Internal and External ROM
addresses
External RAM addresses
Microcontrollers-... 2nd Ed. Raj Kamal
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42

We learnt
Internal Devices
T0 and T1
SI
WDT

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Microcontrollers-... 2nd Ed. Raj Kamal

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43

We learnt
Pins
Port P0 with option of AD0-AD7
Port P1
Port P2 with option of AD8-AD15,
Port P3 with options WR, RD, T1, T0,
INT1/GT1, INT0/GT0, TxD/CLK,
RxD/Data

2011

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

44

We learnt
Pins
VDD and VSS
XTAL1and XTAL2
EA, ALE, PSEN, RST

2011

Microcontrollers-... 2nd Ed. Raj Kamal

Pearson Education

45