CS221 Di it l D i

CS221:DigitalDesign

ClockedRS,D,JKandTFlip
Flop

Dr.A.Sahu
Dept of Comp. Sc. & Engg.
DeptofComp.Sc.&Engg.
IndianInstituteofTechnologyGuwahati

Out e
Outline
Designanewbuildingblock,aflipflop,that
storesonebit
bi
LatchVsFlipFlop
MasterSlaveFlipFlop
DFlip
D FlipFlop
Flop,JJK
KFlip
FlipFlop
FlopandTFlip
and T FlipFlop
Flop
Combinethatblocktobuildmultibitstorage
aregister
a register

Sequential Circuit
SequentialCircuit
x

b
Input

Combinational
logic

n1

output

n0
s1
clk

s0

History/
S
Sequence/State
/St t

Y(t)=F(a(t),b(t),H)
H is History/Sequence/State
HisHistory/Sequence/State

Whereto
Storethis
History
(Memory
Element)

BitStorageUsinganSRLatch
SR latch

S (set)

Doesthecircuittotheright,withcross
coupledNORgates,dowhatwewant?
p
g
,
Yes!Howdidsomeonecomeupwiththatcircuit?
Maybejusttrialanderror,abitofinsight...
S=0
0
1
R=1

1
0
R1
0
t 1
0
Q1
0

t
1

0 Q

S=0
0
1
R=0

t
1

0 Q

S=1
1
0
R=0

Q
R (reset)

S=0

t
0
1 Q

1 Q

R=0

ProblemwithSRLatch:RaceCondition
Problem:IfS=1&R=1simultaneouslyandboth
releasedto0,wedontknowwhatvalueQwill
1
S
S=1 take
S=0
S=0
t
t
t
0
0

0
R=1

0 Q

1 Q

R=0

R=0

0 Q

1
R

0
1

t
0
1
Q
0

Qmayoscillate.Then,becauseone
pathwillbeslightlylongerthanthe
other,Qwilleventuallysettleto1or
0 butwedon
0
but we donttknowwhich.
know which

t
Q

1
0
1
0

ProblemwithSRLatch
Problemnotjustoneofauserpressingtwobuttonsat
sametime
CanalsooccurevenifSRinputscomefromacircuitthat
supposedlyneversetsS=1andR=1atsametime
does due to different delays of different paths
But
Butdoes,duetodifferentdelaysofdifferentpaths
X

Arbitrary
circuit

SR latch

1
X
0
1
Y
0

Q
Y

1
S
0
SR = 11

ThelongerpathfromXtoRthantoS
The longer path from X to R than to S
causesSR=11forshorttime could
belongenoughtocauseoscillation

1
R
0

Solution: LevelSensitive
Solution:Level
SensitiveSRLatch
SR Latch
AddenableinputCasshown
Only
OnlyletSandRchangewhenC
let S and R change when C=0
0
EnsurecircuitinfrontofSRneversetsSR=11,exceptbriefly
duetopathdelays
ChangeCto1onlyaftersufficienttimeforSandRtobestable
Ch
C t 1 l ft
ffi i t ti
f S d R t b t bl
WhenCbecomes1,thestableSandRvaluepassesthrough
thetwoANDgatestotheSRlatchsS1R1inputs.
Level-sensitive SR latch
S

S1

Q
C
Q
R

C
Q
R
R1

Level-sensitive SR
latch symbol

Solution:LevelSensitiveSRLatch
Level-sensitive SR latch
S

Clk

S1

C
Q
R

Y
S

Though SR=11 briefly...

0
1

1
0

S1
R1

R1

0
1
0

...S1R1 never = 11

Solution:Ensure,Stabilize,Store
Level-sensitive SR latch
S

Clk

S1

C
Q
R

R1

Ensure
Stage
NeverHappens
SR=11

Stabilize
Stage

Store
Stage

WhenC=0
When
C=0
StabilizeSRand
UsewhenC=1

Storebit

Clocks

Clockperiod:timeintervalbetween
pulses
pulses
Abovesignal:period=20ns

Freq

Period

Clockcycle:onesuchtimeinterval

100 GHz

0.01 ns

Abovesignalshows3.5clockcycles

10 GHz

0.1 ns

1 GHz

1 ns

100 MH
MHz

10 ns

10 MHz

100 ns

Clockfrequency:1/period
Above
Abovesignal:frequency=1/20ns=50
signal: frequency = 1 / 20 ns = 50
MHz
1Hz=1/s

ClockSignalsforaLatch
HowdoweknowwhenitssafetosetC=1?
d
k
h
f
MostcommonsolutionmakeCpulseup/down
C=0:SafetochangeX,YC=1:Mustnot
C 0 Safe to change X Y C 1 Must not changeX,Y
change X Y
Clock signal Pulsingsignalusedtoenablelatches
Becauseittickslikeaclock
Because it ticks like a clock
Sequentialcircuitwhosestoragecomponentsalluse
clocksignals:synchronous circuit
Level-sensitive SR latch
S
S1

Clk

C
Q
R

R1

LevelSensitiveDLatch
SRlatchrequirescarefuldesignto
ensure SR=11 never occurs
ensureSR=11neveroccurs
Dlatchrelievesdesignerofthat
burden

D latch
D
S

InsertedinverterensuresRalways
oppositeofS

Q
R

1
0
1
0
1

0
1
0
1
0

D latch symbol

ProblemwithLevelSensitiveDLatch
Dlatchstillhasproblem(asdoesSRlatch)
WhenC=1,throughhowmanylatcheswillasignaltravel?
DependsonforhowlongC=1
D
d
f h l
C 1
Clk_A signalmaytravelthroughmultiplelatches
Clk_B signalmaytravelthroughfewerlatches
HardtopickCthatisjusttherightlength
d
i k h i j
h i h l
h
Canwedesignbitstoragethatonlystoresavalueonthe
risingedgeofaclocksignal?
Y

D1
C1

Q1

D2
C2

Q2

D3
C3

Clk
Clk_A

Clk_B

Q3

D4
C4

rising edges

Q4

Clk

Flip Flop
FlipFlop
CoinFlip:Head/Tail(1/0)
Coin Flip : Head/Tail (1/0)
Latchhaveeitheronestate0or1
FlipFlop(BothMaster/Slave)
FlipState/FlopState

MasterSlaveDFlipFlop
Flip
Flipflop: stores
storesonclockedge,notlevel
onclockedge,notlevel
Twolatches,outputoffirstgoestoinputofsecond,masterlatch
hasinvertedclocksignal
SomasterloadedwhenC=0,thenservantwhenC=1
WhenCchangesfrom0to1,masterdisabled,servantloadedwith
When C changes from 0 to 1 master disabled servant loaded with
valuethatwasatDjustbeforeCchanged i.e.,valueatDduring
risingedgeofC
D flip-flop
D latch
D

Dm

Qm

Clk

D latch
Ds

Qs

D/Dm
Cm

Cm
master
Clk

Cs

Qs

servant

Q
Qm/Ds
Cs
Qs

Thanks