I/O COUPLER
GENERAL DESCRIPTION
The W83758F is an I/O-coupler chip that includes six line drivers (1488), ten line receivers (1489),
two timers (556), an IDE control signal buffer (74244), and an IDE data bus transceiver (74245). It
also supports a power-down control circuit to reduce power consumption. This chip is intended for use
with a super I/O controller, and it is specifically designed to match the pin assignments of the
Winbond Super I/O series. With this chip, engineers can easily design an all-in-one I/O circuit for
personal computer systems without using any other TTL ICs.
FEATURES
Six line drivers (1488), ten line receivers (1489), two timers (556), IDE control signal buffer (74244),
and IDE data bus transceiver (74245)
Supports two RS232 serial ports and game port control logic
Power-down control function available
Four power supplies needed: 0V, +5V, +12V, and -12V
64-pin QFP package
PIN CONFIGURATION
/
R
V
O
P
3
/
/
R
R
V
V
O G O
P N P
2 D 1
P
D
C
I
N
I I
D D
0 1
I
D
2
I
D
3
I
D
4
I
D
5
I
D
6
/
C
S
0
O
P
/
C
S
1
O
P
G
B
O
0
G
B
O
1
R
V
I
12 N
V 9
R
V
I
N
6
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RVOP4
52
32
DROP5
DRIN1
53
31
RVIN7
DRIN2
54
30
RVIN8
DRIN3
55
29
RVIN10
RVOP5
56
28
DROP4
GMRD
57
27
DROP6
GMWR
58
26
RVIN1
DRIN4
59
25
RVIN4
DRIN5
60
24
DROP2
DRIN6
61
23
RVIN3
RVOP6
62
22
RVIN2
RVOP7
63
21
RVIN5
RVOP8
64
20
DROP3
/ +
R 5
V V
O
P
9
9 10 11 12 13 14 15 16 17 18 19
/
R
V
O
P
10
/
C
S
0
I
N
/ M
C R
S
1
I
N
S
D
0
S
D
1
S
D
2
S
D
3
S
D
4
-1-
S
D
5
S
D
6
/
I
O
R
I
N
/
I
O
W
I
N
G
P
O
1
G +
P 12
O V
0
/
D
R
O
P
1
W83758F
PIN DESCRIPTION
Power Pins
PIN NO.
SYMBOL
I/O
DESCRIPTION
49
GND
Ground
+5V
+5V Power
18
+12V
+12V Power
35
-12V
-12V Power
PIN NO.
SYMBOL
I/O
DESCRIPTION
53
DRIN1
Driver input 1
54
DRIN2
Driver input 2
55
DRIN3
Driver input 3
59
DRIN4
Driver input 4
60
DRIN5
Driver input 5
61
DRIN6
Driver input 6
19
DROP1
Driver output 1
24
DROP2
Driver output 2
20
DROP3
Driver output 3
28
DROP4
Driver output 4
32
DROP5
Driver output 5
27
DROP6
Driver output 6
Line Driver
Line Receiver
PIN NO.
SYMBOL
I/O
DESCRIPTION
26
RVIN1
Receiver input 1
22
RVIN2
Receiver input 2
23
RVIN3
Receiver input 3
25
RVIN4
Receiver input 4
21
RVIN5
Receiver input 5
33
RVIN6
Receiver input 6
31
RVIN7
Receiver input 7
30
RVIN8
Receiver input 8
-2-
W83758F
Line Receiver, continued
PIN NO.
SYMBOL
I/O
DESCRIPTION
34
RVIN9
Receiver input 9
29
RVIN10
Receiver input 10
48
RVOP1
I/O
50
RVOP2
Receiver output 2
51
RVOP3
Receiver output 3
52
RVOP4
Receiver output 4
55
RVOP5
Receiver output 5
62
RVOP6
Receiver output 6
63
RVOP7
Receiver output 7
64
RVOP8
Receiver output 8
RVOP9
Receiver output 9
RVOP10
Receiver output 10
PIN NO.
SYMBOL
I/O
DESCRIPTION
17
GPO0
I/O
16
GPO1
I/O
37
GBO0
36
GBO1
Game Port
57
Control Signals
-3-
W83758F
PIN NO.
SYMBOL
I/O
DESCRIPTION
MR
14
IORIN
15
IOWIN
CS0IN
CS1IN
39
CS0OP
38
CS1OP
47
PDCIN
PIN NO.
SYMBOL
I/O
SD0
I/O
SD1
I/O
SD2
I/O
10
SD3
I/O
11
SD4
I/O
12
SD5
I/O
13
SD6
I/O
46
ID0
I/O
45
ID1
I/O
44
ID2
I/O
43
ID3
I/O
42
ID4
I/O
41
ID5
I/O
40
ID6
I/O
Data Bus
DESCRIPTION
BLOCK DIAGRAM
-4-
W83758F
ID0-6
SD0-6
74245
GBO0
GBO1
GPO0'
GPO1'
GPO0
GPO1
556
CS0OP
CS1OP
BUFFER
GMWR
CS0IN
CS1IN
GMRD
IORIN
IOWIN
DRIN1-6
RVOP1-10
LINE
DRIVER
1488
DROP1-6
LINE
RECEIVER
1489
RVIN1-10
FUNCTIONAL DESCRIPTION
Block 74245
The IDE low byte data bits (except for bit 7) are connected to the host data bus via this transceiver.
The transceiver is controlled by IORIN to read from the IDE data bus and by IOWIN to write to the
bus.
This transceiver also functions as a buffer for reading game port buttons GBO0 and GBO1 and the
status of block 556 output signals GPO0' and GPO1' on bits 4, 5, 0, and 1, respectively.
Block 556
This block contains two independent 555-type timing circuits for generating two separate one-shot
signals, which may be used to measure the RC inputs of the game port. The GMWR signal is the
trigger signal of block 556.
-5-
W83758F
Line Receiver Block 1489
This block contains ten line receivers that are designed to serve as an interface between data
terminal equipment and data communications equipment in conformance with the specifications of
EIA standard no. RS-232C. The power requirements are +12V, 0V, and -12V.
Buffer Block
This block consists of buffers for IDE select signals.
RATING
UNIT
GND, VCC
-0.3 to 7.0
VSS, VDD
-14 to 14
Low Voltage
-0.5 to 7.0
High Voltage
-12 to 12
Operating Temperature
Storage Temperature
0 to 70
-55 to +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
Ta = 0 to +70 C, VCC = 5V, VDD = 12V, VSS = -12V, GND = 0V
PARAMETER
SYMBOL
MIN.
MAX.
VIL (TTL)
-0.3V
+0.6V
NOTES
MR, GMRD , GMWR , IORIN ,
IOWIN , CS0IN , CS1IN
VIH (TTL)
+2.4V
VCC+0.3V
VIL (CMOS)
-0.3V
0.2 VCC
VIH (CMOS)
+3.9 V
VCC+0.3V
VIL (HI-V)
VSS
GND
RVIN1-10
VIH (HI-V)
2V
VDD
RVIN1-10
-6-
W83758F
DC Characteristics, continued
PARAMETER
SYMBOL
MIN.
MAX.
NOTES
VOL
0.4V
VOH
+2.4V
VOL (HI-V)
VSS
-2V
DROP1-6
VOH (HI-V)
+2V
VDD
DROP1-6
CURRENT LEVEL
SYMBOL
MAX.
MIN.
TYP.
IIL
IIH
IOL
IOH
IOL
IOH
MR
-20 A
3 A
CS0IN, CS1IN
-20 A
3 A
IOWIN, IORIN
-20 A
3 A
PDCIN
-20 A
3 A
GMWR , GMRD
-20 A
3 A
GBO0, GBO1
-20 A
3 A
RVIN1-10
-1 mA
3 A
GPO0, GPO1
1.5 mA
2 mA
CS0OP, CS1OP
7 mA
5.5 mA
10 mA
9 mA
ID0-6
7 mA
5.5 mA
11 mA
9 mA
SD0-6
7 mA
5 mA
10 mA
8 mA
RVOP1 -10
2 mA
2 mA
3 mA
3 mA
DROP1 -6
10 mA
10 mA
18 mA
18 mA
-7-
W83758F
AC CHARACTERISTICS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
1488 tpLH
DRIN1-6
60
90
nS
1488 tpHL
DROP1-6
60
90
nS
1489 tpLH
RVIN1-10
60
90
nS
1489 tpHL
RVOP1 -10
60
90
nS
tpLH
MR
50
70
nS
tpLH
70
120
nS
CS0OP , CS1OP
70
120
nS
SD0-6
90
120
nS
tisLH
ID to SD
80
130
nS
tisHL
ID to SD
60
110
nS
tsiLH
SD to ID
60
110
nS
tsiHL
SD to ID
45
95
nS
IOWIN
tpHL
tD
-8-
W83758F
TMING WAVEFORMS
Buffer Timing
+5 V
IN
CS0IN
tp L H
0V
tp H L
CS1IN
+5 V
CS0OP
OUT
0V
CS1OP
Driver Timing
+5 V
IN
tp L H
DRIN1-6
tp H L
0V
DROP1-6
+12 V
OUT
-12 V
Receiver Timing
+12 V
IN
RVIN1-10
-12 V
tp L H
tp H L
RVOP1-10
+5 V
OUT
0V
-9-
W83758F
Timing waveforms, continued
Timer Timing
GMWR
CV= 3.3 V
GPO0
GPO1
GPO0'
T= RC
GPO1'
GMRD
tD
SD0-6
Floating
Floating
Data Valid
+5 V
IN
ts iL H
SD0-6
0V
t s iH L
+5 V
ID0-6
OUT
0V
+5 V
ID to SD
ID0-6
IN
0V
t is L H
tis H L
+5 V
SD0-6
OUT
0V
- 10 -
W83758F
APPLICATION CIRCUIT
U3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
51
52
53
54
55
57
58
59
60
61
D0
D1
D2
D3
D4
D5
D6
D7
66
67
68
69
70
71
72
73
/IOR
/IOW
63
64
XIQ3
XIQ4
IRQ6
XIQ7
T/C
DRQ2
/DACK2
R4
C13
10P
44
37
99
23
97
100
98
7
8
X1
24MHz
5K
C16
10P
P0
P1
P2
P3
P4
P5
P6
P7
/IOCS16
93
XAT
JP10
1
3
5
7
1
3
5
7
RN7
RN3
18
8P4R-33
2
9
4
10
6
11
8
12
2
13
4
14
6
16
8
17
8P4R-33
RESET
6
AEN
62
W83757
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
SIN1
SOUT1, /S3
/RTS1, /P2
/DTR1, /P1
/CTS1
/DSR1
/DCD1
/RI1
SIN2
SOUT2, /S4
/RTS2, /S2
/DTR2, /S1
/CTS2
/DSR2
/DCD2
/RI2
D0
D1
D2
D3
D4
D5
D6
D7
/RDATA
/WD
/WE
/HEAD
/DIR
/STEP
/TRAK0
/INDEX
/DSKCHG
/WP
/IOR
/IOW
IRQ3
IRQ4
IRQ6
IRQ7
TC
DRQ2
/DACK
XTAL1
XTAL2
/IOCS16
/XAT
/PRTOE
P0
P1
P2
P3
P4
P5
P6
P7
/MOA
/MOB
/DSA
/DSB
/RD3FO, /FDCEN
/RWC
/RESIDE
/CS1, HADSEL
/CS0, /IDDEN
/DBENH, /FADSEL
/DBENL, ABCHG
IDED7
/GMRD
/GMWR
MR
AEN
VCC
15
56
+5 V
+5 V
V V V V V V V
S S S S S S S
S S S S S S S
BUSY
PE
SLCT
/ACK
/ERR
/SLIN
/INIT
/AFD
/STB
30
38
36
35
34
33
32
31
SIN1
SOUT1
/RTS1
/DTR1
/CTS1
/DSR1
/DCD1
/RI1
42
43
45
46
47
48
49
50
SIN2
SOUT2
/RTS2
/DTR2
/CTS2
/DSR2
/DCD2
/RI2
74
86
85
88
89
82
78
81
76
77
/RDDATA
/WD
/WE
/HEAD
/DIR
/STEP
/TRAK0
/INDEX
/DSKCHG
/WP
79
80
83
84
2
87
/MOA
/MOB
/DS0
/DS1
/FDCEN
/RWC
1
95
94
92
91
96
/RESIDE
/CS1
/CS0
/DBENH
/DBENL
IDED7
41
39
/GMRD
/GMWR
24
27
28
26
29
22
21
20
19
BUSY
PE
SLCT
/ACK
/ERR
/SLIN
/INIT
/AFD
/STB
/
F
D
C
E
N
/
D
T
R
1
/
R
T
S
1
/
D
T
R
2
S
O
U
T
2
7 5 3 1
S
O
U
T
1
/
R
T
S
2
7 5 3 1
RN5C
8P4R-4.7K
8P4R-4.7K
RN6C
8 6 4 2
X
F
1
D
2
C
3
E
4
N
5
6
8 6 4 2
7 8 9
VCC
13
14
15
16
17
18
H
1 1 1 JP9
0 1 2
JP14
SLCT
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
PE
BUSY
/ACK
P7
P6
P5
P4
P3
/SLIN
P2
/INIT
P1
/ERR
P0
/AFD
/STB
C23
222
222
C14
C12
222
222
C11
C10
222
222
C8
C7
222
C5
222
PRINTER PORT
222
C6
4 5 2 4 6 7 9
5 0 5 5 0
- 11 -
W83758F
Application circuit, continued
X
D
S
R
1
N
U2
D6
D5
D4
D3
D2
D1
D0
13
12
11
10
9
8
7
/DTR1
/RTS1
SOUT1
SOUT2
/RTS2
/DTR2
61
60
59
55
54
53
SIN1
/RI1
/DCD1
/DSR1
/CTS1
SIN2
/CTS2
/DSR2
/DCD2
/RI2
3
1
64
63
62
55
52
51
50
48
/GNWR
57
58
/IOR
/IOW
14
15
/CS0
/CS1
4
5
RESET
PDCIN
47
W83758F
JP8
40
41
42
43
44
45
46
ID6
ID5
ID4
ID3
ID2
ID1
ID0
DRIN6
DRIN5
DRIN4
DRIN3
DRIN2
DRIN1
/DROP6
/DROP5
/DROP4
/DROP3
/DROP2
/DROP1
27
32
28
20
24
19
XDTR1N
XRTS1N
/RVOP10
/RVOP9
/RVOP8
/RVOP7
/RVOP6
/RVOP5
/RVOP4
/RVOP3
/RVOP2
/RVOP1
RVIN10
RVIN9
RVIN8
RVIN7
RVIN6
RVIN5
RVIN4
RVIN3
RVIN2
RVIN1
29
34
30
31
33
21
25
23
22
26
XSIN1
XRI1N
XDCD1N
XDSR1N
XCTS1N
XSIN2
XCTS2N
XDSR2N
XDCD2N
XRI2N
/GMRD
/GMWR
GBO0
GBO1
/IORIN
/IOWIN
GPO0
GPO1
/CS0IN
/CS1IN
/CS0OP
/CS1OP
+12V
-12V
MR
PDCIN
+5V
GND
RN1B
1
3
5
7
3
2
4
6
8
8P4R-4.7K
X
C
T
S
1
N
X
R
I
1
N
X
D
S
R
2
N
6 7 8 9 10 JP3
ID6
ID5
ID4
ID3
ID2
ID1
ID0
SD6
SD5
SD4
SD3
SD2
SD1
SD0
R1
X
D
C
D
2
N
X
S
I
N
2
X
D
T
R
2 G
N N
D
C5
1
2
3
4
5
6
7
8
C1
50P
4 7 5 1
9
10
11
12
13
14
15
16
GAME-PORT
GPO0
GPO1
RN1A
8P4R-2.2K
VCC
GND
JP13
- 12 -
3 8 6 2
GPO0
GPO1
C2
.01U
/CS0OP
/CS1OP
+12V
-12V
JP2
50P
17
16
59
58
470
GBO0
GBO1
JP4
1 2 3 4 5
X
D
T
R
1 G
N N
D
R2
GBO0
GBO1
2
49
X
R
I
2
N
VCC
XRTS2N
XDTR2N
37
36
18
35
470
X
S
I
N
1
X
C
T
S
2
N
COMB
1 2 3 4 5
X
D
C
D
1
N
X
R
T
S
2
N
6 7 8 9 10
COMA
VCC
/GMRD
PDCIN
/RI2
XAT
X
R
T
S
1
N
C3
.01U
W83758F
Application circuit, continued
JP13
D D D D D D D D
8 9 1 1 1 1 1 1
0 1 2 3 4 5
A
L
E
/
I
O
C
S
1
6
VCC
A /
2 C
S
1
O
P
1
2
3
4
5
6
7
8
XIQ4
XIQ3
XIQ7
2 4 6 8 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4
0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0
1 1 1 1 1 2 2 2 2 2 3 3 3 3 3
1 3 5 7 9 1 3 5 7 9 1 3 5 7 9 1 3 5 7 9
JP11
9
10
11
12
13
14
15
16
IRQ4
IRQ3
IRQ5
RESET
DRQ2
-12V
IRQ7
+12V
/IOW
/IOR
JP1
IDE
VCC
/
R
E
S
I
D
E
I
O
C
/ / H
I I R
O O
WR D
I
D
E
D I I I I I I I
D D D D D D
7 D
6 5 4 3 2 1 0
I
R
Q
1
4 A A
1 0
JP7
R3
150
/
C
S
0
O
P
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
/DACK2
T/C
ALE
VCC
/
C
S
1
RP1
6P5R-150
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
FDC
/
D
B
E
N
L
/
D
B
E
N
H
/IOCS16
RN4
8P4R-4.7K
/RWC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
/INDEX
/MOA
/DS1
/DS0
/MOB
/DIR
/STEP
/WD
/WE
/TRAK0
/WP
/RDDATA
/HEAD
/DSKCHG
2 4 6 8
JP6
1
2
3
4
5
VCC
6 7
L
8 9 1
0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D7
D6
D5
D4
D3
D2
D1
D0
IOCHRD
AEN
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
JP12
1 3 5 7
2 3 4 5 6
JP5
/
C
S
0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
11
12
13
14
15
H
IRQ14
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D8
D9
D10
D11
D12
D13
D14
D15
XFDCEN
C9
470P
- 13 -
W83758F
Application circuit, continued
JP1
IDE CONNECTOR
JP2
GAME PORT
JP3
RS232-1 (COMA)
JP4
RS232-2 (COMB)
JP5
FDD CONNECTOR
C15
10u
JP7
LED CONNECTOR
JP8
JP10
JP12
H PDC DISABLE
L PDC ENABLE
JP14
PRINTER PORT
JP6
1 ABCHG
H AB CHG MODE
L NORMAL
2 FADSEL
H 3F0-3F7
L 370-377
DEFAULT :
C20
10u
JP9
1 2
L
L
H
H
L
L
H
H
H 3F6,3F7,1F0-1F7
L 376,377,170-177
5 FDC
H DISABLE
L ENABLE
-12V
C21
10u
C22
.1u
C17
.1u
CB2
.1u
CB1
.1u
+12V
C19
10u
JP11
RS232-1 (COMA)
ON
IRQ4
IRQ3
IRQ5
ON
ON
4
RS232-2 (COMB)
RS232-2 (COMB)
ON
IRQ3
IRQ4
IRQ5
ON
L COM3 (3E8H)
H COM2 (2F8H)
L COM4 (2E8H)
H DISABLE
5 6
L
L
H
H
RS232-1 (COMA)
C18
10u
L COM4 (2E8H)
H COM1 (3F8H)
L COM3 (3E8H)
H DISABLE
3 4
3 IDE
H DISABLE
L ENABLE
4 HADSEL
VCC
ON
7
PRINTER
ON
PRINTER
IRQ7
IRQ5
ON
L LPT3 (3BCH)
H LPT2 (278H)
L LPT1 (378H)
H DISABLE
JP8 SHORT
JP10 SHORT
JP11 1,4,7 SHORT
(COMA-IRQ4;COMB-IRQ3;PRT-IRQ7)
JP13 H
JP6 :
- 14 -
1
2
3
4
5
L
H
L
H
L
JP9 :
1
2
3
4
5
6
L
H
L
H
H
L
W83758F
PACKAGE DIMENSIONS
68-pin QFP
HD
D
52
64
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
51
E HE
33
19
Dimension in inches
Dimension in mm
---
---
0.130
---
---
0.004
---
---
0.10
---
---
0.107
0.112
0.117
2.73
2.85
2.97
0.014
0.016
0.020
0.35
0.40
0.50
0.004
0.006
0.010
0.10
0.15
0.25
0.546
0.551
0.556
13.87
14.00
14.13
0.782
0.787
0.792
19.87
20.00
20.13
0.033
0.039
0.045
0.85
1.00
1.15
0.728
0.740
0.752
18.49
18.80
19.10
3.30
0.964
0.976
0.988
24.49
24.80
25.10
0.039
0.047
0.055
1.00
1.20
1.40
0.087
0.094
0.103
2.21
2.40
2.62
---
---
0.004
---
---
0.10
---
12
---
12
Notes:
20
32
c
A2 A
See Detail F
Seating Plane
A1
L
L1
Detail F
Headquarters
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 15 -