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Verilog

1
Toma Sacco,Ph.D.

Introduction to Verilog
Verilog is a Hardware Description Language
(HDL)
o Behavioral Constructs
o Structural Constructs
Hierarchical description allows us to control
the complexity of a design
A bit may have the values: 1, 0, x, and z

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Toma Sacco,Ph.D.

Concatenation
The concatenation operator {, }
allows us to combine several wires or
vectors together to form a vector
{w3, w2, w1, w0}
Replication Operator
{3{A}} is equivalent to {A,A,A}
{2{C},3{A}} is equivalent to {C,C,A,A,A}

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Toma Sacco,Ph.D.

Procedural models
o They are only sensitive to the inputs they are
explicitly waiting for
o Control is transferred to a procedural
assignment statement in a sequential manner,
flowing from one statement to the next
o The flow of control can be interrupted by an
event (@) statement, wait statement, and #delay
statement

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Toma Sacco,Ph.D.

Assignments
Continuous assignment
o assign a= b&c ;
o Any time any of the inputs (b or c) changes, the
output a is re-evaluated
o The output can only drive nets (signals declared as
wire)

Procedural assignments
o = and <=
o The left-hand sides of all procedural assignments are
registers ( signals declared as reg)
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Toma Sacco,Ph.D.

timescale
The timescale compiler directive is used to
specify the time units of any delay operator (#)
`timescale 1ns/100ps
When placed before a module definition, then all
delay operators in that module and any module
that followed it would be in units of nanoseconds
and any time calculations would be internally
rounded to the nearest one hundred
picoseconds.
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Toma Sacco,Ph.D.

Representation of Numbers
Format:
<size_in_bits><radix_identifier><significant_digits>

type

Radix
identifier

binary
octal
hexadecimal

b
o
h

decimal

d
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Toma Sacco,Ph.D.

sized

unsized

12b101011100110

b100010110

12b1010_1110_0110

o426

12o5346

h116

12hAE6

278

12d2790
-4b101

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Toma Sacco,Ph.D.

Bitwise Operators
operator

operation

1s complement

&

AND

OR

XOR

~^ or ^~

XNOR
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Toma Sacco,Ph.D.

Logical Operators
operator

operation

NOT

&&

AND

||

OR

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Toma Sacco,Ph.D.

Relational operators
operator

operation

>

Greater than

<

Less than

>=

Greater than or equal

<=

Less than or equal

==

Equal to

!=

Not equal to
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Toma Sacco,Ph.D.

Verilog gates
gate

description

usage

and

f=(a.b ..)

and(f,a,b,)

nand

f=(a.b ..)

nand(f,a,b,)

or

f=(a +b+..)

or(f,a,b,)

nor

f=(a+b+..)

nor(f,a,b,)

xor
xnor

f =( a + b + .)
f =( a . b . .)

xor(f,a,b,)
xnor(f,a,b,)

not

f = a

not(f,a)

buf

f=a

buf(f,a)

notif0

f = (!e? a : bz)

notif0(f,a,e)

notif1

f = ( e? a : bz)

notif1(f,a,e)

bufif0

f = (!e? a : bz)

bufif0(f,a,e)

bufif1

f = ( e? a : bz)

bufif1(f,a,e)
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Toma Sacco,Ph.D.

Structural Modeling
Full adder using gates
module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
wire z1,z2,z3;
xor (s, x, y, Cin);
and (z1, x, y);
and (z2, x, Cin);
and (z3, y, Cin);
or (Cout, z1, z2, z3);
endmodule

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Toma Sacco,Ph.D.

module fulladd (Cin, x, y, s, Cout);


input Cin, x, y;
output s, Cout;
wire z1,z2,z3;
xor (s, x, y, Cin);
and (z1, x, y),
(z2, x, Cin),
(z3, y, Cin);
or (Cout, z1, z2, z3);
endmodule

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Toma Sacco,Ph.D.

Full adder using continuous assignment


module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
assign s = x ^ y ^ Cin;
assign Cout = (x & y) | (x & Cin) | (y & Cin);
endmodule

module fulladd (Cin, x, y, s, Cout);


input Cin, x, y;
output s, Cout;
assign s = x ^ y ^ Cin,
Cout = (x & y) | (x & Cin) | (y & Cin);
endmodule

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Toma Sacco,Ph.D.

Full adder
module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
assign {Cout, s} = x + y + Cin;
endmodule

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Toma Sacco,Ph.D.

Four-bit adder
x3 y3
carryout

FA
S3

x2 y2
C3

FA
S2

x1 y1
C2

FA
S1

x0 y0
C1

FA

carryin

S0

module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;
wire c1,c2,c3;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule

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Toma Sacco,Ph.D.

Vector signals
Signals on multiple wires can be represented as a vector
input [3:0] X, Y;
The individual bits can be referenced using index values in square brackets. For
example the most-significant bit of X is referred to as X[3].
module adder4 (carryin, X, Y, S, carryout);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;
fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);
fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);
endmodule

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Toma Sacco,Ph.D.

Grave accent character


`timescale 1ns / 1ps
module addt_v;
// Inputs
reg carryin;
reg [3:0] X,Y;
// Outputs
wire [3:0] S;
wire carryout;
adder4 uut (.carryin(carryin),.X(X),.Y(Y),.S(S),
.carryout(carryout));
initial begin
carryin = 0;X = 3;Y = 2;
#1 X=4; Y=7;
#1 Y=6;
#1 X=3; Y=5;
#1 Y=7;
end
endmodule

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Toma Sacco,Ph.D.

To declare and initialize a one-bit register in verilog we use the following


statement
reg one_bit_reg=1'b0;
Similarly, to declare and initialize a one dimension reg (e.g. 8-bit) we can write
reg [7:0] reg_len_8=8'd0;
We can declare a two dimensional array (e.g. 16x8-bit) as
reg [7:0] reg_dim_2 [15:0];

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Toma Sacco,Ph.D.

Generic Specification
Use of generic parameters allows the designer to scale the
system to any number of bits. The keyword parameter is
used to define the parameter.

Nets
A net represents a node in a circuit. A wire connects an
output of one logic element in a circuit to an input of another
element

Variables
Variables are used to describe a circuit in terms of its behavior. There are
two types of variables: reg and integer. All signals that are assigned a
value using procedural statements must be declared as variables by
using the reg or integer keywords.
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Toma Sacco,Ph.D.

Behavioral Modeling
module addern (carryin, X, Y, S, carryout);
parameter n=32;
input carryin;
input [n-1:0] X, Y;
When using a procedure
output [n-1:0] S;
to describe a combinational
output carryout;
circuit, make sure a value
reg [n-1:0] S;
is assigned to every signal
reg carryout;
no matter what path is taken
reg [n:0] C;
within the procedure.
integer k;
always @(X or Y or carryin)
begin
C[0] = carryin;
for (k = 0; k <= n-1; k = k+1)
begin
S[k] = X[k] ^ Y[k] ^ C[k];
C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]);
end
carryout = C[n];
end
endmodule
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Toma Sacco,Ph.D.

Arithmetic Assignment Statements


.

operator

operation

example

addition

C = A + B;

subtraction

C = A B;

2s complement

C = -A;

multiplication

division
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Toma Sacco,Ph.D.

n-bit adder
module addern (carryin, X, Y, S);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
assign S = X + Y + carryin;
endmodule

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Toma Sacco,Ph.D.

Carryout and overflow


Yn-1 Y0

Xn-1X0
..

..

Carryout Xn-1 Yn-1 Sn-1


C0

n-bit adder
.
Sn-1
S0

Cn

Xn-1 Yn-1 Sn-1

Carryout

Carryout = Xn-1Yn-1+Yn-1Sn-1+Xn-1Sn-1

Overflow

Overflow = Carryout ^ Xn-1 ^ Yn-1 ^ Sn-1

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Toma Sacco,Ph.D.

module addern (carryin, X, Y, S, carryout, overflow);


parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout, overflow;
assign S = X + Y + carryin;
assign carryout = (X[n-1] & Y[n-1]) | (X[n-1] & ~S[n-1]) | (Y[n-1] & ~S[n-1]);
assign overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1];
endmodule

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Toma Sacco,Ph.D.

module addern (carryin, X, Y, S, carryout, overflow);


parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout, overflow;
assign
assign
assign
assign

Sum = {1'b0,X} + {1'b0,Y} + carryin;


S = Sum[n-1:0];
carryout = Sum[n];
overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1];

endmodule

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Toma Sacco,Ph.D.

module addern (carryin, X, Y, S, carryout, overflow);


parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout, overflow;
assign {carryout, S} = X + Y + carryin;
assign overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1];
endmodule

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Toma Sacco,Ph.D.

`timescale 1ns / 1ps


module addt_v;
// Inputs
reg carryin;
reg [3:0] X,Y;
// Outputs
wire [3:0] S;
wire carryout, overflow;
addern uut (.carryin(carryin),.X(X),.Y(Y),.S(S),
.carryout(carryout).overflow(overflow));
initial begin
carryin = 0;X = 3;Y = 2;
#1 X=4; Y=-2;
#1 Y=6;
#1 X=-3; Y=-2;
#1 Y=-7;
end
endmodule

Toma Sacco,Ph.D.

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Toma Sacco,Ph.D.

`timescale 1ns / 1ps


//////////////////////////////////////////////////////////////////////////////////
// Company: CPP
// Engineer: Toma Sacco
//////////////////////////////////////////////////////////////////////////////////
module PAX(X,Y,S,ov,cout);
parameter n=4;
input [n-1:0] X,Y;
output [n-1:0]S;
output ov,cout;
wire coutn_1;
assign {coutn_1,S[n-2:0]} = {1'b0,X[n-2:0]} + Y[n-2:0];
assign {cout,S[n-1]}= {1'b0,X[n-1]} + Y[n-1]+ coutn_1;
assign ov= cout ^ coutn_1;
nndmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: CPP
// Engineer:Toma Sacco
//////////////////////////////////////////////////////////////////////////////////
module PAM(input [7:0] A,B,output coutput,output ov,output [7:0] Sum);
PAX #(8) sub1(A,B,Sum,ov,coutput);
endmodule

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Toma Sacco,Ph.D.

`timescale 1ns / 1ps


////////////////////////////////////////////////////////////////////////////////
// Company: CPP
// Engineer: Toma Sacco
////////////////////////////////////////////////////////////////////////////////
module test;
reg [7:0] A; reg [7:0] B;
wire coutput;wire ov;wire [7:0] Sum;
PAM uut (.A(A),.B(B),.coutput(coutput),.ov(ov),.Sum(Sum));
initial begin
A = 0;B = 0;
#1 A=50; B=60;
#1 A=-50; B=-60;
#1 A=50; B=-70;
#1 A=100; B=50;
#1 A=-90; B=-90;
end
endmodule
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Toma Sacco,Ph.D.

2x1 MUX using


the conditional operator
Conditional_expression? True_expression: false_expression
If the conditional expression evaluates to 1, then the value of the true
expression is chosen : otherwise, the value of the false_expression is
chosen.

w1

module mux2to1 (w0, w1, s, f);


input w0, w1, s;
output f;

2x1
MUX
f

w0
s

assign f = s ? w1 : w0;
endmodule

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Toma Sacco,Ph.D.

module mux2to1 (w0, w1, s, f);


input w0, w1, s;
output f;
reg f;
always @(w0 or w1 or s)
if (s==0)
f = w0;
else
f = w1;
endmodule

When using a procedure


to describe a combinational
circuit, make sure a value
is assigned to every signal
no matter what path is taken
within the procedure.

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Toma Sacco,Ph.D.

4x1
w3 MUX
4x1
w2

MUX

module mux4to1 (w0, w1, w2, w3, S, f);


f
input w0, w1, w2, w3;
w1
input [1:0] S;
output f;
w0
S0
reg f;
S1
always @(w0 or w1 or w2 or w3 or S)
if (S == 2'b00)
f = w0;
else if (S == 2'b01)
When using a procedure
f = w1;
to describe a combinational
circuit, make sure a value
else if (S == 2'b10)
is assigned to every signal
f = w2;
no matter what path is taken
else if (S == 2'b11)
within the procedure.
f = w3;
endmodule
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Toma Sacco,Ph.D.

module mux4to1 (W, S, f);


input [0:3] W;
input [1:0] S;
output f;
reg f;
always @(W or S)
case (S)
0: f = W[0];
1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase

When using a procedure


to describe a combinational
circuit, make sure a value
is assigned to every signal
no matter what path is taken
within the procedure.

endmodule
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Toma Sacco,Ph.D.

W15

w3
w2
w1
w0

4x1
MUX f
S1S0

w3
w2
w1
w0

4x1
MUX f
S1S0

w3
w2
w1
w0

4x1
MUX f
S1S0

Hierarchical
16x1 MUX

M3

M2

w3 4x1
w2 MUX
w1
w0 S1 S0

M1

M0

W1

w3
w2
w1
w0

4x1
MUX f
S1S0

S1

S0

S3

S2

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Toma Sacco,Ph.D.

module mux4to1 (W, S, f);


input [0:3] W;
input [1:0] S;
output f;
reg f;
always @(W or S)
case (S)
0: f = W[0];
1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase

module mux16to1 (W, S16, f);


input [0:15] W;
input [3:0] S16;
output f;
wire [0:3] M;
mux4to1 Mux1 (W[0:3], S16[1:0], M[0]);
mux4to1 Mux2 (W[4:7], S16[1:0], M[1]);
mux4to1 Mux3 (W[8:11], S16[1:0], M[2]);
mux4to1 Mux4 (W[12:15], S16[1:0], M[3]);
mux4to1 Mux5 (M[0:3], S16[3:2], f);
endmodule

endmodule

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Toma Sacco,Ph.D.

2x4 Decoder
En W1 W0

Y 3Y 2Y 1Y 0

0 x x

0 0 0 0

1 0 0

0 0 01

1 0 1

0 0 1 0

1 1 0

0 1 0 0

1 1 1

1 0 0 0

2x4
Decoder
En

w1
w0

Y3
Y2
Y1
Y0

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Toma Sacco,Ph.D.

module dec2to4 (W, Y, En);


input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
always @(W or En)
begin
if (En == 0)
Y = 4'b0000;
else
case (W)
0: Y = 4'b1000;
1: Y = 4'b0100;
2: Y = 4'b0010;
3: Y = 4'b0001;
endcase
end
endmodule

module dec2to4 (W, Y, En);


input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
always @(W or En)
case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
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Toma Sacco,Ph.D.

4x16 Decoder

2x4 Decoder

W1
W0

Y3
Y2
Y1
Y0

w1
w0
En

M3

2x4 Decoder

W3
W2
En

w1
w0
En

2x4 Decoder

M2

Y3
Y2
Y1
Y0

Y15

W1
W0

Y3
Y2
Y1
Y0

w1
w0
En
2x4 Decoder

M1

W1
W0

Y3
Y2
Y1
Y0

w1
w0
En

M0

2x4 Decoder

W1
W0

w1
w0
En

Y3
Y2
Y1
Y0

Y0

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Toma Sacco,Ph.D.

module dec2to4 (W, Y, En);


input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
integer k;
always @(W or En)
for (k = 0; k <= 3; k = k+1)
if ((W == k) && (En == 1))
Y[k] = 1;
else
Y[k] = 0;
endmodule

module dec4to16(W, Y, En);


input [3:0] W;
input En;
output [0:15] Y;
wire [0:3] M;
dec2to4 Dec1 (W[3:2], M[0:3], En);
dec2to4 Dec2 (W[1:0], Y[0:3], M[0]);
dec2to4 Dec3 (W[1:0], Y[4:7], M[1]);
dec2to4 Dec4 (W[1:0], Y[8:11], M[2]);
dec2to4 Dec5 (W[1:0], Y[12:15], M[3]);
endmodule

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Toma Sacco,Ph.D.

xyz
000
001
010
011
100
101
110
111

F
0
1
0
1
1
0
1
0

module TT(
input x,y,z,
output reg F
);
always@(*)
case({x,y,z})
1,3,4,6: F=1'b1;
default: F=0;
endcase
endmodule

module test;
reg x,y,z;
wire F;
TT uut (.x(x), .y(y), .z(z), .F(F));
initial begin
{x,y,z}=0;
repeat(7) #1 {x,y,z}= {x,y,z} +1;
end
endmodule

Toma Sacco,Ph.D.

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4-bit to 7-segment decoder


a
b
c
d
e
f
g

a
f

b
c

d
Common anode
7-segment
display
module conv(i, ss);
input [3:0] i;
output [6:0] ss;
reg
[6:0] ss;
always @ (i)
begin
case(i)

//abcdefg
0:ss = 7'b0000001 ;
1:ss = 7'b1001111 ;
2:ss = 7'b0010010 ;
3:ss = 7'b0000110 ;
4:ss = 7'b1001100 ;
5:ss = 7'b0100100 ;
6:ss = 7'b0100000 ;
7:ss = 7'b0001111 ;
8:ss = 7'b0000000 ;
9:ss = 7'b0000100
10:ss = 7'b0001000 ;
11:ss = 7'b1100000 ;
12:ss = 7'b0110001 ;
13:ss = 7'b1000010 ;
14:ss = 7'b0110000 ;
15:ss = 7'b0111000 ;
endcase
end
endmodule

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Toma Sacco,Ph.D.

`timescale 1ns / 1ps


//Seven-Segment driver for a common anode display
module sevensegment(input [3:0] B,output [6:0] ss);
reg [6:0]ROM [0:15];
Initial
begin
ROM[0]= 7'b0000001;
ROM[1]= 7'b1001111 ;
ROM[2]= 7'b0010010 ;
ROM[3]= 7'b0000110 ;
ROM[4]= 7'b1001100 ;
ROM[5]= 7'b0100100 ;
ROM[6]= 7'b0100000 ;
ROM[7]= 7'b0001111 ;
ROM[8]= 7'b0000000 ;
ROM[9]= 7'b0000100 ;
ROM[10]= 7'b0001000 ;
ROM[11]= 7'b1100000 ;
ROM[12]= 7'b0110001 ;
ROM[13]= 7'b1000010 ;
ROM[14]= 7'b0110000 ;
ROM[15]= 7'b0111000 ;
end
assign ss=ROM[B];
endmodule

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Toma Sacco,Ph.D.

`timescale 1ns / 1ps


module convt_v;
// Inputs
reg [3:0] i;
// Outputs
wire [6:0] ss;
// Instantiate the Unit Under Test (UUT)
conv uut (i, ss);
initial begin
// Initialize Inputs
i = 0;
repeat(15) #1 i = i + 1;
end
endmodule

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Toma Sacco,Ph.D.

Using a lookup table to determine the square of a 4-bit binary number


module squarer(
input [3:0] B,
output [7:0] SQ
);
localparam NL=16;
localparam Nb=8;
reg [Nb-1:0]ROM [0:NL-1];
integer i;
initial
begin
for (i = 0; i < 16; i = i+1)
begin
ROM[i]= i**2;
end
end
assign SQ=ROM[B];
endmodule

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49

module testsq;
reg [3:0] B;
wire [7:0] SQ;
// Instantiate the Unit Under Test (UUT)
squarer uut (
.B(B),
.SQ(SQ)
);
initial begin
// Initialize Inputs
B = 0;
#2 B = 1;
#2 B = 2;
#2 B = 4;
#2 B = 5;
#2 B = 10;
#2 B = 15;
end
endmodule

Toma Sacco,Ph.D.

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Arithmetic Logic Unit (ALU)


s 2 s1 s0
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

F
0000
B-A
A-B
A+B
A XOR B
A OR B
A AND B
1111

module alu(s, A, B, F);


input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;
always @(s or A or B)
case (s)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
endcase
endmodule

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Toma Sacco,Ph.D.

4-bit comparator
4
4

AgtB
EeqB

AltB

When using a procedure


to describe a combinational
circuit, make sure a value
is assigned to every signal
no matter what path is taken
within the procedure.

module compare (A, B, AeqB, AgtB, AltB);


input [3:0] A, B;
output AeqB, AgtB, AltB;
reg AeqB, AgtB, AltB;
always @(A or B)
begin
AeqB = 0;
AgtB = 0;
AltB = 0;
if(A == B)
AeqB = 1;
else if (A > B)
AgtB = 1;
else
AltB = 1;
end
endmodule

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Toma Sacco,Ph.D.

module B2BCD(B,hundreds,tens,ones);
input [7:0] B;
output [3:0] hundreds;
output [3:0] tens;
output [3:0] ones;
integer x;
reg [3:0] hundreds, tens, ones;

Binary To BCD
Converter

4
4
4

always @(B)
begin
x=B;
hundreds=0; tens=0; ones = 0;
if(x>99)begin hundreds =hundreds +1; x =x-100; end
if(x>99)begin hundreds =hundreds +1; x =x-100; end
repeat(9)
begin
if(x>9)begin tens = tens +1; x =x-10; end
end
ones =x;
end
endmodule

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Toma Sacco,Ph.D.

`timescale 1ns/1ps
module B2BCD_B2BCDt_v_tf();
reg [7:0] B;
// Outputs
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
// Instantiate the UUT
B2BCD uut (.B(B), .hundreds(hundreds), .tens(tens), .ones(ones));
// Initialize Inputs
initial begin
B = 0;
#1 B =155;
#1 B = 238;
#1 B= 43;
#1 B= 7;
end
endmodule

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Toma Sacco,Ph.D.

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Toma Sacco,Ph.D.

A
B

I0
8

op
module GPadd(cin,x,y,s,cout);
parameter n=4;
input [n-1:0] x,y;
input cin;
output [n-1:0] s;
output cout;
assign {cout,s}={1'b0,x}+y+cin;
endmodule

Y
I1 sel

cout

cout
x
y

cin

module GPmux(sel,I1,I0,Y);
parameter m=4;
input sel;
input [m-1:0] I1,I0;
output [m-1:0] Y;
assign Y=sel?I1:I0;
endmodule

module AddSub(input [7:0] A,B,input op,output [7:0] R,output cout);


wire [7:0] NB,Y;
assign NB = ~B;
GPmux #(8) device1(op,NB,B,Y);
GPadd #(8) device2(op,A,Y,R,cout);
endmodule
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Toma Sacco,Ph.D.

module systest;
reg [7:0] A;reg [7:0] B;reg op;
wire [7:0] R;wire cout;
AddSub uut (.A(A), .B(B), .op(op),
.R(R), .cout(cout));
initial begin
A = 0; B = 0; op = 0;
#2 A = 20;B = 55;op = 0;
#2 A = 77;B = 55;op = 1;
#2 A = 20;B = 55;op = 1;
end
endmodule

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