There are two factors that can affect the accuracy of the delays:

1. The crystal frequency

2. The AVR design
The idea of pipelining is to allow the CPU to fetch and execute at the same time.
In AVR, each instuction is executed in 3 stages:
Stage 1

Stage 2

Stage 3

Read Operands
Process
Write Back
In stage 1, the operand is fetched. In stage 2, the operation is performed. In step 3, the result is written
into the destination register.
The time taken for the CPU to execute an instrucion is referred as machine cycles.
Properties of instruction in the AVR:
1. 1-word (2-byte) or 2 word (4-byte)
2. Takes no more than one or two cycles to execute
3. The length of the machine cycle depends on the frequency of the oscillator connected to the
AVR system
The machine cycle for a system of 1MHz is 1s. (Refer instruction set)
Delay subroutine consists of two parts:
1. Setting a counter
2. A loop
One way to increase the delay is to use NOP(no operation) instructions in the loop. NOP simply waste
time but takes 2 bytes of program from ROM space which is too heavy for just one instuction cycle.
An alternate way is to use a nested loop.. To get more accurate delay, we use timers.
Comparison between using NOP and nested loop methods:
NOP
Coding
.INCLUDE M32DEF.INC
.ORG 0
LDI R16, HIGH
(RAMEND)
OUT SPH, R16
LDI R16,
LOW(RAMEND)
OUT SPL, R16
BACK:
LDI R16, 0x55
OUT PORTB, R16
RCALL DELAY
LDI R16, 0xAA
OUT PORTB, R16
RCALL DELAY
RJMP BACK
DELAY:
LDI R20, OxFF
AGAIN:
NOP
NOP
DEC R20
BRNE AGAIN
RET

Nested Loop
Instuction
Cycles

1
1
1
1
2/1
4

Instuction Cycles
DELAY:
R16, 200
AGAIN:
R17, 250
HERE:

LDI
LDI
NOP
NOP
DEC
R17
BRNE
HERE
DEC
R16
BRNE
AGAIN
RET

1
1
1
1
1
2/1
1
2/1
4