Note: Size of the memory always depends on the number of address lines.
Two separate units: Bus Interface Unit and Execution Unit
External Co processor (8087) supported
6 byte instruction queue present to help speed up instruction execution
Has multiplexed address and data bus
It consist two memory banks viz. odd memory bank and even memory bank
Segment registers:
There are 4 segment registers in the Bus interface unit, size of each segment register is 16
bits.
Segment registers give the base address (segment address) to select any memory segment.
Operand register or Temporary register:
It is a 16 bit register which can store 16 bit data. This register cannot be used by the
programmer/user. It is used by the p to store intermediate data or results therefore it is
called as temporary register.
Pointers and Index Registers:
The 16 bit register from where the p will take 16 bit effective address is called memory
pointer.
Also there are 2 index registers which have multiple purposes such as:
Note: The index registers are also a type of memory pointers but having multiple purpose
There are two index registers as follows:
Eg: When the instruction DIV BL is executed what the p does is that it divide
content of AX register with the content of BL register by default and after dividing the
4. DX (Data register): During multiplication and division operations when the result
goes beyond 16 bits i.e. 32bits, then the upper 16 bits are stored in the DX register.
Q5. Draw the flag register of 8086. Explain the status flags.
Carry Flag:
During an addition operation if a carry is generated from the MSB or during a subtraction
operation a borrow is generated carry flag sets indicating a carry or borrow respectively.
Therefore when
CF = 1; carry is generated
CF = 0; carry not generated
Auxiliary carry flag:
During an addition operation if a carry is generated from the lower nibble to the higher nibble,
then AC flag sets.
Parity flag:
When an addition, subtraction, multiplication, division or any logical operation takes place
then depending on the result the parity flag gets affected.
If the number of ones in the 8 LSBs are 0/2/4/6/8 then the parity flag sets i.e. PF = 1
indicating even parity
If the number of ones in the 8 LSBs are 1/3/5/7 then the parity flag resets i.e. PF = 0
indicating odd parity
Zero flag:
Whenever any arithmetic or logical operation takes place and the result is 0 then zero flag sets
to indicate that the result is 0 i.e. ZF = 1.
B = 80H
SUB B instruction is executed. The result obtained is 00H in A register. When p checks this
it has to reflect it somewhere that the result is zero, so it reflects in bit 7 which is reserved for
zero flag by setting its value to 1 i.e. ZF = 1
Sign flag:
Whenever the result of any arithmetic operation is negative the sign flag sets i.e. SF = 1 else
remain in the reset state i.e. SF = 0.
Q6. Draw the flag register of 8086 and explain the control flags.
Shown above is the internal circuitry to control the maskable interrupts. When Bit 10 of Flag
register is 0 i.e.
IF = 0, input to the AND gate is 0 therefore o/p of AND gate goes low. Therefore any input to
the AND gate wont be recognized hence any interrupt occurring on the INTR pin wont be
acknowledged as it is not recognized.
When IF = 1 and interrupt on the INTR pin occurs it is recognized and given to the internal
INTR circuitry through AND gate and then acknowledged.
Trap Flag (Bit 9):
This flag is used to detect any error in the program (debugging) by executing the program in
single stepping mode.
- If logic 0 is stored in TF, then the p will execute all the instructions of a program in one
operation (free run operation)
Eg: When we execute the program and press key F9, the entire program gets executed in one
stroke. The imp. Point to understand is that when we press the key F9, value 0 gets placed bit
9 of the flag register therefore Trap flag resets i.e. TF = 0.
- If logic 1 is stored in TF, then the p will execute one instruction of the program at a time,
after executing each instruction p will execute INT1 (software interrupt), so p will branch
from main program to subroutine.
The subroutine has a program which displays the result in different registers of p on the
screen, so after each instruction the programmer can verify the result.
Eg: We use F8 function key to execute the program in single stepping mode. When we press
key F8 value 1 gets placed into bit 9 of flag register, hence trap flag sets i.e. TF = 1.
In the above example we see two memory blocks. The offset address of first memory block is
placed in the SI register and offset address of the second memory block is placed in the DI
register.
Now we need to manually increment SI and DI after each byte transfer from data segment to
extra segment.
To avoid all this what we do is after moving one byte from Data segment to extra segment
we clear the direction flag (CLD instruction is used to clear the direction flag) which puts SI
and DI in auto increment mode.
In other words whenever DF = 0, SI and DI increment automatically.
If we are copying the data from the last location we set the direction flag (STD instruction is
used to set the direction flag) which puts the SI and DI in auto decrement mode.
In other words whenever DF = 1, SI and DI decrement automatically.
p 8086 has created 2 logical units within its architecture one is the bus interface unit (BIU)
and the other is the execution unit (EU).
While the EU is decoding an instruction or executing an instruction which does not require
the use of buses, the BIU fetches upto six bytes from the memory.
The BIU stores these prefetch bytes in FIFO register called as queue register.
When the EU is ready for the next instruction it simply takes (fetches) the next byte from the
instruction queue in the BIU.
This is much faster than sending out address to the system memory and waiting for memory
to send back the next instruction bytes.
This is a simple example of a car manufacturer which defines a person to make a car. Now
that person starts making the engine, then on its completion, he starts preparing the outer
body and continues.
We need to understand is that the person is completing one task and then starting another,
hence to manufacture one car will take a lot of time.
The manufacturer came up with an idea, that why not increase my staff. Instead of one staff
Ill make it 5.
First : Engine manufacture
Second : Body manufacture
Third : Seat manufacture
Fourth : Painting
Fifth : Tyre manufacture
Now what happens that the work got divided and each person is busy. After completion of
first module it goes to second and so on till the fifth.
So every module is continuously busy, and the work got divided.
1 person can do the work in 1 sec, now the work got divided, but first time all the modules
are in wait state and waiting for the previous one to complete i.e. M2 is waiting for M1 to
complete. So time taken is same i.e. 1s. But after the entire cycle is complete once, now the
time taken is only 0.2 sec.
Q8. List the steps in physical address generation in 8086 microprocessor. Calculate the
physical address for the given CS = 2340H, IP = 76A9H.
Since address bus is of 20 bits = Physical address is of 20 bits
The calculation is as follows:
Physical address (PA) = BA + EA
But addition is a little different, lets understand with an example:
Now base address is always appended with 0H i.e. 0000B at the end internally by the
p.
Now,
---------------------------------------------
= 10000H
3467H
13467H
---------------------------------------------
Now,
CS = BA = 2340H
IP = EA = 76A9H
PA = BA + EA
= 23400H = 0010 0011 0100 0000 0000
+
=
76A9H =
Q9. State the function of following assembly language programming tools. a. Editor b.
Assembler c. Linker d. Debugger
Editor:
It is used to type the assembly language statements for the program and save in a file.
The file containing the text of assembly language statements is called as source file
and has the extension .asm
Assembler:
Assembler is a software which reads the text from the source file, translates into
respective binary codes and saves into two files, one with the extension .obj called as
object file and one with the extension .lst called as list file.
The object file contains binary codes and addresses of the instructions.
The list file contains assembly language statements, binary codes, and offset address
for each instruction.
Linker:
Large assembly language programs are usually divided into many small modules.
The code for each module are separately developed, tested and finally linked into a
single large executable program.
The linker is used to join many object files into a single large object file.
Usually linker produces files with the extension .exe which can be directly loaded in
the memory and executed.
Debugger:
It enables the program to be loaded into the system memory, execute it and then
debug it. It also enables to insert breakpoints at any desired locations, change the
content of register, memory location and rerun the program.
Hence our main aim is to access a memory location and from there access data.
The main point to understand is that the size of the registers is 16 bit and address is of
20 bits.
The memory is divided into segments or blocks. The length of the segment is 64 Kb.
Two registers are used, one to access a segment and one to move within the segment
(select any location within the segment).
Select the segment with the help of base address or segment address (starting
address (indicating start of any segment). It means that the segment register contains
the base address with the help of which we are able to select any segment.
Now to move within the segment or in other words to select any location within the
segment we use offset address or effective address which we get from any pointer or
index register or any general purpose register.
Now these segments are logical segments, it means that there is no physical division within
the memory.
The segments can either be Code Segment, Data Segment, Extra Segment, Stack segment.
Code segment : when a segment is assigned as code segment, it is used to store the codes or
instructions
Data Segment : when a segment is assigned as data segment, it is used to store data used in
the programs
Extra Segment : it is also another segment used to store data
Stack Segment : it is used to store stack of data and address of main program during
subroutine call
When one instruction is getting decoded and executed and simultaneously next
instruction is being fetched from the memory is called as pipelining process.
In 8086 with the help of queue register 6 instruction bytes are prefetched in the queue
register, whenever the EU requires bytes for decoding and execution purpose it just
has to fetch from the queue register instead of going to the main memory and waist its
time.
By the time it is decoding and executing the byte fetched from the queue, p does not
allow the buses to remain idle, the external bus goes to the memory and fetches the
next bytes and places in the queue.
This is actually parallel processing and similar to a water pipe where the water
continues to remain in motion. Similar way the instruction bytes are in continuous
motion i.e. from the memory to the BIU then into the queue then to the execution unit
for execution.
In other words the motion of bytes does not stop anywhere ideally unless and until a
branch instruction arises in the queue.
Note: The p does not perform the next fetch operation till at least two bytes of the
instruction queue are emptied.
This is a simple example of a car manufacturer which defines a person to make a car. Now
that person starts making the engine, then on its completion, he starts preparing the outer
body and continues.
We need to understand is that the person is completing one task and then starting another,
hence to manufacture one car will take a lot of time.
1 person can do the work in 1 sec, now the work got divided, but first time all the modules
are in wait state and waiting for the previous one to complete i.e. M2 is waiting for M1 to
complete. So time taken is same i.e. 1s. But after the entire cycle is complete once, now the
time taken is only 0.2 sec.
These lines work as Address Bus (A16 A19) during T1 state of every machine cycle i.e.
when ALE signal goes high.
T2 onwards these work as status signals S3 to S6
S3 and S4 gives the status of the memory segment currently accessed.
S5 gives the status of Interrupt Flag.
S6 remains low in general.
Whenever those instructions arrive in the program which are dedicated to the co processor
then they are sent to the co processor for execution.
While the co processor is busy executing those instructions it sends a high signal on the
TEST pin of the p indicating that it is busy executing those instructions, till then the p
remains in idle state.
It is used along with M/IO pin to indicate whether memory write or io write operation.
M/IO (Pin 28):
This is an o/p pin used in minimum mode, to distinguish between a memory operation and io
operation.
When this pin is low it indicates io operation and is used with RD and WR.
For Eg. M/IO is high, and RD is also low whereas WR is high, then memory read operation
takes place.
For Eg. M/IO is high, and WR is also low whereas RD is high, then memory write operation
takes place.
In similar manner IO read and IO write operation takes place, only M/IO is low.
RQ0 / 0 , RQ 1 / 1 :
This signal works in the maximum mode when more than one processor is connected in the
system.
RQ stands for bus request. GT stands for bus grant.
0 has the higher priority than 1. It means that when two processors simultaneously asks the
8086 to release the system bus, the processor which is connected at pin 31 will get bus grant
first then the one which is connected at pin 30.
The external processor will send a low signal as a request to the p to release the system bus,
the p will complete its current machine cycle and release the bus i.e. it will grant the bus to
the bus master by sending a low signal.
After using the system bus again the external bus master will send a low signal thereby
releasing back the system bus to the p.
Q14. Draw the physical address calculation unit to generate 20 bit physical address.