[Type the document title]

LAB # 4(a)
Objective
To implement a D flip flop circuit by using data flow modeling.

Circuit Diagram

Coding
//Design module
module dff(q,qbar,d,clk);
input d,clk;
output q,qbar;
wire x,y;
assign x=(d&clk);
assign y=((~d)&clk);
assign q=~(x|qbar);
assign qbar=~(y|q);
endmodule
//stimulus module
module dffa;
reg d,clk;
wire q,qbar;
dff ff(q,qbar,d,clk);
initial
clk=1'b1;
always #5

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clk=~clk;
initial
begin
d=1'b0;
#20
d=1'b1;
#20
$finish;
end
endmodule

Truth Table

Timing Diagram

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LAB # 4(b)
Objective
Write the following expression for the circuit by using data flow modeling:
Sum = a.b.cin + a.b.cin + a.b.cin + a.b.cin
Cout = a.b + b.cin + a.cin

Circuit Diagram

Coding
//Design module
module fa(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
assign sum =((a&b&cin)|((~a)&b&(~cin))|((~a)&(~b)&cin)|(a&(~b)&(~cin)));
assign cout=((a&b)|(b&cin)|(a&cin));
endmodule
//stimulus module
module test;
reg a,b,cin;
wire sum,cout;
fa adder(sum,cout,a,b,cin);

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initial
begin
cin=1'b0;
a=1'b0; b=1'b0;
#20
a=1'b0; b=1'b1;
#20
a=1'b1; b=1'b0;
#20
a=1'b1; b=1'b1;
#20
$finish;
end
endmodule

Truth Table

Timing Diagram

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LAB # 4(c)
Objective
To implement a Master Slave flip flop by using data flow modeling.

Circuit Diagram

Coding
//Design module
module msjk(q,qbar,j,k,clk,clear);
input j,k,clk,clear;
output q,qbar;
wire a,b,y,ybar,c,d;
assign a =~(qbar&j&clk&clear);
assign b
=~(q&clk&k);
assign y =~(a&ybar);
assign ybar =~(b&clear&y);
assign c =~(y&(~clk));
assign d
=~(ybar&(~clk));
assign q
=~(c&qbar);
assign qbar =~(d&clear&q);
endmodule
//stimulus module
module test;
reg j,k,clear,clk;
wire q,qbar;

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msjk ff(q,qbar,j,k,clk,clear);
initial
clk=1'b1;
always #5
clk=~clk;
initial
begin
clear=1'b0;
#20
clear=1'b0;
#20
clear=1'b0;
#20
clear=1'b0;
#20
clear=1'b1;
#20
clear=1'b1;
#20
clear=1'b1;
#20
clear=1'b1;
#20
$finish;
end
endmodule

j=1'b0; k=1'b0;
j=1'b0; k=1'b1;
j=1'b1; k=1'b0;
j=1'b1; k=1'b1;
j=1'b0; k=1'b0;
j=1'b0; k=1'b1;
j=1'b1; k=1'b0;
j=1'b1; k=1'b1;

Truth Table
J
0
0
1
1

K
0
1
0
1

Q
Q
0
1
Q

Q
Q
1
0
Q

Comments
No change
Reset
Set
Toggle

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Timing Diagram

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LAB # 4(d)
Objective
Design a synchronous 4-bit counter using master slave JK flip flop.

Circuit Diagram

Coding
//Design module
module msjk(q,qbar,j,k,clk,clear);
input j,k,clk,clear;
output q,qbar;
wire a,b,y,ybar,c,d;
assign a =~(qbar&j&clk&clear);
assign b =~(q&clk&k);
assign y =~(a&ybar);
assign ybar =~(b&clear&y);
assign c =~(y&(~clk));
assign d =~(ybar&(~clk));
assign q =~(c&qbar);
assign qbar =~(d&clear&q);
endmodule
//4 bit counter design module
module counter(q,qbar,j,k,clk,clear);

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input j,k;
input clk,clear;
output [3:0]q,qbar;
msjk m0(q[0],qbar[0],1,1,clk,clear);
msjk m1(q[1],qbar[1],q[0],q[0],clk,clear);
msjk m2(q[2],qbar[2],q[0]&q[1],q[0]&q[1],clk,clear);
msjk m3(q[3],qbar[3],q[0]&q[1]&q[2],q[0]&q[1]&q[2],clk,clear);
endmodule
//stimulus module
module test;
reg j,k,clear,clk;
wire [3:0]q,qbar;
counter ff(q,qbar,j,k,clk,clear);
initial
clk=1'b1;
always #5
clk=~clk;
initial
clear = 1'b0;
always #5
clear = 1'b1;
initial
begin
j=1'b0; k=1'b0;
#20
j=1'b0; k=1'b1;
#20
j=1'b1; k=1'b0;
#20
j=1'b1; k=1'b1;
#20
$finish;
end
endmodule

Truth Table
Q1

Q2

Q3

Q4

Decimal

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Equivalent

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Timing Diagram

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15