Code No: A5711

NR
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABAD
M.Tech I Semester Regular Examinations, March 2009
MODELLIGN AND SYNTHESIS WITH VERILOG HDL
(VLSI System Design)
Time:3 hours. Max.marks:60

Answer any Five questions

All questions carry equal marks
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1.a) What type of statement is used to describe a design in the data flow style?
b) List out the verilog primitives and briefly explain about them.

2.a) What are the two kinds of delays that can be specified in a procedural assignment
statement? Elaborate using an example.
b) Write a verilog code in structural style for the 2 to 4 decodes.

3.a) Write verilog HDL model of a masterslave flipflop using gate level description.
b) Explain the min:typ:max form of delay for a gate with an example.
c) What are the conditional operators in verilog HDL language? Explain them with
an example.

4.a) Write verilog code to describe the following function.

f = x1 x3 + x2 x3 + x3 x4 + x1 x2 + x1 x4
b) Write a user defined primitive description for the priority encoder.

5.a) When there are two or more assignments to the same target, how is the effective
value for the target determined.
b) What is the difference between a sequential block and a parallel block statements?
Can a sequential block appear with in a parallel block? Explain.

6.a) Describe the behavior of a majority circuit. The input is a 12 bit vector. If number
of 1’s exceeds the number of 0’s, the output is sterol. The input data is checked
only when ‘Ready’ is ‘1’.
b) Design a Finite state machine which can detect 11011 sequence in verilog HDL.

7.a) Design an universal shift register by writing a verilog code.

b) Write a verilog model for a N-bit counter with a ‘hold’ control. If hold is 1, the
counter holds its value, when hold is 0, the counter is reset to 0 and starts counting
again

8. Write a brief note on:

a) Synthesis of ‘IF fork join blocks’
b) CMOS transmission gates.

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