Digital Logic Design

Combinational Logic

Mustafa Kemal Uygurolu

Combinational Circuits
Output is function of input only
i.e. no feedback

n inputs

Combinational
Circuits

m outputs

When input changes, output may change (after a delay)

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Combinational Circuits
Analysis
Given a circuit, find out its function

Function may be expressed as:

Boolean function
Truth table

Design
Given a desired function, determine its circuit
Function may be expressed as:
Boolean function

Truth table
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Analysis Procedure
Boolean Expression Approach
T2=ABC

T1=A+B+C

T3=AB'C'+A'BC'+A'B'C

F2=(A+B)(A+C)(B+C)

F2=AB+AC+BC

F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC

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Analysis Procedure
Truth Table Approach
=0
=0
=0

=0
=0
=0

=0
=0

=0
=0

=0
=0

A B C
0 0 0

F1

F2

0
1

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Analysis Procedure
Truth Table Approach
=0
=0
=1

=0
=0
=1

=0
=0

=0
=1

=0
=1

A B C
0 0 0
0 0 1

F1
0
1

F2
0
0

1
1

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Analysis Procedure
Truth Table Approach
=0
=1
=0

=0
=1
=0

=0
=1

=0
=0

=1
=0

A
0
0
0

B
0
0
1

C
0
1
0

F1
0
1
1

F2
0
0
0

1
1

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Analysis Procedure
Truth Table Approach
=0
=1
=1

=0
=1
=1

=0
=1

=0
=1

=1
=1

A
0
0
0
0

B
0
0
1
1

C
0
1
0
1

F1
0
1
1
0

F2
0
0
0
1

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Analysis Procedure
Truth Table Approach
=1
=0
=0

=1
=0
=0

=1
=0

=1
=0

=0
=0

1
1

A
0
0
0
0
1

B
0
0
1
1
0

C
0
1
0
1
0

F1
0
1
1
0
1

F2
0
0
0
1
0

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Analysis Procedure
Truth Table Approach
=1
=0
=1

=1
=0
=1

=1
=0

=1
=1

=0
=1

0
0

A
0
0
0
0
1
1

B
0
0
1
1
0
0

C
0
1
0
1
0
1

F1
0
1
1
0
1

F2
0
0
0
1
0

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Analysis Procedure
Truth Table Approach
=1
=1
=0

=1
=1
=0

=1
=1

=1
=0

=1
=0

0
0

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A
0
0
0
0
1
1
1

B
0
0
1
1
0
0
1

C
0
1
0
1
0
1
0

F1
0
1
1
0
1
0

F2
0
0
0
1
0
1

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Analysis Procedure
Truth Table Approach
=1
=1
=1

=1
=1
=1

=1
=1

=1
=1

=1
=1

A
0
0
0
0
1
1
1
1

0
0

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

B
A

0
1

1
0

0
1

F1
0
1
1
0
1
0
0

F2
0
0
0
1
0
1
1

B
1
0

0
0

0
1

1
1

0
1

F1=AB'C'+A'BC'+A'B'C+ABC

F2=AB+AC+BC

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Design Procedure
Given a problem statement:
Determine the number of inputs and outputs
Derive the truth table
Simplify the Boolean expression for each output
Produce the required circuit

Example:
Design a circuit to convert a BCD code to Excess 3 code
4-bits
0-9 values

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4-bits
Value+3
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Design Procedure
BCD-to-Excess 3 Converter
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

w
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x

x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x

y
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x

z
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x

x
1

1
x
1

1
x
x

C
1
x
x

1
x

x
1

x
x

x
x

w = A+BC+BD

x = BC+BD+BCD

1
1
x
1

1
1
x
x

x
x

1
1
x
1

D
y = CD+CD
Eastern Mediterranean

x
x

1
1
x
x

D
z = D
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Design Procedure
BCD-to-Excess 3 Converter
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

w
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x

x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x

y
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x

z
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x

w = A + B(C+D)
x = B(C+D) + B(C+D)
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y = (C+D) + CD
z = D
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Seven-Segment Decoder
w
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

abcdefg
1111110
0110000
1101101
1111001
0110011
1011011
1011111
1110000
1111111
1111011
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx

a
w
x
y
z

a
b
c
d
e
f
g

b
c

BCD code

y
1

x
1

1
1
x
x

1
x
1

1
1
x
x

z
a = w + y + xz + xz
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b=...
c=...
d=...

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Binary Adder
Half Adder

x
y

Adds 1-bit plus 1-bit

Produces Sum and Carry

x y
0
0
1
1

0
1
0
1

C
0
0
0
1

S
0
1
1
0

HA

S
C

x
+ y

C S

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Binary Adder
Full Adder

x
y
z

Adds 1-bit plus 1-bit plus 1-bit

Produces Sum and Carry

x y
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

z
0
1
0
1
0
1
0
1

C
0
0
0
1
0
1
1
1

S
0
1
1
0
1
0
0
1

y
x

0
1

1
0

0
1

1
0

FA

S
C

x
+ y
+ z

C S

z
S = xy'z'+x'yz'+x'y'z+xyz = x y z
y
x

0
0

0
1

1
1

0
1

z
C = xy + xz + yz
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Binary Adder
Full Adder

S = xy'z'+x'yz'+x'y'z+xyz = x y z
C = xy + xz + yz

S
x

y
z

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Binary Adder
Full Adder
x
y

HA

HA

S
C

x
S
y

z
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Binary Adder
x3x2x1x0

y3y2y1y0

Binary Adder

Cy

C0

Carry
Propagate
Addition

c3 c2 c1 .
+ x3 x2 x1 x0
+ y3 y2 y1 y0

Cy S3 S2 S1 S0

S3S2S1S0

x3

x2

y3

x1

y2

x0
y0

y1

0
FA
C4

S3

FA
C3

S2

FA
C2

S1

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FA
C1

S0

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Binary Adder
Carry Propagate Adder
x7 x6 x5 x4

y7 y6 y5 y4

A3 A2 A1 A0 B3 B2 B1 B0
Cy

CPA

C0

x3 x2 x1 x0

y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy

CPA

S3 S2 S1 S0

S3 S2 S1 S0

S7 S6 S5 S4

S3 S2 S1 S0

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C0

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 Carry propagation
When the correct outputs are available
The critical path counts (the worst case)
(A1, B1, C1) C2 C3 C4 (C5, S4)
When 4-bits full-adder 8 gate levels (n-bits: 2n gate
levels)

Figure 4.10 Full Adder with P and G Shown

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Parallel Adders
Reduce the carry propagation delay
Employ faster gates
Look-ahead carry (more complex mechanism, yet faster)
Carry propagate: Pi = AiBi
Carry generate: Gi = AiBi
Sum: Si = PiCi
Carry: Ci+1 = Gi+PiCi
C0 = Input carry
C1 = G0+P0C0
C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0
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Carry Look-ahead Adder (1/2)

Logic diagram

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

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Carry Look-ahead Adder (2/2)

4-bit carry-look
ahead adder
Propagation delay
of C3, C2 and C1 are
equal.

Fig. 4.12 4-Bit Adder with Carry Look-ahead

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BCD Adder
4-bits plus 4-bits
Operands and Result: 0 to 9
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy
0+0 0 0 0 0 0 0 0 0 =0 0
0+1 0 0 0 0 0 0 0 1 =1 0
0+2 0 0 0 0 0 0 1 0 =2 0

S3 S2 S1 S0
0 0 0 0
0 0 0 1
0 0 1 0

0+9
1+0
1+1

0 0 0 0
0 0 0 1
0 0 0 1

1 0 0 1
0 0 0 0
0 0 0 1

=9
=1
=2

0
0
0

1 0 0 1
0 0 0 1
0 0 1 0

1+8
1+9
2+0

0 0 0 1
0 0 0 1
0 0 1 0

1 0 0 0
1 0 0 1
0 0 0 0

=9 0
=A 0
=2 0

1 0 0 1
1 0 1 0
0 0 1 0

9+9

1 0 0 1

1 0 0 1 = 12 1

0 0 1 0

0001 Mediterranean
1000
Eastern

+ x3 x2 x1 x0
+ y3 y2 y1 y0

Cy S3 S2 S1 S0

Invalid Code
Wrong BCD Value
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BCD Adder
X +Y

x3 x2 x1 x0

y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9+0
9+1
9+2
9+3
9+4
9+5
9+6
9+7
9+8
9+9

1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

=9
= 10
= 11
= 12
= 13
= 14
= 15
= 16
= 17
= 18

0
0
0
0
0
0
0
1
1
1

1
1
1
1
1
1
1
0
0
0

0
0
0
1
1
1
1
0
0
0

0
1
1
0
0
1
1
0
0
1

1
0
1
0
1
0
1
0
1
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
1
1
1
1
1
1
1
1
1

1
0
0
0
0
0
0
0
0
1

0
0
0
0
0
1
1
1
1
0

0
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0

=9
= 16
= 17
= 18
= 19
= 20
= 21
= 22
= 23
= 24

+6
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BCD Adder
Correct Binary Adders Output (+6)
If the result is between A and F
If Cy = 1
S3 S2 S1 S0
0 0 0 0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Err
0
0
0
1
1
1
1
1
1

S1

S3

1
1

1
1

S2

S0
Err = S3 S2 + S3 S1

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BCD Adder

Err

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Binary Subtractor
Use 2s complement with binary adder
x y = x + (-y) = x + y + 1

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Binary Adder/Subtractor
M: Control Signal (Mode)
M=0 F = x + y
M=1 F = x y

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Overflow
Unsigned Binary Numbers
x3

x2

y3

x1
y2

x0
y1

y0
0

FA

Carry

C4

S3

FA
C3

2s Complement Numbers
x3

S2

FA
C2

x2

y3

S1

FA
C1

x1
y2

S0
x0

y1

y0
0

FA

Overflow

C4

S3

FA
C3

S2

FA
C2

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S1

FA
C1

S0

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Magnitude Comparator
Compare 4-bit number to 4-bit number
3 Outputs: < , = , >
Expandable to more number of bits

x3 A3 B3 A3 B3
x2 A2 B2 A2 B2
x1 A1 B1 A1 B1

A3A2A1A0 B3B2B1B0
Magnitude
Comparator

x0 A0 B0 A0 B0
A<B A=B A>B
( A B ) x3 x2 x1 x0
( A B) A3 B3 x3 A2 B2 x3 x2 A1 B1 x3 x2 x1 A0 B0
( A B ) A3 B3 x3 A2 B2 x3 x2 A1 B1 x3 x2 x1 A0 B0
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Magnitude Comparator

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Magnitude Comparator
x7 x6 x5 x4

0
1
0

y7 y6 y5 y4

A3 A2 A1 A0 B3 B2 B1 B0

I(A>B)
Magnitude
I(A=B)
Comparator
I(A<B)
A<B A=B A>B

x3 x2 x1 x0

y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0

I(A>B)
Magnitude
I(A=B)
Comparator
I(A<B)
A<B A=B A>B

A<B A=B A>B

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Decoders
Extract Information from the code
Binary Decoder

Only one
lamp will
turn on

Example: 2-bit Binary Number

x1
x0

0
0

1
0
Binary
Decoder 0
0
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Decoders

I1
I0
I1 I0
0
0
1
1

0
1
0
1

Binary
Decoder

2-to-4 Line Decoder

y3
y2
y1
y0

Y3 Y2 Y1 Y0
0
0
0
1

0
0
1
0

0
1
0
0

1
0
0
0

Y3 I1 I 0

Y2 I1 I 0

Y1 I1 I 0

Y0 I1 I 0

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Decoders
3-to-8 Line Decoder

I 2 I1 I 0

I2
I1
I0

Binary
Decoder

I 2 I1 I 0

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

I 2 I1 I 0
I 2 I1 I 0
I 2 I1 I 0
I 2 I1 I 0
I 2 I1 I 0
I 2 I1 I 0

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Decoders

Binary
Decoder

Enable Control
I1
I0
E

Y3
Y2
Y1
Y0

I1 I0

Y3 Y2 Y1 Y0

0
1
1
1
1

x
0
0
1
1

0
0
0
0
1

x
0
1
0
1

0
0
0
1
0

0
0
1
0
0

0
1
0
0
0
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Decoders
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
1
0

0
0
0
0
0
1
0
0

0
0
0
0
1
0
0
0

0
0
0
1
0
0
0
0

0
0
1
0
0
0
0
0

0
1
0
0
0
0
0
0

1
0
0
0
0
0
0
0

Eastern Mediterranean

I0
I1
E

I0
I1
E

Binary
Decoder

I2 I1 I0

Y3
Y2
Y1
Y0

Binary
Decoder

I2 I1 I0

Expansion

Y3
Y2
Y1
Y0

Y7
Y6
Y5
Y4

Y3
Y2
Y1
Y0

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Decoders
Active-High / Active-Low
I1 I0 Y3 Y2 Y1 Y0

I1 I0 Y3 Y2 Y1 Y0

0
0
1
1

0
0
1
1

I0

0
0
1
0
Y3
Y2
Y1
Y0

0
1
0
0

1
0
0
0

I1
I0

0
1
0
1

Binary
Decoder

I1

0
0
0
1

Binary
Decoder

0
1
0
1

1
1
1
0

1
1
0
1

1
0
1
1

0
1
1
1

Y3
Y2
Y1
Y0

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Implementation Using Decoders

Each output is a minterm
All minterms are produced

Binary
Decoder

Sum the required minterms

Example: Full Adder

S(x, y, z) = (1, 2, 4, 7)
C(x, y, z) = (3, 5, 6, 7)

x
y
z

I2
I1
I0

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

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Implementation Using Decoders

x
y
z

Binary
Decoder

Binary
Decoder

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

I2
I1
I0

x
y
z

I2
I1
I0

C
Eastern Mediterranean

C
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Encoders
Put Information into code

Only one
switch
should be
activated
at a time

Binary Encoder
Example: 4-to-2 Binary Encoder

x1
x2
x3

Binary
Encoder

y1
y0

x3 x2 x1

y1 y0

0
0
0
1

0
0
1
1

Eastern Mediterranean

0
0
1
0

0
1
0
0

0
1
0
1

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 Octal-to-Binary Encoder (8-to-3)

I7
0
0
0
0
0
0
0
1

I6
0
0
0
0
0
0
1
0

I5
0
0
0
0
0
1
0
0

I4
0
0
0
0
1
0
0
0

I3
0
0
0
1
0
0
0
0

I2
0
0
1
0
0
0
0
0

I1
0
1
0
0
0
0
0
0

I0
1
0
0
0
0
0
0
0

Y2 Y1 Y0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

I7
I6
I5
I4
I3
I2
I1
I0

Binary
Encoder

Encoders

Y2
Y1
Y0

Y2 I 7 I 6 I 5 I 4
Y1 I 7 I 6 I 3 I 2
Y0 I 7 I 5 I 3 I1

Eastern Mediterranean

46 / 65

Priority Encoders

I3 I2 I1 I0
0
0
0
0
1

0
0
1
x
x

I1

Y1

I3

0
0
0
1
x

1 1 1 1
1 1 1 1
1 1 1 1

I0

0
1
x
x
x

I3
I2
I1
I0

Y1 Y0 V
0 0 0
0 0 1
0 1 1
1 0 1
1 1 1

Priority
Encoder

4-Input Priority Encoder

V
Y1
Y0

Y1 I 3 I 2
I2

Y0 I 3 I 2 I1
V I 3 I 2 I1 I 0
Eastern Mediterranean

47 / 65

Encoder / Decoder Pairs

Binary
Encoder
I7
I6
I5
I4
I3
I2
I1
I0

Binary
Decoder

Y2
Y1
Y0

I2
I1
I0

Eastern Mediterranean

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

48 / 65

Multiplexers

S1 S0
0
0
1
1

0
1
0
1

Y
I0
I1
I2
I3

Eastern Mediterranean

I0
I1
MUX Y
I2
I3 S1 S0
49 / 65

Multiplexers
2-to-1 MUX
I0
MUX Y
I1
S

4-to-1 MUX
I0
I1
MUX Y
I2
I3 S1 S0
Eastern Mediterranean

50 / 65

Multiplexers
Quad 2-to-1 MUX
x3
x2

x1

x0

y3

I0
MUX Y
I1
S

y2

I0
MUX Y
I1
S

A3
A2
A1
A0

I0
MUX Y
I1
S

y1

Y3
Y
MUX 2
Y1
B3
Y0
B2
B1
B0 S E

I0
MUX Y
I1
S
S
Eastern Mediterranean

51 / 65

Multiplexers
Quad 2-to-1 MUX
A3
A2
A1
A0

Y3
MUX Y2
Y1
B3
Y0
B2
B1
B0 S E
Extra
Buffers
Eastern Mediterranean

52 / 65

Implementation Using Multiplexers

Example
F(x, y) = (0, 1, 3)
x y

0
0
1
1

1
1
0
1

0
1
0
1

1
1
0
1

I0
I1
MUX Y
I2
I3 S1 S0

x y

Eastern Mediterranean

53 / 65

Implementation Using Multiplexers

Example
F(x, y, z) = (1, 2, 6, 7)
x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

F
0
1
1
0
0
0
1
1

0
1
1
0
0
0
1
1

I0
I1
I2
I3 MUX Y
I4
I5
I6
I7 S2 S1 S0

x y z
Eastern Mediterranean

54 / 65

Implementation Using Multiplexers

Example
F(x, y, z) = (1, 2, 6, 7)
x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

F
0
1
1
0
0
0
1
1

F=z
F=z

z
z
0
1

I0
I1
MUX Y
I2
I3 S1 S0

F=0

x y

F=1
Eastern Mediterranean

55 / 65

Implementation Using Multiplexers

Example
F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

F
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1

F=1

I0
I1
I2
I3 MUX Y
I4
I5
I6
I7 S2 S1 S0

F=1

A B C

F=0

D
D
D
0
0
D
1

F=D

F=D
F=D
F=D
F=0

Eastern Mediterranean

56 / 65

Multiplexer Expansion
8-to-1 MUX using Dual 4-to-1 MUX
I0
I1
I2
I3

I4
I5
I6
I7

I0
I1
MUX Y
I2
I3 S1 S0
I0
I1
MUX Y
I2
I3 S1 S0
1 0 0
S2 S1 S0

I0
MUX Y
I1
S

Eastern Mediterranean

57 / 65

DeMultiplexers
Y3
Y2
I DeMUX
Y1
S1 S0 Y0

S1 S0

Y 3 Y2 Y1 Y 0

0
0
1
1

0
0
0
I

0
1
0
1

Eastern Mediterranean

0
0
I
0

0
I
0
0

I
0
0
0
58 / 65

Multiplexer / DeMultiplexer Pairs

MUX

DeMUX

I7
I6
I5
I4 Y
I3
I2
I1
SI20 S1 S0

Y7
Y6
Y5
Y4
I
Y3
Y2
Y1
Y0
S2 S1 S0

x2 x1 x0

Synchronize
Eastern Mediterranean

y2 y 1 y0
59 / 65

Y3
Y2
I DeMUX
Y1
S1 S0 Y0

I1
I0
E

S1 S0

Y3 Y 2 Y 1 Y0

0
0
1
1

0
0
0
I

0
1
0
1

0
0
I
0

0
I
0
0

I
0
0
0

Binary
Decoder

DeMultiplexers / Decoders
Y3
Y2
Y1
Y0

I1 I 0

Y3 Y2 Y1 Y0

0
1
1
1
1

x
0
0
1
1

0
0
0
0
1

x
0
1
0
1

Eastern Mediterranean

0
0
0
1
0

0
0
1
0
0

0
1
0
0
0
60 / 65

Three-State Gates
Tri-State Buffer
A

C A

0 x
1 0
1 1

Hi-Z
0
1

C
A

Tri-State Inverter
C

Eastern Mediterranean

61 / 65

Three-State Gates
C D

A
Y

C
B

0
0
1
1

0
1
0
1

Hi-Z
B
A
?
Not Allowed

D
A
C

Y=

if C = 1

if C = 0

B
Eastern Mediterranean

62 / 65

Three-State Gates
I3
I2
Y
I1

S1
S0
E

I1
I0
E

Binary
Decoder

I0
Y3
Y2
Y1
Y0

Eastern Mediterranean

63 / 65