Lesson 2

Advanced Aspects of Digital Logic

Sept. 2005

EE37E Adv. Digital

Electronics

Topics

Fundamental Concepts
Hazards
FSM Design
Timing, Clock issues, and Metastability
Pipelining and Power Estimation

Sept. 2005

EE37E Adv. Digital

Electronics

Fundamental Concepts
We can classify digital logic circuits in three groups:
Pure Combinational circuits (i.e. mux, decoder, encoder, etc)
Pure sequential circuits (DFF, JKFF, D-Latch, ripple counter, shift
register, etc)
Mixed combinational-sequential circuits also called sequential
circuits (up/down counter, universal register, ram, FIFO, etc).

On the most important aspect of sequential circuits lies

in their mode of operation:
Synchronous (use of a clock)
Asynchronous (self-time operation)
Globally asynchronous Locally synchronous (combination of
asynchronous and synchronous techniques)

Sept. 2005

EE37E Adv. Digital

Electronics

The synchronous design paradigm

A system is said to operate synchronously if all
memory operations are triggered on a common
grid which is defined by the status of a global
signal referred to as clock.
A property making synchronous systems easy to
design and verify is, that all (local) timing issues
are related to a common global clock and delay
properties are only subject to one-sided
constraints.

Sept. 2005

EE37E Adv. Digital

Electronics

Asynchronous design techniques

The concept of discrete time steps, which is the root of synchronous

paradigm, is given up and has to be substituted by some other datavalid signaling schemes.
Proponents of asynchronous design styles claim some major
advantages:
Easing of global timing issues and no clock skew problems.
Lower power consumption
Automatic adaptation to properties (temperature, supply etc.)
Modularity of designs
Better technology migration potential.

Almost 99% of digital circuits are synchronous. But we believe that

this figure will change drastically in the years to come.
This lesson and others to come will focus only on synchronous
design methods.
The GALS architecture is composed of modules that are
synchronized to a local clock whereas interactions between those
modules are based on an asynchronous protocol. Thus the global
clock net is eliminated, which reduces power consumption.
Sept. 2005

EE37E Adv. Digital

Electronics