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rouiter design using verilog
Descriptiondesign router using verilog.design a 1x3 router using verilog.
By udimudi 20150110

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/************************************************************************
MAVENSILICONCONFIDENTIALThisisanunpublished,proprietarywork
ofMavenSiliconSoftechPvt.Ltd.,Bangalore,andisfullyprotected
undercopyrightandtradesecretlaws.Youmaynotview,use,disclose,
copy,ordistributethisfileoranyinformationcontainedhereinexcept
pursuanttoavalidwrittenlicensefromMavenSiliconSoftechPvt.Ltd.,
Bangalore

DesignName:router_1X3
ModuleName:router_reg
Date:19/09/2009
Description:Thismodulecontainsallthestatus,data
parityregistersrequiredbyrouter_1x3
Author:PRSIVAKUMAR
Email:siva@vlsitraining.com
Company:MavenSilicon,Bangalorewww.vlsitraining.com
Version:1.0revision0.0
*************************************************************************/
modulerouter_reg(clock,
resetn,
packet_valid,
data_in,
fifo_full,
detect_add,
lfd_state,
ld_state,
lp_state,
laf_state,
full_state,
reset_int_reg,
parity_done,
low_packet_valid,
dout,
err
);

inputclock;
inputresetn;
inputpacket_valid;
input[7:0]data_in;
inputfifo_full;
inputreset_int_reg;
inputdetect_add;
inputld_state;
inputlp_state;
inputlfd_state;
inputlaf_state;
inputfull_state;

outputparity_done;
outputlow_packet_valid;
output[7:0]dout;
outputerr;

regparity_done;
reglow_packet_valid;
reg[7:0]dout;
regerr;

//Internalsignals
reg[7:0]first_byte;
reg[7:0]full_state_byte;
reg[7:0]data_parity;
reg[7:0]parity;
regcheck_error;

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//parity_donestatusregisterstorestheinformation
//thatlastparitybytehasbeendelivered
always@(posedgeclock)
begin
if(resetn==1'b0)
parity_done<=1'b0;
elseif((ld_state&&!fifo_full&&!packet_valid)||
(laf_state&&!parity_done&&low_packet_valid))
parity_done<=1'b1;
elseif(reset_int_reg)
parity_done<=1'b0;
end

//low_packet_validstatusregisterstorestheinformationthat
//forcurrentpackettransmissionpacket_validhasbecomelow,
//toavoidanyconflictionwithhighpacket_validofnexttransmission
always@(posedgeclock)
begin
if(resetn==1'b0)
low_packet_valid<=1'b0;
elseif(ld_state==1&&packet_valid==0)
low_packet_valid<=1'b1;
elseif(reset_int_reg==1)
low_packet_valid<=1'b0;
end

//Dataislatchedfrominputanddata
//issenttofifothroughfsm_dout
always@(posedgeclock)
begin
if(resetn==1'b0)
begin
dout<=8'h00;
first_byte<=8'h00;
full_state_byte<=8'h00;
end
else
begin
if(detect_add&&packet_valid==1)
first_byte<=data_in;
elseif(lfd_state)
dout<=first_byte;
elseif(ld_state&&!fifo_full)
dout<=data_in;
elseif(ld_state&&fifo_full)
full_state_byte<=data_in;
elseif(laf_state)
dout<=full_state_byte;
elseif(lp_state&&!fifo_full)
dout<=data_in;
end
end

//Paritycalculationforincomingdata
always@(posedgeclock)
begin
if(resetn==1'b0)
parity<=8'h00;
else
begin
if(detect_add)
parity<=8'h00;
elseif(lfd_state)
parity<=parity^first_byte;
elseif(ld_state&&!full_state&&packet_valid)
parity<=parity^data_in;
end
end

//Parityofpacketisstoredindata_parityregister
//andcheck_errorsignalgeneration
always@(posedgeclock)
begin
if(resetn==1'b0)
begin
data_parity<=8'b0000_0000;
check_error<=1'b0;
end
elseif(detect_add)

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begin
data_parity<=8'b0000_0000;
check_error<=1'b0;
end
elseif((ld_state&&!packet_valid)||
(full_state&&!packet_valid))
begin
data_parity<=data_in;
check_error<=1'b1;
end
else
begin
data_parity<=data_parity;
check_error<=1'b0;
end
end

//Errorinparityischeckedbycomparingthecalculated
//parityanddata_paritycomingfromthepacket
always@(posedgeclock)
begin
if(!resetn)
err<=1'b0;
elseif(!check_error)
err<=1'b0;
elseif(data_parity!=parity)
err<=1'b1;
else
err<=1'b0;
end

endmodule

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2010-08-1802:58
2011-09-2623:29

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