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Home Source Code rouiter design using verilog fifo_rtl.v

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rouiter design using verilog
Descriptiondesign router using verilog.design a 1x3 router using verilog.
By udimudi 20150110

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`defineFIFO_DEPTH16
`definefifo_width8
`defineptr_size8
modulefifo_rtl(clk,
reset_n,
data_in,
wr_en,
rd_en,
empty,
full,
data_out

);

input[(`fifo_width1):0]data_in;
inputclk,
reset_n,
wr_en,
rd_en;
reg[(`ptr_size1):0]wr_ptr;
reg[(`ptr_size1):0]rd_ptr;
reg[(`ptr_size1):0]fifo_status;
outputfull,
empty;
output[`fifo_width1:0]data_out;

wirefull,
empty;
reg[`fifo_width1:0]data_out;

reg[`fifo_width1:0]mem[0:`FIFO_DEPTH1];

always@(posedgeclkornegedgereset_n)
begin
if(~reset_n)
begin
data_out<=8'b0;
//over_flow<=1'b0;
//under_flow<=1'b0;
end
else
begin
if(rd_en)
begin
if(!empty)
begin
data_out<=mem[rd_ptr];
//under_flow<=1'b0;
end
else
begin
//under_flow<=1'b1;
data_out<=8'b0;//mem[rd_ptr];

end
end
else
data_out<=8'b0;
//under_flow<=1'b0;

if(wr_en)
begin
if(!full)

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begin
mem[wr_ptr]<=data_in;
//under_flow<=1'b0;
end
else
begin
mem[wr_ptr]<=data_in;
//under_flow<=1'b1;
end
end
else
mem[wr_ptr]<=8'b0;
//under_flow<=1'b0;

end
end

always@(posedgeclkornegedgereset_n)
begin
if(~reset_n)
begin
wr_ptr<=`ptr_size'b0;
rd_ptr<=`ptr_size'b0;
end
else
begin
if(rd_en&&!empty)
begin
if(rd_ptr==`FIFO_DEPTH1)
rd_ptr<=`ptr_size'b0;
else
rd_ptr<=rd_ptr+1'b1;
end

if(wr_en&&!full)
begin
if(wr_ptr==`FIFO_DEPTH1)
wr_ptr<=`ptr_size'b0;
else
wr_ptr<=wr_ptr+1'b1;
end
end

end
//FIFOSTATUS..........................................
always@(posedgeclkornegedgereset_n)
begin
if(~reset_n)
fifo_status<=`ptr_size'b0;
elseif((fifo_status==`FIFO_DEPTH1)&&(wr_en))
fifo_status<=`FIFO_DEPTH1;
elseif((fifo_status==`ptr_size'b0)&&(rd_en))
fifo_status<=`ptr_size'b0;
elseif(rd_en==1'b1&&wr_en==1'b0&&empty==1'b0)
fifo_status<=fifo_status1'b1;
elseif(!rd_en&&wr_en&&!full)
fifo_status<=fifo_status+1'b1;
end

//FIFIFULLANDEMPTYCONDITIONS>>>>>...............

assignempty=(fifo_status==`ptr_size'b0)?1'b1:1'b0;
assignfull=(fifo_status==`FIFO_DEPTH1)?1'b1:1'b0;

/*always@(posedgeclkornegedgereset_n)
begin
if(~reset_n)
begin
empty<=1'b1;
full<=1'b0;
end
else
begin
if(fifo_status==`FIFO_DEPTH1)
full<=1'b1;
else
full<=1'b0;
if(fifo_status==`ptr_size'b0)

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empty<=1'b1;
else
empty<=1'b0;
end
*/

/*if(wr_ptr==`ptr_size'b0&&
rd_ptr==`ptr_size'b0)
//begin
empty<=1'b1;
else
begin
empty<=1'b0;
/*if(rd_en&&rd_ptr!=(`fifo_depth1))
rd_ptr<=rd_ptr+1;
else
rd_ptr<=`ptr_size'b0;

end
if(wr_ptr==(`fifo_depth1))
begin
full<=1'b1;
//wr_ptr<=`ptr_size'b0;
end
else
full<=1'b0;
//wr_ptr<=wr_ptr+1;*/

endmodule

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2010-08-1803:00

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2011-09-2623:29

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