POLITEKNIK SULTAN HAJI AHMAD SHAH KUANTAN

DEPARTMENT OF ELECTRICAL ENGINEERING

DEE6113 CMOS IC DESIGN

Practical Work 1

Introduction to Microwind 2.6a

Software
Registration
No.

No

Name

Practical
Work Report
(Cognitive)

Practical Skill
Marks
(Psychomotor)

Total
Marks

1.

/ 30

/ 70

/ 100

2.

/ 30

/ 70

/ 100

CLASS

LECTURER NAME

: PN. NOORFOZILA BINTI BAHARI

DATE SUBMITTED

(Note: Submit this page along with the practical skill rubric after each Practical Work is completed)

Practical Work Report Marks Distribution

Report format :
1.

Title and Outcomes

/4

2.

Result

/ 10

3.

Discussion

/ 12

4.

Conclusion

/4
TOTAL :

/ 30

DEE6113 CMOS IC Design

PRACTICAL WORK 1
1.1 TITLE: Introduction to Microwind 2.6a.
1.2 LEARNING OUTCOMES
At the end of this practical work session, the student should be able to:
1. understand the features of Microwind software.
2. practice drawing the layout of simple devices such as MOS transistor.
3. practice simulating the layout of simple devices such as MOS transistor.
1.3 EQUIPMENT/TOOLS
PC Set & Microwind 2.6a software.
1.4 PROCEDURE
Part 1 : Layout Steps
Open the Microwind Editor window.
Select the Foundry file from File menu. Select cmos06.rul file. Click open, as shown in
figure 1.1. (We will be using the 0.6micron transistor technology)

Figure 1.1: Foundry file selection in Microwind

Click file menu, select new and save it with name nmos.msk
You can now start drawing layout using Microwind with desired process.
The steps used to draw NMOS device are as follows:
1. Click on the show palette window. This is shown in figure 1.2.
2. From the palette window click on the polysilicon.
3. Draw a polysilicon box with width not less than 2, which is the minimum width of
the polysilicon as shown in figure 1.3.

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DEE6113 CMOS IC Design

4. Draw a N+ Diffusion as shown in figure 4. The intersection between diffusion and

polysilicon creates the channel of the nMOS device.

Figure 1.2: Palette window in Microwind Editor

Figure 1.3: Creating a polysilicon box

Figure 1.4: Creating a N+ Diffusion

Part 2 : Change the Layout Background Colour

Click file menu, select Colors.. and tick White background box.
Your layout and simulation background will turn into white colour.

Page | 2

DEE6113 CMOS IC Design

Figure 5: Changing the layout background colour.

Figure 1.5: Changing the layout background colour

Part 3 : Process Simulation

Click on this icon above to see the process section in 2D.
The cross-section is given by a click of the mouse at the first point and the release of the
mouse at the second point.
The cross-section of the n-channel MOS device is shown in figure 1.6.

Figure 1.6: The cross-section of the nMOS devices.

Part 4 : MOS Characteristics

Click on the MOS characteristics icon. The screen shown in Figure 1.7 appears. It
represents the Id - Vd simulation of the nMOS device.

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DEE6113 CMOS IC Design

Figure 1.7: N-Channel MOS characteristic curves

The MOS size (width and length of the channel situated at the intersection of the
polysilicon gate and the diffusion) has a strong influence on the value of the current.
In Figure 1.7, the MOS width is 12.8m and the length is 1.2m. A high gate voltage (Vg
=5.0) corresponds to the highest Id-Vd curve. For Vg=0, no current flows. The maximum
current is obtained for Vg=5.0V, Vd=5.0V, with Vs=0.0.

1.5 RESULTS
In your report, include the results of the following:
1. NMOS transistor
a. transistor layout
b. transistor cross section
c. Id-Vd Characteristics Curve

(2 marks)
(1.5 marks)
(1.5 marks)

2. PMOS transistor
a. transistor layout
b. transistor cross section
c. Id-Vd Characteristics Curve

(2 marks)
(1.5 marks)
(1.5 marks)

1.6 DISCUSSION
1. Explain the terminology technology feature.

(4 marks)

2. Describe the difference between micron and lambda unit in layout design process.
(4 marks)
3. PMOS transistor is usually larger than NMOS transistor in layout. Give an explanation.
(4 marks)
1.7 CONCLUSION
Give TWO(2) conclusions for this practical work.

(4 marks)
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DEE6113 CMOS IC Design

PRACTICAL SKILL ASSESSMENT RUBRIC

DEE6113 CMOS IC DESIGN
PRACTICAL WORK 1
Student Name :

Class :

Student ID# :

Date :

ASPECTS

EXCELLENT
4-5

SCORE DESCRIPTION
MODERATE
2-3

SCALE

POOR
1

A.

Technology feature

Use correct technology feature for

the transistor layout.

Use incorrect technology

feature for the transistor layout.

Did not use any technology

feature.

x2

B.

Polysilicon width

Able to draw polysilicon width and

length correctly.

Able to draw polysilicon width

correctly.

Not able to draw the

polysilicon width incorrectly.

x2

C.

Draw basic MOS

transistor layout

Able to draw MOS transistor layout

correctly and precisely.

Able to draw MOS transistor

layout partly correct.

Not able to draw MOS

transistor layout correctly.

x2

D.

MOS transistor
cross-section

The MOS transistor cross-section is

correct.

The MOS transistor crosssection is incorrect.

MOS transistor cross-section

not produced at all.

x2

E.

Changing the layout

background colour

Able to change the layout

background colour correctly.

Able to change the layout

background colour with
assistance.

Not able to change the

layout background colour.

x2

F.

Layout simulation

Able to produce ALL layout

simulations correctly and precisely.

Able to produce SOME

simulations correctly.

Not able to produce any

simulation result.

x2

G.

Save file as .msk

Able to save the layout file

correctly under designated folder.

Able to save the layout file with

correct name and extension.

Did not save the layout file.

x2

TOTAL

SCORE

/ 70

...
Supervisor Name & Signature