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80196 MICROCONTROLLER

Features of 80196:
It is available with 16 and 20 MHz clock speeds
It has 488 Byte Register RAM
Its a Register-to-Register Architecture
It has 28 Interrupt Sources/16 Vectors
Peripheral Transaction Server
It can perform Multiplication (16 X 16) and Division (32/16) (Only in 20 MHz version)
It has Powerdown and Idle Modes
It has Five 8-Bit I/O Ports
It has 16-Bit Watchdog Timer
Its buswidth can be Dynamically Configurable 8-Bit or 16-Bit
It has Serial Port (Full Duplex)
It has High Speed I/O Subsystem
It has 16-Bit Up/Down Counter with Capture
It has 3 Pulse-Width-Modulated Outputs
It has Four 16-Bit Software Timers
It has 8- or 10-Bit A/D Converter with Sample/Hold
It has HOLD/HLDA Bus Protocol
Architecture:

80196 operates on 5V supply. 80196 uses 16KB internal ROM, 2000H through 5FFFH, when

EA 1 and

512-bytes internal RAM of which the first 24-bytes are SFR. It has five 8-bit ports (P0P4). Port 0 is an high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. Port 1 is 8-bit quasi-bidirectional I/O port. Port 2 is 8bit multi-functional port. Ports 3 and 4 are 8-bit bidirectional I/O ports and can be used as
Address/Data bus. It has on-chip clock generator and a watch-dog timer.

ARM (Advanced RISC Machine)

ARM is a key component in Embedded systems


ARM cores are used in mobile phones, handheld organizers, portable consumer devices
etc.,.

Naming ARM:
ARMxyzTDMIEJFS
x: series
y: MMU
z: cache
T: Thumb
D: debugger
M: Multiplier
I: EmbeddedICE (built-in debugger hardware)
E: Enhanced instruction
J: Jazelle (JVM Java Virtual Machine)
F: Floating-point
S: Synthesizible version (source code version for EDA tools)
For example: ARM7TDMI 7 series, Supports Thumb instruction set, Debugger and Multiplier
Embedded ICE present
Features:
Its a 32-bit RISC processor (simple but powerful instructions that execute within a single
cycle at high clock speed.)
Its design is based on the following major design rules
Instructions: reduced set/single cycle/fixed length
Pipeline: decode in one stage/no need for microcode
Registers: a large set of general-purpose registers
Load/store architecture: data processing instructions apply to registers only;
load/store to transfer data from memory
Low power consumption
Fixed opcode width of 32 bits to ease decoding and pipelining
Powerful indexed addressing modes
Simple, but fast, 2-priority-level interrupt subsystem with switched register banks.
Enhanced Instructions: DSP
Conditional execution: An instruction is only executed when a specific condition has been
satisfied
Ex:
CMP r0,r1
SUBGT r0, r0,r1
SUBLT r0, r1,r0

Architecture:

Load store architecture: For instance, in a load/store approach both operands for an ADD
operation must be in registers. All values for an operation need to be loaded from memory and be
present in registers. Following the operation, the result needs to be stored back to memory. This
differs from a register memory architecture in which one of the operands for the ADD operation
may be in memory, while the other is in a register.
Modes of operation:
User (unprivileged mode under which most tasks run)
FIQ (entered when a high priority (fast) interrupt is raised)
IRQ (entered when a low priority (normal) interrupt is raised)
Supervisor (entered on reset and when a Software Interrupt instruction is executed)
Abort (used to handle memory access violations)
Undef (used to handle undefined instructions)
Registers:

Only 16 registers are visible to a specific mode. A mode could access


A particular set of r0-r15
r13 (sp, stack pointer)
r14 (lr, link register)
r15 (pc, program counter)
Current program status register (cpsr)
CPSR (Current Program Status Register):

mode
bits
Thumb

overflo
w
carry/borro
w
zer
negativ
o
e

state
FIQ
disable
IRQ
disable

ARM supports two types of instruction sets namely ARM and Thumb
ARM / Thumb:
Instruction size
Core instructions
Conditional execution
Data processing instructions
Program status register
Register usage

ARM (T = 0)
32-bit
58
Most
Access to barrel shifter & ALU
Read-write in previliged mode
15 general purpose registers +
PC

Thumb (T = 1)
16-bit
30
only branch instructions
Separate barrel shifter &
ALU instructions
No direct access
8 general purpose registers +
7 high registers + PC

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