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Subject: TRONLA 2

Name: RABAYA, Janray S.

Section: ECE-3A

n: 25

Design Exercise 02
FET Biasing
Journal:
In this laboratory activity, we performed on how to construct a Self-bias configuration of Field
Effect Transistor (FET) consisting an n-channel Junction Field Effect Transistor (JFET) 2N5458. The
circuit is like an Emitter Bias but at this time the terminals are namely the gate, drain, and source. In
JFET, the controlled current passes from source to drain while the controlling voltage is applied between
the gate and source. With the reverse biased input junction, it has a very high input impedance thus
minimizes the interference with or loading of the signal source when conducting a measurement. FETs
are also commonly used for low signal amplifications for example, amplifying wireless signals.
This is a change is coming performance for me. My n is not a curse but this time, its a
comeback. I may say that this experiment is much better than the previous one because FET is not that
dependent on its transconductance or the counterpart of Beta in a BJT. Meaning, measurements were
easier to do since its not affected by temperature. Still, made a lot of trial-and-errors just to get a low
percentage error and consulted from those who got their work checked. I guess it is a matter of luck again
but I may recommend to really consult from the professor because in every values of n and JFETs
IDss, there is a corresponding conditions and set of formula. Just give a shot every trial and dont lose
patience.
In conclusion, this activity helped me to better understand the behavior of FET, and in particular
an n-channel JFET. For further experiments I recommend also to construct the different configuration, so
that we can prove all the things we have learned in our lecture and will help us to appreciate the subject
more.

Subject: TRONLA 2

Name: RABAYA, Janray S.

Section: ECE-3A

n: 25

Design Exercise 02
FET Biasing
Question and Answer:
At cutoff, the JFET channel is,
A.
B.
C.
D.

At its widest point


Completely closed by the depletion region.
Extremely narrow.
Reverse-biased.

Background:
The cutoff region of a JFET transistor is the region where the drain-source channel resistance is at
its maximum and there is no drain current, ID, flowing from the drain to the source of the FET transistor.
In this region, the transistor is off. The cutoff voltage (VGS off), to turn a transistor off, is applied to the
gate-source region of the FET transistor. It is the particular gate-source voltage where the JFET acts like
an open circuit.

Reference:
1. http://www.allaboutcircuits.com/textbook/semiconductors/chpt-5/junction-field-effect-transistorsjfet/
2. http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/fet.html
3. Electronic Devices and Circuit Theory by Robert L. Boylestad

Answer: B. Completely closed by the depletion region.