INSTITUTE OF TECHNOLOGY
(Approved by AICTE, New Delhi & Affiliated to Anna University, Chennai )
Dr.N.G.P. - Kalapatti Road, Coimbatore-641048
PART A
1. Define Hazards.
2. What is critical race and non critical race?
3. Explain state reduction procedure to generate reduced flow table from a primitive flow table.
4. Differentiate static and Dynamic Hazard.
5. Define fundamental mode operation of asynchronous sequential circuit.
6. Prove that dynamic hazard do not happen in two level AND OR circuit.
7. What are the advantages and disadvantages of are hot method assignments?
8. What are the situations the synchromesh networks unsuitable?
9. Write the types of Hazards?
10.Briefly explain about transition table in ASC?
11.Write short notes an static Hazard?
12.Write short notes an dynamic Hazard?
13.Write short notes an essential Hazard?
14.What is lock out condition? How it is avoided.
PART B
1. Explain static, dynamic and essential Hazards in digital circuit. Give Hazard free realization
for the following Boolean function
f (A, B, C, D) = m (2, 8, 5, 7, 10, 14)
2. Design an asynchronous sequential circuit with two Inputs x and y and with one output Z.
Whenever y is 1. Input x is transferred to Z. When y is 0, the output does not change for any
change in x.
3. An Asynchronous sequential circuit is described by the following excitation and output
function
Y = x1 x2 + (x1+x2) y; Z = Y
i. Draw the logic diagram of the circuit
ii. Derive the transition table and output map.
iii. Describe the behavior of the circuit
4. Explain the Design procedure using stage table reduction method.
5. Find a circuit that has no static hazard and implements the Boolean function.
F (A, B, C, D) + (0, 2, 6, 7, 8, 12)
2. What is D algorithm?
3. What are the advantages of using Boolean difference method over Path sensitization method?
4. What is the need for DFT in testing?
5. Define Reconvergent fan out?
6. Explain IDD Q test
7. Explain D calculus
8. What is s a o and s a i?
9. What is path sensitization method.
10.What is Fault table method?
PART B
1. Find a minimal complete test set for detecting all distinguishable single faults in the
irredundant circuit shown below by the fault table method.
2. Construct a complete test set of the circuit shown below by sensitizing its
3. Explain in detail about Built in self test method of testing digital circuits.
4. Discuss about the path sensitization and D algorithm for test vector
5. Determine the test vector for the logic circuit Z = (BC) 1 + B1 A which has a reconvergent fan
out problem.
6. Find the all the (Input and output) faults of the following expression using fault table F1 = ab
+ aie
7. Find a minimum set of set of test that win test all single stuck at o and stuck at fault in the
following expression.F = (abc + def + ghi)
For each test, specify which faults are tested for s - a - 0 and s - a 1
UNIT IV - SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES
PART A
1. Draw the basic ROM structure.
2. Comparison between PROM, PLA and PAL.