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LAPORAN PRAKTIKUM

TEKNIK DIGITAL
PENBUATAN JAM DIGITAL
DENGAN IC 7493

Oleh :

BUDI UTOMO ( IB/10 )

IMANDA RAHMA ARUM ( IB/15)

NURUL FURQON R ( IB/20 )

POLITEKNIK NEGERI MALANG


JURUSAN TEKNIK ELEKTRO
PROGRAM STUDI TEKNIK TELEKOMUNIKASI
A. Tujuan
1. Dapat menerapkan logika dasar dari suatu perangkat digital
2. Dapat merancang suatu system dengan menggunakan IC TTL
(Trasistor – Transistor Logika)
3. Mengetahui cara kerja IC 7493.
4. Mengetahui cara pengaplikasian IC 7493 pada pembuatan jam digital.
5. Mengetahui cara kerja IC 7447.
6. Mengetahui prinsip kerja dari seven segmen common anoda.

B. Teori Dasar
Jam elektronika digital yang terdiri dari pencacah yang merupakan komponen terpenting dari
sistem jam digital. Gambar (1) merupakan diagram blok sederhana suatu sistem jam digital.
Kebanyakan jam menggunakan daya frekuensi jala-jala 60 Hz sebagai masukannya. Frekuensi ini
dibagi menjadi detik, menit dan jam oleh bagian pembagi frekuensi dari jam tersebut. Kemudian
pulsa satu-per-detik, satu-per-menit, dan satu-per-jam dihitung dan disimpan dalam akumulator
pencacah jam tersebut. Selanjutnya isi akumulator pencacah (detik, menit, jam) yang tersimpan
didekode, dan waktu yang tepat ditayangkan pada tayangan waktu keluaran. Jam digital
mempunyai elemen sistem khusus. Masukannya berupa arus bolak-balik 60 Hz. Pengolahan
terjadi pada pembagi frekuensi, akumulator pencacah, dan bagian pendekode.

MASUKAN KELUARAN
   
Pembagi Counter Dekoder  7-Segmen
60Hz frekuensi display
 
 
Set waktu                    Gambar (1) 

        

     
    Jam      menit          detik 

          KELUARAN 

 
Dekoder Dekoder Dekoder 
       

 
Counter Counter Counter
  hit. 0-23 Hit. 0-59 hit. 0-59

 1 pulsa/jam              1 pulsa/menit              1 pulsa/detik 

MASUKAN
60 Hz    Dibagi    detik     Dibagi 
        menit    Dibagi 
  jam 
dengan  dengan  dengan 
60  60  60 
         

 
Gambar (2) 
 
 
 Penyimpanan terjadi pada akumulator. Bagian kendali barupa kendali set-waktu seperti pada
gambar (2). Telah disebutkan bahwa semua sistem terdiri atas gerbang logika, flip-flop, dan
subsistem. Diagram pada gambar (2) memperlihatkan bagaiman subsistem diorganisasikan
sampai menampilkan waktu dalam jam, menit, detik. Ini merupakan diagram jam digital yang
lebih terinci. Masukan berupa sinyal 60 Hz. 60 Hz dibagi 60 oleh pembagi frekuensi pertama.
Keluaran rangkaian pembagi ini berupa pulsa 1 per detik. Pulsa 1 per detik dimasukkan ke
pencacah naik yang mencacah naik dari 00 sampai 59 dan reset 00. Kemudian pencacah detik
didekode dan ditayangkan pada 7segmen.
Perhatikan rangkaian pembagi frekuensi tengah pada gambar (2). Masukan pada rangkaian ini
berupa pulsa1 per detik. Keluarannya berupa pulsa 1 per menit. Keluaran pulsa 1 per menit
dipindah ke pencacah menit 0 - 59. Pencacah naik ini mengawasi jumlah menit dari 00 sampai 59
dan reset menjadi 00. Keluaran akumulator pencacah menit didekode dan ditayangkan pada dua
7-segmen di sebelah atas tengah gambar (2).
Memperhatikan rangkaian pembagi 60 di sebelah kanak gambar (2). Masukan pada pembagi
frekuensi ini adalah pulsa 1 per menit. Keluaran rangkaian ii adalah pulsa 1 per jam. Keluaran pulsa 1
per jam dipindah ke pencacah jam di sebelah kiri. Akumulator pencacah jam ini mengawasi jumlah
jam dari 0 sampai 23. keluaran akumulator jam didekode dan dipindahkan kedua penayang 7-segmen
pada kiri atas gambar (2). Kita telah perhatikan bahwa rangkaian tersebut sudah berupa suatu jam
digital 24-jam. Rangkaian tersebut dapat diubah dengn mudah menjadi jam 12-jam dengan menukar
akumulator pencacah 0 sampai 23 menjadi pencacah 0 sampai 11.

C. Alat dan Bahan


1. Protoboard 3x
2. IC 7493 (4 binary counter) 6x
3. IC 7447 (BCD to 7-Segment Decoder/Driver) 6x
4. IC 7408 (Quard 2-input AND Gate) 1x
5. IC 7432 (Quard 2-input OR Gate) 1x
6. 7-Segment Display Common Anoda 6x
7. Resistor 300Ω 6x
8. Power Supply
9. Clock Generator
10. Kabel Penghubung
D. Rangkaian Logika

Decoder Driver Decoder Driver

SET SET SET SET SET SET SET SET


J Q J Q J Q J Q J Q J Q J Q J Q
Jam
K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q

Decoder Driver Decoder Driver Decoder Driver Decoder Driver

1 Hz J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q J
SET
Q

K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q K CLR Q

Detik Menit
E. Hubungan IC
F. Kesimpulan
 
o IC 74 LS 93 merupakan IC 4 bit counter yang dapat digunakan dalam rancangan
pembuatan jam digital.
o Tampilan jam harus direset dua kali dengan gerbang AND & OR agar 7-segment tidak
menampilkan nilai lebih dari 24.

o Rangkaian detik pada jam digital merupakan rangkaian pembagi 60.


o Rangkaian menit pada jam digital merupakan rangkaian pembagi 3600.
o Rangkaian jam pada jam digital merupakan rangkaian pembagi 86400.
Lampiran
URUTAN KAKI 7 – SEGMEN DISPLAY

COMMON
G  F  A  B 

 


 



E  D  C  dot
COMMON
SN54/74LS90
SN54/74LS92
DECADE COUNTER; SN54/74LS93
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
DECADE COUNTER;
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
DIVIDE-BY-TWELVE COUNTER;
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or 4-BIT BINARY COUNTER
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi- LOW POWER SCHOTTKY
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
• Low Power Consumption . . . Typically 45 mW J SUFFIX
• High Count Rates . . . Typically 42 MHz CERAMIC
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, CASE 632-08
Binary 14
1
• Input Clamp Diodes Limit High Speed Termination Effects

PIN NAMES LOADING (Note a)


HIGH LOW N SUFFIX
PLASTIC
CP0 Clock (Active LOW going edge) Input to 0.5 U.L. 1.5 U.L.
CASE 646-06
÷2 Section 14
CP1 Clock (Active LOW going edge) Input to 0.5 U.L. 2.0 U.L. 1
÷5 Section (LS90), ÷6 Section (LS92)
CP1 Clock (Active LOW going edge) Input to 0.5 U.L. 1.0 U.L.
÷8 Section (LS93) D SUFFIX
MR1, MR2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L. SOIC
14
MS1, MS2 Master Set (Preset-9, LS90) Inputs 0.5 U.L. 0.25 U.L. CASE 751A-02
1
Q0 Output from ÷2 Section (Notes b & c) 10 U.L. 5 (2.5) U.L.
Q1, Q2, Q3 Outputs from ÷5 (LS90), ÷6 (LS92), 10 U.L. 5 (2.5) U.L.
÷8 (LS93) Sections (Note b)
ORDERING INFORMATION
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. SN54LSXXJ Ceramic
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74) SN74LSXXN Plastic
b. Temperature Ranges. SN74LSXXD SOIC
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.

LOGIC SYMBOL

LS90 LS92 LS93


6 7

1 2

MS
14 CP0 14 CP0 14 CP0
1 CP1 1 CP1 1 CP1
MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3

1 2 1 2 1 2

2 3 12 9 8 11 6 7 12 11 9 8 2 3 12 9 8 11
VCC = PIN 5 VCC = PIN 5 VCC = PIN 5
GND = PIN 10 GND = PIN 10 GND = PIN 10
NC = PINS 4, 13 NC = PINS 2, 3, 4, 13 NC = PIN 4, 6, 7, 13

FAST AND LS TTL DATA


5-1
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

LOGIC DIAGRAM CONNECTION DIAGRAM


DIP (TOP VIEW)
LS90
6
MS1 CP1 1 14 CP0
MS2
7
MR1 2 13 NC
S S S S
J DQ J DQ J DQ R DQ
14 MR2 3 12 Q0
CP0 CP CP CP CP
NC 4 11 Q3
KC Q KC Q KC Q SC Q
D D D D
VCC 5 10 GND
1
CP1 MS1 6 9 Q1
2
MR1 MS2 7 8 Q2
12 9 8 11
MR2
3 Q0 Q1 Q2 Q3
NC = NO INTERNAL CONNECTION
= PIN NUMBERS NOTE:
VCC = PIN 5 The Flatpak version has the same
GND = PIN 10 pinouts (Connection Diagram) as
the Dual In-Line Package.

LOGIC DIAGRAM CONNECTION DIAGRAM


DIP (TOP VIEW)
LS92
CP1 1 14 CP0

NC 2 13 NC
J Q J Q J Q J Q
14
CP0 NC 3 12 Q0
CP CP CP CP
KC Q KC Q KC Q KC Q NC 4 11 Q1
D D D D
VCC 5 10 GND
1
CP1 MR1 6 9 Q2
6
MR1 12 11 9 8 MR2 7 8 Q3
MR2
7 Q0 Q1 Q2 Q3
NC = NO INTERNAL CONNECTION
= PIN NUMBERS NOTE:
VCC = PIN 5 The Flatpak version has the same
GND = PIN 10 pinouts (Connection Diagram) as
the Dual In-Line Package.

LOGIC DIAGRAM CONNECTION DIAGRAM


DIP (TOP VIEW)
LS93
CP1 1 14 CP0
J Q J Q J Q J Q MR1 2 13 NC
14
CP0 CP CP CP CP
MR2 3 12 Q0
KC Q KC Q KC Q KC Q
D D D D
NC 4 11 Q3
1
CP1 VCC 5 10 GND
2
MR1 NC 6 9 Q1
12 9 8 11
MR2
3 Q0 Q1 Q2 Q3 NC 7 8 Q2

= PIN NUMBERS NC = NO INTERNAL CONNECTION


VCC = PIN 5 NOTE:
GND = PIN 10 The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.

FAST AND LS TTL DATA


5-2
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade, C. Divide-By-Two and Divide-By-Five Counter — No external
Divide-By-Twelve, and Binary Counters respectively. Each interconnections are required. The first flip-flop is used as a
device consists of four master/slave flip-flops which are binary element for the divide-by-two function (CP0 as the
internally connected to provide a divide-by-two section and a input and Q0 as the output). The CP1 input is used to obtain
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight binary divide-by-five operation at the Q3 output.
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
LS92
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore, A. Modulo 12, Divide-By-Twelve Counter — The CP1 input
decoded output signals are subject to decoding spikes and must be externally connected to the Q0 output. The CP0 in-
should not be used for clocks or strobes. The Q0 output of put receives the incoming count and Q3 produces a sym-
each device is designed and specified to drive the rated metrical divide-by-twelve square wave output.
fan-out plus the CP1 input of the device. B. Divide-By-Two and Divide-By-Six Counter —No external
A gated AND asynchronous Master Reset (MR1 • MR2) is interconnections are required. The first flip-flop is used as a
provided on all counters which overrides and clocks and binary element for the divide-by-two function. The CP1 in-
resets (clears) all the flip-flops. A gated AND asynchronous put is used to obtain divide-by-three operation at the Q1
Master Set (MS1 • MS2) is provided on the LS90 which and Q2 outputs and divide-by-six operation at the Q3 out-
overrides the clocks and the MR inputs and sets the outputs to put.
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices LS93
may be operated in various counting modes. A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
LS90 to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are
A. BCD Decade (8421) Counter — The CP1 input must be ex- performed at the Q0, Q1, Q2, and Q3 outputs as shown in
ternally connected to the Q0 output. The CP0 input receives the truth table.
the incoming count and a BCD count sequence is pro-
B. 3-Bit Ripple Counter— The input count pulses are applied
duced.
to input CP1. Simultaneous frequency divisions of 2, 4, and
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 8 are available at the Q1, Q2, and Q3 outputs. Independent
output must be externally connected to the CP0 input. The use of the first flip-flop is available if the reset function coin-
input count is then applied to the CP1 input and a divide-by- cides with reset of the 3-bit ripple-through counter.
ten square wave is obtained at output Q0.

FAST AND LS TTL DATA


5-3
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

LS90 LS92 AND LS93


MODE SELECTION MODE SELECTION
RESET / SET INPUTS OUTPUTS RESET
OUTPUTS
INPUTS
MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3
MR1 MR2 Q0 Q1 Q2 Q3
H H L X L L L L
H H X L L L L L H H L L L L
X X H H H L L H L H Count
L X L X Count H L Count
X L X L Count L L Count
L X X L Count H = HIGH Voltage Level
X L L X Count L = LOW Voltage Level
H = HIGH Voltage Level X = Don’t Care
L = LOW Voltage Level
X = Don’t Care

LS90 LS92 LS93


BCD COUNT SEQUENCE TRUTH TABLE TRUTH TABLE
OUTPUT OUTPUT OUTPUT
COUNT COUNT COUNT
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
0 L L L L 0 L L L L 0 L L L L
1 H L L L 1 H L L L 1 H L L L
2 L H L L 2 L H L L 2 L H L L
3 H H L L 3 H H L L 3 H H L L
4 L L H L 4 L L H L 4 L L H L
5 H L H L 5 H L H L 5 H L H L
6 L H H L 6 L L L H 6 L H H L
7 H H H L 7 H L L H 7 H H H L
8 L L L H 8 L H L H 8 L L L H
9 H L L H 9 H H L H 9 H L L H
NOTE: Output Q0 is connected to Input
10 L L H H 10 L H L H
CP1 for BCD count. 11 H L H H 11 H H L H
NOTE: Output Q0 is connected to Input 12 L L H H
CP1. 13 H L H H
14 L H H H
15 H H H H
NOTE: Output Q0 is connected to Input
CP1.

FAST AND LS TTL DATA


5-4
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

GUARANTEED OPERATING RANGES


Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)


Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,


VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

20 µA VCC = MAX, VIN = 2.7 V


IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
Input LOW Current
MS, MR – 0.4
IIL CP0 – 2.4 mA VCC = MAX, VIN = 0.4 V
CP1 (LS90, LS92) – 3.2
CP1 (LS93) – 1.6
IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX
ICC Power Supply Current 15 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA


5-5
SN54/74LS90 • SN54/74LS92 • SN54/74LS93

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)


Limits
LS90 LS92 LS93
S b l
Symbol P
Parameter Min Typ Max Min Typ Max Min Typ Max U i
Unit
fMAX CP0 Input Clock Frequency 32 32 32 MHz
fMAX CP1 Input Clock Frequency 16 16 16 MHz
tPLH Propagation Delay, 10 16 10 16 10 16
ns
tPHL CP0 Input to Q0 Output 12 18 12 18 12 18
tPLH 32 48 32 48 46 70
CP0 Input to Q3 Output ns
tPHL 34 50 34 50 46 70
tPLH 10 16 10 16 10 16
CP1 Input to Q1 Output ns
tPHL 14 21 14 21 14 21
tPLH 21 32 10 16 21 32
CP1 Input to Q2 Output ns
tPHL 23 35 14 21 23 35
tPLH 21 32 21 32 34 51
CP1 Input to Q3 Output ns
tPHL 23 35 23 35 34 51
tPLH MS Input to Q0 and Q3 Outputs 20 30 ns
tPHL MS Input to Q1 and Q2 Outputs 26 40 ns
tPHL MR Input to Any Output 26 40 26 40 26 40 ns

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)


Limits
LS90 LS92 LS93
S b l
Symbol P
Parameter Min Max Min Max Min Max U i
Unit
tW CP0 Pulse Width 15 15 15 ns
tW CP1 Pulse Width 30 30 30 ns
tW MS Pulse Width 15 ns
tW MR Pulse Width 15 15 15 ns
trec Recovery Time MR to CP 25 25 25 ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize
and transfer HIGH data to the Q outputs
AC WAVEFORMS

*CP 1.3 V 1.3 V 1.3 V


tW
tPHL tPLH

Q 1.3 V 1.3 V

Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.

MR & MS 1.3 V 1.3 V MS 1.3 V 1.3 V


tW trec tW trec

CP 1.3 V CP 1.3 V
tPHL tPLH
Q0 • Q3
Q 1.3 V (LS90) 1.3 V

Figure 2 Figure 3

FAST AND LS TTL DATA


5-6
SN54/74LS47
BCD TO 7-SEGMENT
DECODER/DRIVER
The SN54 / 74LS47 are Low Power Schottky BCD to 7-Segment Decod-
er / Drivers consisting of NAND gates, input buffers and seven AND-OR-IN-
VERT gates. They offer active LOW, high sink current outputs for driving BCD TO 7-SEGMENT
indicators directly. Seven NAND gates and one driver are connected in pairs DECODER/ DRIVER
to make BCD data and its complement available to the seven decoding
AND-OR-INVERT gates. The remaining NAND gate and three input buffers LOW POWER SCHOTTKY
provide lamp test, blanking input / ripple-blanking output and ripple-blanking
input.
The circuits accept 4-bit binary-coded-decimal (BCD) and, depending on
the state of the auxiliary inputs, decodes this data to drive a 7-segment display
indicator. The relative positive-logic output levels, as well as conditions
required at the auxiliary inputs, are shown in the truth tables. Output J SUFFIX
configurations of the SN54 / 74LS47 are designed to withstand the relatively CERAMIC
high voltages required for 7-segment indicators. CASE 620-09
These outputs will withstand 15 V with a maximum reverse current of 16
1
250 µA. Indicator segments requiring up to 24 mA of current may be driven
directly from the SN74LS47 high performance output transistors. Display
patterns for BCD input counts above nine are unique symbols to authenticate
input conditions.
The SN54 / 74LS47 incorporates automatic leading and / or trailing-edge N SUFFIX
zero-blanking control (RBI and RBO). Lamp test (LT) may be performed at any PLASTIC
time which the BI / RBO node is a HIGH level. This device also contains an 16 CASE 648-08
overriding blanking input (BI) which can be used to control the lamp intensity 1
by varying the frequency and duty cycle of the BI input signal or to inhibit the
outputs.
• Lamp Intensity Modulation Capability (BI/RBO) D SUFFIX
• Open Collector Outputs
16
SOIC
• Lamp Test Provision 1 CASE 751B-03
• Leading / Trailing Zero Suppression
• Input Clamp Diodes Limit High-Speed Termination Effects
ORDERING INFORMATION
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54LSXXJ Ceramic
VCC f g a b c d e
SN74LSXXN Plastic
16 15 14 13 12 11 10 9 SN74LSXXD SOIC

LOGIC SYMBOL
7 1 2 6 3 5

1 2 3 4 5 6 7 8
A B C D LT RBI
B C LT BI / RBO RBI D A GND
PIN NAMES LOADING (Note a)
HIGH LOW BI/
a b c d e f g RBO
A, B, C, D BCD Inputs 0.5 U.L. 0.25 U.L.
RBI Ripple-Blanking Input 0.5 U.L. 0.25 U.L.
LT Lamp-Test Input 0.5 U.L. 0.25 U.L. 13 12 11 10 9 15 14 4
BI / RBO Blanking Input or 0.5 U.L. 0.75 U.L.
Ripple-Blanking Output 1.2 U.L. 2.0 U.L. VCC = PIN 16
a, to g Outputs Open-Collector 15 (7.5) U.L. GND = PIN 8
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH, 1.6 mA LOW.
b) Output current measured at VOUT = 0.5 V
The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74) Temperature Ranges.

FAST AND LS TTL DATA


5-1
SN54/74LS47

LOGIC DIAGRAM
a a

b b
B
INPUT

C c c

D
OUTPUT
d d

BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT e e

f f
LAMP-TEST
INPUT
RIPPLE-BLANKING
INPUT g g

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS

TRUTH TABLE
INPUTS OUTPUTS

DECIMAL
OR LT RBI D C B A BI/RBO a b c d e f g NOTE
FUNCTION
0 H H L L L L H L L L L L L H A
1 H X L L L H H H L L H H H H A
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L
4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H
8 H X H L L L H L L L L L L L
9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L
14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
BI X X X X X X L H H H H H H H B
RBI H L L L L L L H H H H H H H C
LT L X X X X X H L L L L L L L D
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
NOTES:
(A) BI/RBO is wire-AND logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held
at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking
of a decimal 0 is not desired. X = input may be HIGH or LOW.
(B) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state of
any other input condition.
(C) When ripple-blanking input (RBI) and inputs A, B, C, and D are at LOW level, with the lamp test input at HIGH level, all segment outputs
go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).
(D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level, and a LOW level is applied to lamp test input,
all segment outputs go to a LOW level.

FAST AND LS TTL DATA


5-2
SN54/74LS47
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High BI / RBO 54, 74 – 50 µA
IOL Output Current — Low BI / RBO 54 1.6 mA
BI / RBO 74 3.2
VO (off) Off-State Output Voltage a to g 54, 74 15 V
IO (on) On-State Output Current a to g 54 12 mA
On-State Output Current a to g 74 24

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)


Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Theshold Voltage
VIH Input HIGH Voltage 2.0 V
for All Inputs
54 0.7 Guaranteed Input
p LOW Threshold Voltage
g
VIL Input LOW Voltage V
74 0.8 for All Inputs
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
VCC = MIN,, IOH = – 50 µA,
µ ,
VOH Output HIGH Voltage,
Voltage BI / RBO 24
2.4 42
4.2 V
VIN = VIN or VIL per Truth Table
Output
p LOW Voltage
g 54, 74 0.25 0.4 V IOL = 1.6 mA VCC = MIN,, VIN = VIN or
VOL
BI / RBO 74 0.35 0.5 V IOL = 3.2 mA VIL per Truth Table
Off-State Output Current VCC = MAX, VIN = VIN or VIL per Truth
IO (off) 250 µA
a thru g Table, VO (off) = 15 V
On-State Output
p Voltage
g 54, 74 0.25 0.4 V IO (on) = 12 mA VCC = MAX, VIN = VIH
VO (on) or VIL per Truth
T th Table
T bl
a thru g 74 0.35 0.5 V IO (on) = 24 mA
20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
Input LOW Current BI / RBO – 1.2
IIL mA VCC = MAX, VIN = 0.4 V
Any Input except BI / RBO – 0.4
IOS BI / RBO Output Short Circuit Current (Note 1) – 0.3 –2.0 mA VCC = MAX, VOUT = 0 V
ICC Power Supply Current 7.0 13 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)


Limits
Symbol
S b l Parameter
P Min Typ Max Unit
U i Test
T Conditions
C di i
tPHL Propagation Delay, Address 100 ns
tPLH Input to Segment Output 100 ns VCC = 5.0 V
tPHL Propagation Delay, RBI Input 100 ns CL = 15 pF
tPLH To Segment Output 100 ns

AC WAVEFORMS

VIN 1.3 V 1.3 V VIN 1.3 V 1.3 V

tPHL tPLH tPHL tPLH

VOUT 1.3 V 1.3 V VOUT 1.3 V 1.3 V

Figure 1 Figure 2

FAST AND LS TTL DATA


5-3