0 penilaian0% menganggap dokumen ini bermanfaat (0 suara)
25 tayangan14 halaman
This document discusses asynchronous processors and their advantages over synchronous processors. It provides a brief history of asynchronous processors including early examples from the 1950s-2000s. It describes how asynchronous processors use handshaking and Muller C elements to synchronize without a central clock. Asynchronous processors provide benefits like power efficiency, reliability, and adaptability but face challenges in design and getting synchronous engineers accustomed to the approach. Present trends include using asynchronous techniques in applications like mobile devices and space where power efficiency and reliability are important.
This document discusses asynchronous processors and their advantages over synchronous processors. It provides a brief history of asynchronous processors including early examples from the 1950s-2000s. It describes how asynchronous processors use handshaking and Muller C elements to synchronize without a central clock. Asynchronous processors provide benefits like power efficiency, reliability, and adaptability but face challenges in design and getting synchronous engineers accustomed to the approach. Present trends include using asynchronous techniques in applications like mobile devices and space where power efficiency and reliability are important.
Hak Cipta:
Attribution Non-Commercial (BY-NC)
Format Tersedia
Unduh sebagai PPTX, PDF, TXT atau baca online dari Scribd
This document discusses asynchronous processors and their advantages over synchronous processors. It provides a brief history of asynchronous processors including early examples from the 1950s-2000s. It describes how asynchronous processors use handshaking and Muller C elements to synchronize without a central clock. Asynchronous processors provide benefits like power efficiency, reliability, and adaptability but face challenges in design and getting synchronous engineers accustomed to the approach. Present trends include using asynchronous techniques in applications like mobile devices and space where power efficiency and reliability are important.
Hak Cipta:
Attribution Non-Commercial (BY-NC)
Format Tersedia
Unduh sebagai PPTX, PDF, TXT atau baca online dari Scribd
Processors The clock less approach • Introduction. • Synchronous Vs Asynchronous. • History of asynchronous. • Asynchronous approach. • Muller C element. • Properties. • Challenges. • Present trends. Introduction
• One overshadowed by another's success.
• Demand for high performance, time-critical battery-powered devices. • Revisiting the clock less concept. Synchronous vs. Asynchronous • Central clock. • Power efficiency. • Electromagnetic compatibility. • Reliability and robustness. • Clock skew. • Adaptability. • Speed. Until so far • ILLIAC series (1952-62) VonNeumann • Caltech async proc(1988) world’s first. • TITAC tokyo(1998) • ARM-implementing AMULET(2000) • HT80C51 (2007) • SEA-Forth multicore. (2008). The Asynchronous approach • Methods of speeding up. • Handshaking. Enables different components of a circuit to synchronize. (no critical path required). Additional overhead and invalid signal propogation. The Asynchronous approach • Bundled-data protocols. Two phase and Four phase. referred to as micro pipelines. The Muller Pipeline • Muller-C element • While true do fundamental of Async. if x==y then • Propagates only the z=x valid data else z=z end if done The Muller Pipeline Properties • Self-timed. • Energy efficiency. • Maximum speed operation. • Electromagnetic compatibility. • Reliability and robustness against metastability. • Plug and play. Challenges • Handshaking mechanism. • Computer-aided design. • Custom chip design. • Tutoring Sync engineers Present trend • INTEL says “ …traditional synchronous design becomes increasingly inefficient. Much of total delay is dedicated to clock skew, latch delay, margin in each cycle, and non-ideal division to cycle boundaries. …Significant margins must be added to account for slow marginal cells that are statistically probable in a 24MB cache. The delivery of low clock skew over such an area is also difficult and costly. This single-ended asynchronous design eliminates the drawbacks above…”
• AsAp hybrids using GALS technology.
• Seiko Epson flexible. • Outer space applications, Wireless sensors,Mobiles. • CADRE DSP mobile app. Summing up THANK YOU.