--------------------------------------------------------------------------------

--
-- Company:
-- Engineer:
--
-- Create Date: 06:49:42 03/11/2008
-- Design Name:
-- Module Name: ques3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ques3 is
Port ( a : IN std_logic_vector (7 downto 0) ;
b : IN std_logic_vector(7 downto 0) ;
sum : OUT std_logic_vector (7 downto 0) );
end ques3;

----------file my_components.vhd-----------
----- file full_adder.vhd------
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
port (Ain IN :std_logic bit;
Bin IN :std_logic bit ;
Cin IN :std_logic bit ;
Sum OUT :std_logicm bit ;
Cout OUT:std_logic bit);
end full_adder;
architecture full_adder of full_adder is
begin
sum <= Ain xor Bin xor Cin;
Cout<= (Ain and Bin ) or (Cin and (Ain xor Bin));
end full_adder;
architecture Behavioral of ques3 is
signal width,carry :std_logic ;
--width <= "1000";
---------end full_adder-----------------
component full_adder is
port (a b c :std_logic ; sum,cout:std_logic );
end component;
begin
adder : for i in 0 to width-1 generate
ls_bit : if i = 0 generate
ls_cell : full_adder port map (a(0), b(0), '0', sum(0), cin(1));
end generate lsbit;
middle_bit : if i > 0 and i < width-1 generate
middle_cell : full_adder port map (a(i), b(i), cin(i), sum(i), cin(i+1));
end generate middle_bit;
ms_bit : if i = width-1 generate
ms_cell : full_adder port map (a(i), b(i), cin(i), sum(i), carry);
end generate ms_bit;
end generate adder;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
PACKAGE my_components is
component full_adder is
port (a b c :std_logic ; sum,cout:std_logic );
end component;
end my_components;
-------------------------------------------