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Nama : Rizgan Hafiz

NPM : 06.2008.1.04592

TUGAS ARSITEKTUR & KOMPONEN KOMPUTER

Rancanglah VHDL lode untuk rangkaian digital !

- Dekoder 3 to 8 ( output aktif “ high” )

- Dekoder 3 to 8 ( output aktif “ low” )

- Multiplexer 8 to 1

- Buatlah VHDL nya dari Tabel fungsi operasi logika berikut ini.

S1 S0 F
0 0 A AND
B
0 1 A XOR
B
1 0 A OR B
1 1 A NOR
B

Penyelesaian :

Dekoder 3 to 8 ( output aktif “ high” )


Rangkaian VHDL Dekoder 3 to 8 ( output aktif “ high” )

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder is
port( input : in std_logic_vector(2 downto 0); --3 bit input
y : out std_logic_vector(7 downto 0) -- 8 bit ouput
);
end decoder;
architecture Behavioral of decoder is

begin
y(0) <= (not input(2)) and (not input(1)) and (not input(0));
y(1) <= (not input(2)) and (not input(1)) and input(0);
y(2) <= (not input(2)) and input(1) and (not input(0));
y(3) <= (not input(2)) and input(1) and input(0);
y(4) <= input(2) and (not input(1)) and (not input(0));
y(5) <= input(2) and (not input(1)) and input(0);
y(6) <= input(2) and input(1) and (not input(0));
y(7) <= input(2) and input(1) and input(0);

end Behavioral;
setelah dilakukan pengompailan :

untuk mengetahui apakah rangkaian VHDL ini benar kita harus menginputkan
inputan sesuai dengan table. Dan ini adalah gambar setelah inputan dimasukkan :
Dekoder 3 to 8 ( output aktif “ low” )
Rangkaian VHDL :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoderlow is
port( input : in std_logic_vector(2 downto 0); --3 bit input
output : out std_logic_vector(7 downto 0) -- 8 bit ouput
);
end decoderlow;
architecture Behavioral of decoderlow is

begin
output(0) <= input(2) or input(1) or input(0);
output(1) <= input(2) or input(1) or (not input(0));
output(2) <= input(2) or (not input(1)) or input(0);
output(3) <= input(2) or (not input(1)) or (not input(0));
output(4) <= (not input(2)) or input(1) or input(0);
output(5) <= (not input(2)) or input(1) or (not input(0));
output(6) <= (not input(2)) or (not input(1)) or input(0);
output(7) <= (not input(2)) or (not input(1)) or (not input(0));

end Behavioral;

Sehtelah di lakukan melakukan pengompailan :


Setelah dimasukkan inputan, dan di kompail :

Multiplexer 8 to 1
Rangkaian VHDL :

ENTITY mux_8ch IS
PORT(
sel : IN BIT_VECTOR (2 downto 0);
d : IN BIT_VECTOR (7 downto 0);
y : OUT BIT);
END mux_8ch;
ARCHITECTURE a OF mux_8ch IS
BEGIN
-- Selected Signal Assignment
MUX8: WITH sel SELECT
y <= d(0) WHEN "000",
d(1) WHEN "001",
d(2) WHEN "010",
d(3) WHEN "011",
d(4) WHEN "100",
d(5) WHEN "101",
d(6) WHEN "110",
d(7) WHEN "111";
END a;
Setelah dikompail :

Setelah dimasukkan di dalam simulator dan di beri inputan maka hasilnya adalah :