FAST

MATH
PROCESSOR

Presented by: Anurag Sharma AND Shashwat Diesh

 Intrinsity FastMATH™
Vector and Matrix Math Processor
Optimized for real-time and adaptive signal processing needs:

Innovative architecture:  On-chip matrix coprocessor and

MIPS32™ ISA RISC core
 2 GHz SIMD 4 × 4 matrix engine with
 4 × 4 array of processors, each
multiprocessor scalability due to
high bandwidth RapidIO™ with sixteen 32-bit registers, two
interfaces 40-bit MACs
 64 GOPS (peak)
 Fixed-point math  Matrix and vector math native
instructions: 1-, 8-, 16-, 32-bit
 High-level (e.g., C) language support; convenient complex math
programmable
 Descriptor-based DMA controller
• Compiler built-in matrix intrinsics
• Vector/matrix library
 1 Mbyte on-chip cache-coherent L2
cache

Speed plus an architecture designed for parallel computations

HPEC 2002 © 2002 Intrinsity, Inc. 2

 Intrinsity FastMATH Vector and
Matrix Math Processor
2 GHz MIPS® 2 GHz
scalar engine: interconnected 4
dual issue × 4 matrix
instructions processor with
16 registers

RapidIO ports balance

I/O and processor speed

HPEC 2002 © 2002 Intrinsity, Inc. 3

 FastMATH Example:
Applications and Performance
FFTs
 OFDM
 Fast correlation/convolution
FFTs per seco nd
600,000

500,000
FastMAT H @ 2 GHz
400,000
TMS320C6416 @
300,000 600 MHz

MSC8101 @ 300
200,000 MHz

100,000 TMS320C6203 @
300 MHz
0
Smart Antenna
 Beamforming using matrix-matrix multiplication
 Parallel weight matrix calculation over 16 users
CDMA Multi-User Detection
 Jacobi iteration via matrix-matrix multiplication
 Calculation distributed over FastMATH processors via RapidIO channels

HPEC 2002 © 2002 Intrinsity, Inc. 4