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  • Arrangement and Method For Improved Downward Scaling of Higher Conductivity Metal-Based Interconnects (US Patent 6455937)

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    U.S. patent 6455937: Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects. Granted to Cunningham on 2002-09-24 (filed 1999-03-17). Currently involved in at least 1 patent litigation: Intellectual Ventures I LLC et. al. v. Hynix Semiconductor Inc. et. al. (Delaware). See http://news.priorsmart.com for more info.

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    Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects (US patent 6455937)

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    U.S. patent 6455937: Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects. Granted to Cunningham on 2002-09-24 (filed 1999-03-17). Currently involved in at least 1 patent litigation: Intellectual Ventures I LLC et. al. v. Hynix Semiconductor Inc. et. al. (Delaware). See http://news.priorsmart.com for more info.

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    345 tayangan9 halaman

    Arrangement and Method For Improved Downward Scaling of Higher Conductivity Metal-Based Interconnects (US Patent 6455937)

    Diunggah oleh

    PriorSmart
    U.S. patent 6455937: Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects. Granted to Cunningham on 2002-09-24 (filed 1999-03-17). Currently involved in at least 1 patent litigation: Intellectual Ventures I LLC et. al. v. Hynix Semiconductor Inc. et. al. (Delaware). See http://news.priorsmart.com for more info.

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    USO (64559371 «y United States Patent (0) Patent No: US 6,455,937 BL Cunningham (45) Date of Patent: Sep. 24, 2002 (58) ARRANGEMENT AND METHOD FOR 600802 A 3200 Yamagua wevsa IMPROVED DOWNWARD SCALING OF Sie A $200 Ding ta asrnst HIGHER CONDUCTIVITY METAL-BASED. Ae a . ey peer esas TENET A 12/2000 Nariman et al. 257/752, ‘oc: James A. Cunningham, fi Yet Lopate a ‘aeat (75) Yovemoe: omen A Cunningham, 1077 Sat oa Bt Lab Peet somes : 7 FOREIGN PATENT DOCUMENTS: (©) Notise: Subject any disclaimer, the term ofthis, aes a am Paton extended or adjusted under 35.22 souosss as cme Ca UL sae ® 162133050 1987 228/108 ie ios? 989 Gx si08 21) Appl. No: o97271,179 ” dnsesz 31989 xeon i mews 91900 onus (22) Filed: Man. 17, 1999 ° diss oiler OXI ” voonsio? 908 Saco Related US. Application Data * cited by examiner (63) Contimtin inp of ppiation No 09138055, (See oe MSL satan anc applcaion Primary Examiner—Phat X. Cuo NE O48 ed om Mar 20, 18 (74) Atornes, Agen, or Firm—Alleo, Dyer, Doppelt Milbrath & Gilchrist, BA. G1) Im. cl’. HOLL 23/48, HOLL 23/52; HOLL 29/40 (57) ABSTRACT (2) US. cL 287/762; 257/763 (3s) Ratlot Search rer762. 740, FOC downwarlly-saled semiconductor processing, hist- ‘conductivity meta diffusion is blocked using extremely thin 257/767, 751, 763 arsier fllms/layers. Diffusion of a highly-conductive metal sferances i mits ing 4 lees barter layer pono 6 ee distance under the high-conduetivity metal aod a distance US. PATENT DOCUMENTS tore ie ave regusalesemiconlctor devices 4283067 19RD Sena 718% iniues« highl-condueive metal ierconnet paler 4,592,891 A 6/1986 Nishikawa et al. 420/491, ighly- P AUB A 91086 Nant 201 Geer a conduclve paral dilison bari and adhesion SREGE A SARHE Aleta mons 2073 Tromelin. AL undeiing elects burt ayer Soon A ree ‘GRR Lunt fosion of the mete! ierconnect fs ermed above : eee a TAMAS the actve are fut nol diel cone withthe metal a taper imerconmect and is ted 19 black tiosion tha is nt : tina Sinctzd by te paral ahsion waver and adhesion peo- as ‘Aoyam moting film. Ina more specific embodiment, the metal a oe Jnierenanect i coated on tke upper surface and edges with * Bio a soz? ihn elecvaesl depited pal bit hn sh sx 4 Sense BOM Stl or eal 70300 A SHOE Ane aa Sore Saaraot A + Yann hae’ sa 29 Claims, 2 Drawing Sheets 0 Nw om a ) a | me: Ss U.S, Patent Sep. 24,2002 Sheet 1 of 2 US 6,455,937 B1 Ww CC" } ( _\ am iS FIG. 1A. (PRIOR ART) 120 120 \ ~~ [ 5 en \ u FIG. 1B. (PRIOR ART) 122 120 2 14 \ us FIG.1C. (PRIOR ART) U.S, Patent Sep. 24,2002 Sheet 2 of 2 US 6,455,937 B1 me cr 240 238 | } 28 200 US 6,455,937 BL 1 ARRANGEMENT AND METHOD FOR IMPROVED DOWNWARD SCALING OF HIGHER CONDUCTIVITY METAL-BASED INTERCONNECTS, RELATED PATENT DOCUMENTS This iscontinustion-in-part of US. patent application Ser. No. 09/148,096, filed on Sep. 4, 1998, which is. a ccontinuation-in-part of U.S. patent ‘application Ser. No. (091045610, filed on Mar. 20, 1998, both of these patent documents being entitled “Metallic Structure Having Elec- tromigratioa Resistance and Manufacturing Method There- for” Priority to these applications is claimed for subject ‘matter that is common, and each of these applications is incorporated herein in its entirety FIELD OF THE INVENTION ‘The present invention relates 10 the field of integrated is and integrated circuit manufacturing. More larly the present invention relates to the intereoninec= tion of clecironic eicuit structures and to blocking diffusion of high-coneluctivity structures using a thin barrier layer that is useable in downwardly scaled semiconductor siructures. BACKGROUND OF THE INVENTION ‘The electronics industry continues to rely upon advances in semiconductor technoiogy to realize higher-funetioning eviews in more compact areas, For many applications, realizing higher-functioning devices requires integrating & large number of electronic devices into a single silicon waler. As the numberof electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficul, ‘A large variety of semiconductor devices have been ‘manufactured having various applications in numerous dis- ciplines, Such silicon-based! semiconduetor devices often include metal-oxide-semiconductor (MOS) devices, such as p-channel MOS (PMOS), n-channel MOS (NMOS), com- plimentary MOS (CMOS), BICMOS devices, and bipolar transistors. Each of these semiconductor devices generally includes a semiconductor substrate on which @ number of | active devices are formed and connected to other circuitry Using metal interconnects extending from metal layers ormed above the devices. The particular structure of agiven active device can vary between device types. For example, 4 MOS ransistor generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions. Depending on the circuit design, one or more metal layers are formed above such MOS ‘transistors with lower level metal interconnects extending 10 various portions of the MOS tesnsistors, such as to the gate electrodes and the source drain regions. In the past, the motal interconnects have beea typically formed from ‘sluminum alloys. By the late 1 990, other metals, including copper, have been increasingly used and considered hecause of their improved conductivity and improved resistance to clectromigeaton, ‘One importaat step in the manufacture of such devices is the formation of baerier of isolation regions to prevent diffusion from the metal layers to the active areas of the semiconductor deviees. Diflusion occurs at elevated tem peratures where there is a concentration gradient between dopant atoms extemal to a region of the silicon wafer and dopant atoms in the silicon wafer region. Diffusion is problematic in « number of areas including, for example, in 0 6 2 coppersased interconnect systems processed using tech- nologies below about 0.25 jm and the “dusl-Damascene”™ approach, where vias and metal lines are formed simult- neously into dielectric slots. To prevent copper difusion into the active area of the device, various barrier metal or tmelal-compound lms have been used including, Tor ‘ample, Th and TAN at barrier thicknesses of about 300) A {o 500 A. Preventing diffusion of copper is important, because the presence of copper in the substrate silicon causes an increase in pa junction leakage and threshold Voltage shifls in MOS deviees. Such diffsion has also caused reduced diclectic breakdown, ‘As downward sealing of semiconductor sirutytes con- inues and processing approaches 0.06 sm (600 A) tevel, for example, conductive barrier fils having thicknesses in the range of 300-500 A will be prohibitively thick to the practical manafaciue of such semiconductor srutures. For example, a via having a width of 0.06 fm wold be filled ompletcly with a barter film coating of only 300 A in thickness. Further, because the resistivity of many barriers imatrials is quite high, a signifieant increase in sheet resis tivity CRS") for copper lines, formed by the Damescene rooess, woukl occur with eved thinner barriers. Therese vty oF TaN, For example, i about 150 times higher than the 25 resistivity of copper For such small via structures, in aition o the sidewall barter thickness being a concern, the barier material atthe base of the opening Would cause an increase ia via resis- tance. For example, the resistance across the barrie ina 0.06 um wide via using 2 300 A'TaN boxtom coating would he ‘hou 20 ohms. ‘While the above discussion evidences the need to reduce the barzer thickness for downwardly scaled semiconductor siructares, an analysiof prior at suggests thatthe thickness of certin barticr materials aginst diffsion of the highly oniluctive metals (such as copper and silver) can be redueed to thicknesses to about 100 A without adversely impacting circuit operation. A more detailed analysis of published data on bias temperate studies, om the elect of barter thickness on dieletric failure (high leakage), sug> gests that for TAN baties, a ough estimate for a minimum barsice thickness is on the order of 207A. This estimate is, based on a number of assumptions that may or may not be applicable for a given application. Among others, these assumptions include: a median time to faite ty of about 10° hours is needed at an operating Lemperatise of 150" C. (consist with a long term failire percent of OL at 10° hours and log normal sigma of 0.8), and an acceleration factor to 275° C. (estimated on the basis of the activation nergy of Cu difusion in C1), The temperate of 275° Cis, the level at which there have been relevant studies of dielectric fallure due to copper diffusion, with reported data fon the median time to fall (is) for several thickness of ‘TAN. For further information concerning such work, refer cence may be made to VMIC Conference Proceedings, June 10-12, 1997. p87. The test device employed in this work was under an electri field of 2 MViem. This data can be plowed as ty, Versus the barrier thickness “x” yielding the relationship where ke0.23 hours/A, Using the above target value of tyy and the acceleration factor, a minimum barter thickness for TaN is estimated to ‘be on the order of 20 A, ‘At the less aggressive operating temperature of 125° C., according to the present invention, an analysis based on the US 6,455,937 BL 3 above reasoning suggests that a barrier on the order of a single monolayer would suffice. Thus, the very thin barrier films suggested in connection with the present invention ‘would range from less than 60 A to a monolayer of material depending, of course, on the diffusion coefficient (D) of the barri “The above estimate is for a sullicient barrier thickness to protect the dielecirically-insulated interconnects, where lectic fields on the order af 210* Viem might be present The diffusion rate of copper is greatly accelerated by an electric field, but with a condvetive barrier in place, the amount of copper transported into a dielectric is controlled by thermal diffusion rates only. But to protect underlying active devices and pa junctions, adkltional protection is necessary, ‘One prior art approach for forming copper-based inter- connects or vias is illustrated in FIGS, LA“IC, Beginning with FIG. 1A, the approach involves a plasma etching process to open a trench 110 through a SiN layer 112 and through an uaderlying SiO, based dielectric layer 114, The plasma eiching process terminates when the trench 110 reaches a conductive contact region 116 under the SiO.- based dielectric layer 14. As shown in FIG. 1B, a barrier layer 120 of sufficient thickness to protect underlying active transistors is then formed, followed by sputter deposition or 2s clectroplating of copper 122. A ehemical-mechinical pol- ishing (CMP) process is then used to planarize the siucture down to the 1op ofthe SiN layer H12, The polished structure is shown in FIG. 1C. The SIN layer 112 acts as 2 hard polishing stop for the CMP process, and also inhibits copper diffusion into lower levels from the copper source and from any copper interconnects above the one shown in FIG. 1C, ‘One problem with this approach relates to the SiN layer 112 having a relatively high dielectric constant. The dicle- trie constant of the SiN layer I12 is about 7.5, whereas the dliclectric constant of the SiO.-based dielectric layer 114 is only about 3.9. This differential inereases the capacitive ‘coupling between interconnect levels that may be formed on the structure. This increased coupling adversely effects RC delays in the integrated circuit, Accordingly, there has been a need for semiconductor structures, and manufucturing processes therefor, that are consistent with efforts to downward scale semiconductor structures while overcoming the above-discussed disadvan= tages. SUMMARY OF THE INVENTION According to various aspects of the present invention, ‘embodiments thereof are exemplified ia the form of manu Tacturing methods and siruetures involving difusion bacrior layers (or films) fo highly-conduetive metals such as copper and silver. One example implementation is directed 10 4 process for fabricating a semiconductor device baving an active area below a frst level of metal interconnects. ‘The process involves: forming a dielectric barrier against clue Sion of a highly conductive metal, wherein the highly Conductive metal im pure form is more conductive than luosinum; forming a refractory metal connecting device or plug that penetrates the dielectric barrier and makes elec fal contact with a doped semiconductor material; forming & fiest level interconnect of the highly conductive metal, the highly conductive metal covered on the sides and o0 the bottom with a conductive barrier film that partially blocks (as compared to completely blocking) diffusion of the highly conductive metal at an operating temperature of the ser conductor device, wherein the dielectric diffusion barrier lies above the active area and lies below but oot in direct 0 6 4 contact with the first evel of metal interconnects and blocks diffusion that is not blocked by the coaduetive barter film. ‘Another example implementation of the present invention is directed to a method for fabricating 3 semiconductor device. The method includes: forming active devices on Semiconductor subsirate and a first insulating film over the active devices; forming a dielectric barrier against penetra- tion of capper over the first insulating film; forming asecond insulating film over the dieleceic barrier; Forming an open ing in the ist and second insulating films and the dielectric barrier to doped semiconductor regions; filing the opening with a refractory metal; forming a thicd insulating layer over the refractory metal and the second insulating film; forming fan opening to the refractory metal in the third insulating layer; and forming a thin barrier to copper diffusion within the opening; and filling the opening with copper, “Another example implementation of the present invention is directed to a semiconductor device involving 4 dielectric barrier for blocking diffusion of a highly conductive metal ‘The structure includes a diclectsie harrier against diffusion ‘ofa highly conductive metal. ‘The highly conductive metal in pure form is more conductive than aluminum, and the diffusion barter lies above the active agea and below but not in direct contact with the first level of metal interconnects ‘Arefractory metal connecting device penetrates the diclec- wie barcier and makes electrical contaet with a doped semi- ‘conductor material located on a side of the dielectric barcier ‘opposite the first level of metal interconnects. The highly ‘conductive metal is covered on the sides and on the bottom ‘with 4 conductive basier film, and the conductive bartier film is adapted so that it only partially blocks (as compared to completely blocking) diffusion of the highly conductive meal at an operating temperaae of the semisondcior ‘Another embodiment of the present invention is. also directed to a semiconductor doviee, but with the semicon- ‘ctor device constructed with: a dielecteic barrier layer, & thin, conductive, partial-diusion harrier and adhesion pro= moting film; and a highly-conductive-metal interconnect ppaltemed over the thin, conductive, patial-difusion barcioe ‘and adhesion promoting film. Further, a thin barrier film is teranged! to coat the metal interconnect om its upper surfice tnd edges, and the metal interconnect overlies but isnot in direct coniaet with the dielectric barrier layer. In a more Specific embodiment, the highly-conductive-metal iatercon- nect is copper or a copper alloy. “Another embodiment of the present invention is directed to & method for fabricating a semiconductor device having, active devices, This method comprises: covering a highly- ‘conductive metal-based connecting means on the edges and lower surface with a conducting barrier and adhesion improvement film, the conducting barrier and adhesion improvement film selected to partially block the high con-

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