A-59 Appendix A: Digital Logic

Example: Modulo-4 Counter

• Counter has a clock input (CLK) and a RESET input.
• Counter has two output lines, which take on values of 00, 01, 10,
and 11 on subsequent clock cycles.
Time (t) 4 3 2 1 0 4 3 2 1 0 Time (t)
00001 RESET q0 01100
3-bit q1 01010
Synchronous
s0
Counter D Q
s1 s0
D Q
Q
s1
CLK Q

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-60 Appendix A: Digital Logic

Output 00 Output 01
state state
RESET 0/01
State
1/00 A B
Transition q1 q0
1/00
Diagram for
Mod-4 1/00
0/10
Counter 0/00
1/00

C D
0/11

Output 10 Output 11
state state

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-61 Appendix A: Digital Logic

State Table for Mod-4 Counter

Input RESET
Present state 0 1
A B/01 A/00
B C/10 A/00
C D/11 A/00
D A/00 A/00

Next state Output

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-62 Appendix A: Digital Logic

State Assignment for Mod-4 Counter

Input RESET
Present
state (St) 0 1
A:00 01/01 00/00
B:01 10/10 00/00
C:10 11/11 00/00
D:11 00/00 00/00

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-63 Appendix A: Digital Logic

Truth Table for Mod-4 Counter

RESET s1 (t) s0 (t) s1 s0 (t+1) q1 q0 (t+1)

r(t)

0 0 0 01 01 s0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)

0 0 1 10 10
s1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
0 1 0 11 11
0 1 1 00 00 q0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
1 0 0 00 00
q1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
1 0 1 00 00
1 1 0 00 00
1 1 1 00 00

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-64 Appendix A: Digital Logic

Logic Design for Mod-4 Counter

RESET

DQ
s1 q1
CLK Q

DQ
s0 q0
Q

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-65 Appendix A: Digital Logic

Example: A Sequence Detector

• Example: Design a machine that outputs a 1 when exactly two of
the last three inputs are 1.
• e.g. input sequence of 011011100 produces an output sequence
of 001111010.
• Assume input is a 1-bit serial line.
• Use D flip-flops and 8-to-1 Multiplexers.
• Start by constructing a state transition diagram (next slide).

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-66 Appendix A: Digital Logic

Sequence Detector State Transition

Diagram 0/0
0/0
• Design a machine that D
outputs a 1 when ex-
actly two of the last B 1/0

three inputs are 1. 0/0 0/0

E
1/0

A 1/1 0/0

0/0
F 1/1
1/0
C 0/1

G
1/0
1/0
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-67 Appendix A: Digital Logic

Sequence Detector State Table

Input X
Present state 0 1

A B/0 C/0
B D/0 E/0
C F/0 G/0
D D/0 E/0
E F/0 G/1
F D/0 E/1
G F/1 G/0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-68 Appendix A: Digital Logic

Sequence Detector State Assignment

Input and Next state
state at and output at
time t time t+1
s 2 s1 s 0 x s2 s1 s0 z
Input X
0 0 0 0 0 0 1 0
Present state 0 1 0 0 0 1 0 1 0 0
S 2S 1S 0 S 2S 1S 0Z S 2S 1S 0Z
0 0 1 0 0 1 1 0
A: 000 001/0 010/0 0 0 1 1 1 0 0 0
B: 001 011/0 100/0 0 1 0 0 1 0 1 0
0 1 0 1 1 1 0 0
C: 010 101/0 110/0 0 1 1 0 0 1 1 0
D: 011 011/0 100/0 0 1 1 1 1 0 0 0
E: 100 101/0 110/1 1 0 0 0 1 0 1 0
F: 101 011/0 100/1 1 0 0 1 1 1 0 1
G: 110 101/1 110/0 1 0 1 0 0 1 1 0
1 0 1 1 1 0 0 1
(a) 1 1 0 0 1 0 1 1
1 1 0 1 1 1 0 0
1 1 1 0 d d d d
1 1 1 1 d d d d

(b)
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-69 Appendix A: Digital Logic

Sequence Detector Logic Diagram

0 000 x 000 x 000 0 000

x 001 x 001 x 001 0 001
1 010 x 010 x 010 0 010
x 011 x 011 x 011 0 011
D Q D Q D Q Z
1 100 S2 x 100 S1 x 100 S0 x 100
x 101 Q x 101 Q x 101 Q x 101
1 110 x 110 x 110 x 110
0 111 0 111 0 111 0 111

CLK

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-70 Appendix A: Digital Logic

Example: A Vending Machine

Controller
• Example: Design a finite state machine for a vending machine
controller that accepts nickels (5 cents each), dimes (10 cents
each), and quarters (25 cents each). When the value of the money
inserted equals or exceeds twenty cents, the machine vends the
item and returns change if any, and waits for next transaction.
• Implement with PLA and D flip-flops.

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-71 Appendix A: Digital Logic

Vending Machine State Transition

Diagram
1/0 = Dispense/Do not
dispense merchandise
A dime is 1/0 = Return/Do not return
inserted a nickel in change
Q/110 1/0 = Return/Do not
N/100 D/110 return a dime in change
N/000
A B D/000 D
0¢ Q/101 5¢ 15 ¢
Q/111
N/000
D/000 N/000
N = Nickel
Q/111 D = Dime
D/100 Q = Quarter
C
10 ¢
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-72 Appendix A: Digital Logic

Vending Machine State Table and

State Assignment

Input N D Q Input N D Q
x1 x0 x1 x0 x1 x0
P.S. 00 01 10 P.S. 00 01 10
A B/000 C/000 A/110 s 1 s0 s 1 s0 / z 2 z 1 z 0
B C/000 D/000 A/101 A:00 01/000 10/000 00/110
C D/000 A/100 A/111 B:01 10/000 11/000 00/101
D A/100 A/110 B/111 C:10 11/000 00/100 00/111
D:11 00/100 00/110 01/111
(a)
(b)

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
 A-73 Appendix A: Digital Logic

PLA Vending Machine Controller

s1 s0 x1 x0
x1 z2
x0 5×5 z1
PLA z0

Q D
s0 0
(a) CLK
1
Q D
s1 2

P resent N ext
D ispense 5
R eturn nickel
state C oin state R eturn dim e

B ase 10
6
equivalent
s1 s0 x1 x0 s1 s 0 z 2 z 1 z 0
8
0 0 0 0 0 0 1 0 0 0
1 0 0 0 1 1 0 0 0 0
2 0 0 1 0 0 0 1 1 0 9
3 0 0 1 1 d d d d d
4 0 1 0 0 1 0 0 0 0 10
5 0 1 0 1 1 1 0 0 0
6 0 1 1 0 0 0 1 0 1 12
7 0 1 1 1 d d d d d
8 1 0 0 0 1 1 0 0 0
13
9 1 0 0 1 0 0 1 0 0
10 1 0 1 0 0 0 1 1 1
11 1 0 1 1 d d d d d 14
12 1 1 0 0 0 0 1 0 0
13 1 1 0 1 0 0 1 1 0
14 1 1 1 0 0 1 1 1 1
15 1 1 1 1 d d d d d
(b) (c)
s1 s0 z2 z1 z0

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring