Release 10.1 - Timing Analyzer K.31

Release 10.1 - Timing Analyzer K.
31
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Design file:
file: D:\a_dlx04\4d\DLX_17_1_11\sources\TOP_LEVEL.ncd
Physical constraint file:
file: D:\a_dlx04\4d\DLX_17_1_11\sources\TOP_LEVEL.pcf
Device,
Device,package,
package,speed:
speed: xc2s50,tq144,-6 (PRODUCTION 1.27 2008-01-09)
Report level:
level: verbose report
Environment Variable Effect

NONE No environment variables were set
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be
reported in the unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the
details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.
Timing constraint:
constraint: TS_
TS_clk_
clk_in = PERIOD TIMEGRP "clk_clk_in"
in" 50 MHz HIGH 50%
50%;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
Timing constraint:
constraint: TS_
TS_xIO_
xIO_LOGIC_
LOGIC_XLXI_
XLXI_2_XLXI_
XLXI_2_int_
int_clk1
clk1x = PERIOD TIMEGRP "xIO_
xIO_LOGIC_
LOGIC_XLXI_
XLXI_2_XLXI_
XLXI_2_int_
int_clk1
clk1x"
TS_
TS _clk_
clk_in HIGH 50%
50%;
646129 paths analyzed, 3028 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 19.902ns.
1
Slack:
Slack:0.098ns (requirement - (data path - clock path skew + uncertainty))
uncertainty))
Source:
Source: XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd15 (FF) clk:
clk: xIO_LOGIC/XLXI_2/XLXN_17 rising at 0.000ns
Destination:
Destination: XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19 clk:
clk: xIO_LOGIC/XLXI_2/XLXN_17 rising at
(FF) 20.000ns
Requirement Data Path Delay Clock Path Skew:

Skew: Clock Uncertainty
20.000ns 19.902ns (Levels of Logic = 11) 0.000ns 0.000ns
Maximum Data Path: XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd15 to

XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19
Delay type Delay(
Delay(ns)
ns) Logical Resource
Tcko 1.085 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd15
net (fanout=9) 1.215 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd15
Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_Out221

net (fanout=5) 1.048 XLXI_54/XLXI_1/Itype
Tilo 0.549 XLXI_54/XLXI_1/XLXI_38/O<2>1

net (fanout=4) 0.759 XLXI_54/XLXI_1/Cadr<2>
Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_8/bound

net (fanout=1) 0.186 XLXI_54/XLXI_1/XLXI_3/XLXI_8/1.0
Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_9

net (fanout=56) 1.053 XLXI_54/XLXI_1/XLXI_3/GPR_WE
Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_5/O<1>1

net (fanout=64) 4.089 XLXI_54/XLXI_1/XLXI_3/AADD<1>
Tif5x 0.864 XLXI_54/XLXI_1/XLXI_3/XLXI_2/ram01/O7.G

XLXI_54/XLXI_1/XLXI_3/XLXI_2/ram01/O7.F5
net (fanout=1) 0.753 XLXI_54/XLXI_1/A<15>
Topcyf 1.250 XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_110

XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_2
net (fanout=1) 0.000 XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_129/O
Tbyp 0.081 XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_147

net (fanout=2) 1.385 XLXI_54/XLXI_1/XLXI_36/XLXN_53

net (fanout=1) 0.714 XLXI_54/XLXI_1/AEQZ
Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In164

net (fanout=2) 0.364 XLXI_54/XLXI_1/N0
Tick 1.213 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In2

Total 19.902ns (8.336ns logic, 11.566ns route)
(41.9% logic, 58.1% route)
2
Slack:
uncertainty))
Source:
Destination:
(FF) 20.000ns


Delay type Delay(
Delay(ns)










(41.6% logic, 58.4% route)
3
Slack:
uncertainty))
Source:
Destination:
(FF) 20.000ns


Delay type Delay(
Delay(ns)










(41.6% logic, 58.4% route)
Derived Constraint Report

Derived Constraints for TS_
TS_clk_
clk_in
Constraint Period Actual Period Errors Paths Analyzed
Requirement
Direct Derivative Direct Derivative Direct Derivative
TS_clk_in 20.000ns N/A 19.902ns 0 0 0 646129
TS_xIO_LOGIC_XLXI_2_XLXI_2_int_clk1x 20.000ns 19.902ns N/A 0 0 646129 0
All constraints were met.

Data Sheet report:
report: All values displayed in nanoseconds (ns)
ns)
Clock to Setup on destination clock clk_
clk_in
4
Src:
Src:Rise Src:
Src:Fall Src:
Src:Rise Src:
Src:Fall
Source Clock Dest::Rise
Dest Dest::Rise
Dest Dest::Fall
Dest Dest::Fall
Dest
clk_in 19.902
Timing summary:
summary:
Timing errors:
errors: 0 Score:
Score: 0
Constraints cover 646129 paths,
paths, 0 nets,
nets, and 5364 connections
Design statistics:
statistics:
Minimum period: 19.902ns{1}(Maximum frequency: 50.246MHz)
Footnotes
1 The minimum period statistic assumes all single cycle delays.
Analysis completed Wed Jan 19 14:27:30 2011
Timing Analyzer Settings:
Settings:
Timing Analyzer Settings OpenPCF D:
\a_dlx04\4d\DLX_17_1_11\sources\TOP_LEVEL.pcfSpeed -6IncludeNetsExcludeNetsSelectFailingTimingConstraint
FalseIncludeNoTimingConstraint FalseReport normalMaxPathsPerTimingConstraint 3ReportFastestPaths
FalseGenerateDataSheet TrueGenerateTimeGroup FalseDefineEndpoints ToAllDefineEndpoints FromAllOmitUserConstraints
FalseDropTimingConstraintSetForce OffProratingOptions Peak Memory Usage: 342 MB

Release 10.1 - Timing Analyzer K.31

Diunggah oleh

Informasi Dokumen

Deskripsi Asli:

Judul Asli

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

Release 10.1 - Timing Analyzer K.31

Diunggah oleh

Hak Cipta:

Format Tersedia

Release 10.1 - Timing Analyzer K.

Environment Variable Effect

Requirement Data Path Delay Clock Path Skew:

Maximum Data Path: XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd15 to

Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_Out221

Tilo 0.549 XLXI_54/XLXI_1/XLXI_38/O<2>1

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_8/bound

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_9

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_5/O<1>1

Tif5x 0.864 XLXI_54/XLXI_1/XLXI_3/XLXI_2/ram01/O7.G

Topcyf 1.250 XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_110

Tbyp 0.081 XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_147

Tilo 0.549 XLXI_54/XLXI_1/XLXI_36/XLXI_5

Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In164

Tick 1.213 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In2

Requirement Data Path Delay Clock Path Skew:

Maximum Data Path: XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd15 to

Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_Out221

Tilo 0.549 XLXI_54/XLXI_1/XLXI_38/O<2>1

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_8/bound

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_9

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_5/O<3>1

Tif5x 0.864 XLXI_54/XLXI_1/XLXI_3/XLXI_2/ram00/O7.G

Topcyf 1.250 XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_151

Tilo 0.549 XLXI_54/XLXI_1/XLXI_36/XLXI_5

Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In164

Tick 1.213 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In2

Requirement Data Path Delay Clock Path Skew:

Maximum Data Path: XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd15 to

Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_Out221

Tilo 0.549 XLXI_54/XLXI_1/XLXI_38/O<2>1

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_8/bound

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_9

Tilo 0.549 XLXI_54/XLXI_1/XLXI_3/XLXI_5/O<1>1

Tif5x 0.864 XLXI_54/XLXI_1/XLXI_3/XLXI_2/ram00/O5.G

Topcyf 1.250 XLXI_54/XLXI_1/XLXI_36/XLXI_3/I_36_151

Tilo 0.549 XLXI_54/XLXI_1/XLXI_36/XLXI_5

Tilo 0.549 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In164

Tick 1.213 XLXI_54/XLXI_1/XLXI_14/machine_state_FSM_FFd19-In2

Derived Constraint Report

All constraints were met.

Anda mungkin juga menyukai