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LED LCD TV
SERVICE MANUAL
CHASSIS : LD03E

MODEL: 42LE5500/550N 42LE5500/550N-ZA


MODEL: 42LE5800/5900 42LE5800/5900-ZA
MODEL: 42LE5510/5810 42LE5510/5810-ZB
MODEL: 42LE5910 42LE5910-ZB
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

/I
P OK MENU INPUT

P/NO : MFL63263102 (1003-REV00) Printed in Korea


CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION ................................................................ 7

BLOCK DIAGRAM...................................................................................14

EXPLODED VIEW .................................................................................. 15

SVC. SHEET ...............................................................................................

Copyright © 2010 LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE


Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)


Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer, AC Volt-meter

always perform an AC leakage current check on the exposed


metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
shock. such as WATER PIPE,
To Instrument's CONDUIT etc.
0.15 uF
Leakage Current Cold Check(Antenna Cold Check) exposed
With the instrument AC plug removed from AC source, connect an METALLIC PARTS
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc. When 25A is impressed between Earth and 2nd Ground
If the exposed metallic part has a return path to the chassis, the for 1 second, Resistance must be less than 0.1 Ω
measured resistance should be between 1 MΩ and 5.2 MΩ.
*Base on Adjustment standard
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright © 2010 LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range 3. Test method


This specification is applied to the LCD TV used LD03E 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety : CE, IEC specification
2. Requirement for Test - EMC :CE, IEC
Each part is tested as below without special appointment.

1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC


2) Relative Humidity : 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~ 50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.

4. Module General Specification


No. Item Specification Remark
1 Display Screen Device 107 cm(42 inch) wide color display module
2 Aspect Ratio 16:9
3 LCD Module 107 cm(42 inch) TFT LCD FHD
4 Operating Environment Temp. : 0 deg ~ 50 deg
Humidity : 20 % ~ 90 %
5 Storage Environment Temp. : -20 deg ~ 60 deg
Humidity : 10 ~ 90 %
6 Input Voltage AC 100-240V~, 50 / 60Hz
7 Power Consumption Power on (White)
LGD Typ : 90.3 LCD (Module) + Backlight(EDGE LED)
8 Module Size 937.2(H) x 566.2(V) x 23.5 mm(D) With inverter
8 Pixel Pitch 0.4845 (H) x 0.4845 (V)
9 Back Light LED(EDGE)
10 Display Colors 1.06 B(true) colors
11 Coating 3H

Copyright © 2010 LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
5. Module optical specification
No. Item Specification Min. Typ. Max. Remark
1. Viewing Angle [CR>10] Right/Left/Up/Down 89/89/89/89 CR > 10
2. Luminance Luminance (cd/m2) 360 450
Variation 1.3 MAX /MIN
3. Contrast Ratio CR 1000 1400
4. CIE Color Coordinates White Wx 0.279
Wy 0.292
RED Xr 0.636
Yr Typ. 0.335 Typ.
Green Xg -0.03 0.291 +0.03
Yg 0.603
Blue Xb 0.146
Yb 0.061

1) Standard Test Condition(The unit has been ‘ON’)


2) Stable for approximately 60 minutes in a dark environment at 25 ºC
3) The values specified are at approximate distance 50 cm from the LCD surface.

6. Component Video Input (Y, CB/PB, CR/PR)


Specification
No. Remark
Resolution H-freq(kHz) V-freq(Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080i
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 67.5 60 HDTV 1080p

Copyright © 2010 LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
7. RGB (PC)
Specification
No. Proposed Remarks
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08 28.321 For only DOS mode
2. 640*480 31.469 59.94 25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
-> 640*480 60 Hz Display
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1280*768 47.78 59.87 79.5 WXGA
6. 1360*768 47.72 59.8 84.75 WXGA
7. 1280*1024 63.595 60.0 108.875 SXGA FHD model
8. 1920*1080 66.587 59.93 138.625 WUXGA FHD model

8. HDMI Input
(1) DTV Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469 /31.5 59.94 /60 27.00/27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96 /45 59.94 /60 74.17/74.25 HDTV 720P
5. 1920*1080 33.72 /33.75 59.94 /60 74.17/74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97 /27 23.97 /24 74.17/74.25 HDTV 1080P
8. 1920*1080 33.716 /33.75 29.976 /30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43 /67.5 59.94 /60 148.35/148.50 HDTV 1080P

(2) PC Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*400 31.468 70.08 28.321 HDCP
2. 640*480 31.469 59.94 25.17 VESA HDCP
3. 800*600 37.879 60.31 40.00 VESA HDCP
4. 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP
5. 1280*768 47.78 59.87 79.5 WXGA HDCP
6. 1360*768 47.72 59.8 84.75 WXGA HDCP
7. 1280*1024 63.595 60.0 108.875 SXGA HDCP/FHD model
8. 1920*1080 67.5 60.00 138.625 WUXGA HDCP/FHD model

Copyright © 2010 LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range (3) Adjustment
1) Adjustment method
This specification sheet is applied to all of the LCD TV with - Using RS-232, adjust items listed in 3.1 in the other
LD03E chassis. shown in “3.1.(3).3)”

2) Adj. protocol
2. Designation Protocol Command Set ACK
(1) Because this is not a hot chassis, it is not necessary to use Enter adj. mode aa 00 00 a 00 OK00x
an isolation transformer. However, the use of isolation Source change xb 00 40 b 00 OK40x (Adjust 480i, 1080p Comp1 )
transformer will help protect test instrument.
xb 00 60 b 00 OK60x (Adjust 1920*1080 RGB)
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of Begin adj. ad 00 10
25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative Return adj. result OKx (Case of Success)
humidity if there is no specific designation. NGx (Case of Fail)
(4) The input voltage of the receiver must keep AC 100-240 Read adj. data (main) (main)
V~ 50 / 60Hz.
ad 00 20 000000000000000000000000007c007b006dx
(5) The receiver must be operated for about 5 minutes prior to
(sub) (Sub)
the adjustment when module is in the circumstance of over
15. ad 00 21 000000070000000000000000007c00830077x
Confirm adj. ad 00 99 NG 03 00x (Fail)
In case of keeping module is in the circumstance of 0 °C, it NG 03 01x (Fail)
should be placed in the circumstance of above 15 °C for 2 NG 03 02x (Fail)
hours
OK 03 03x (Success)

In case of keeping module is in the circumstance of below - End adj. aa 00 90 a 00 OK90x


20 °C, it should be placed in the circumstance of above 15
°C for 3 hours. Ref.) ADC Adj. RS232C Protocol_Ver1.0

[Caution] 3) Adj. order


When still image is displayed for a period of 20 minutes or - aa 00 00 [Enter ADC adj. mode]
longer (especially where W/B scale is strong. Digital pattern - xb 00 04 [Change input source to Component1(480i&1080p)]
13ch and/or Cross hatch pattern 09ch), there can some - ad 00 10 [Adjust 480i Comp1]
afterimage in the black level area. - xb 00 06 [Change input source to RGB(1024*768)]
- ad 00 10 [Adjust 1024*768 RGB]
- ad 00 90 End adj.

3. Automatic Adjustment 3.2. MAC Address


3.1. ADC Adjustment (1) Equipment & Condition
(1) Overview - Play file: Serial.exe
ADC adjustment is needed to find the optimum black level - MAC Address edit
and gain in Analog-to-Digital device and to compensate - Input Start / End MAC address
RGB deviation.
(2) Download method
(2) Equipment & Condition 1) Communication Prot connection
1) Jig (RS-232C protocol)
2) MSPG-925 Series Pattern Generator(MSPG-925FA, PCBA PC(RS-232C)
pattern - 65)
- Resolution : 480i Comp1
1080P Comp1
1920*1080 RGB RS-232C Po rt
- Pattern : Horizontal 100% Color Bar Pattern
- Pattern level : 0.7±0.1 Vp-p
- Image Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port

Copyright © 2010 LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
2) MAC Address Download 3.4. LAN PORT INSPECTION(PING TEST)
- Com 1,2,3,4 and 115200(Baud rate) Connect SET -> LAN port == PC -> LAN Port
- Port connection button click(1)
SET PC
(1) Equipment setting
1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test
Program.
*IP Number : 12.12.2.2
(2) LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN CABLE

- Load button click(2) for MAC Address write.


- Start MAC Address write button(3)
- Check the OK Or NG

3.3. LAN
(1) Equipment & Condition
A Each other connection to LAN Port of IP Hub and Jig

3.5. V-COM Adjust(Only LGD(M+S) Module)


(2) LAN inspection solution - Why need Vcom adjustment?
A LAN Port connection with PCB
A The Vcom (Common Voltage) is a Reference Voltage of
A Network setting at MENU Mode of TV
Liquid Crystal Driving.
A setting automatic IP
-> Liquid Crystal need for Polarity Change with every frame.
A Setting state confirmation
Circuit Block
-> If automatic setting is finished, you confirm IP and
Data (R ,G,B ) & Ga mma
MAC Address. Con t rol si gnal Re f e r e nce V o ltage
Data (R ,G,B ) & C ont ro l s ignal
Ti m i n g
S Co nt r o ll e r
Gamm a Reference
In t e r f a ce

Con t rol si gnal Volta ge


Y Da t a I n p u t
So urce D r i v e I C
S
T Column Line
Pane l
Gat e Driv e IC

E Power
Po w e rInput
I nput Po w e r V COM
Blo ck
M CLC CST
Liquid
Crys tal
V COM Row Li ne TFT

V COM

Copyright © 2010 LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
- Adjust sequence 3.7. CI+ Key Download method
A Press the PIP key of the ADJ remote control. (This PIP
(1) Download Procedure
key is hot key to enter the VCOM adjusting mode) 1) Press "Power on" button of a service R/C.(Baud rate :
(Or After enter Service Mode by pushing “ADJ” key, then 115200 bps)
Enter V-Com Adjust mode by pushing “G” key at “10. V- 2) Connect RS232-C Signal Cable.
Com”) 3) Write CI+ Key through RS-232-C.
A As pushing the right or the left button on the remote
4) Check whether the key was downloaded or not at ‘In
control, And find the V-COM value Which is no or Start’ menu. (Refer to below).
minimized the Flicker.
(If there is no flicker at default value, Press the exit key
and finish the VCOM adjustment.)
A Push the OK key to store value. Then the message
“Saving OK” is pop.
A Press the exit key to finish VCOM adjustment.

[Visual Adjust and control the Voltage level]

3.6. Model name & serial number download


(1) Model name & Serial number D/L
A Press “Power on” key of service remote control.(Baud => Check the Download to CI+ Key value in LGset.
rate : 115200 bps) 1. check the method of CI+ Key value
A Connect RS232 Signal Cable to RS-232 Jack. a. check the method on Instart menu
A Write Serial number by use RS-232. b. check the method of RS232C Command
A Must check the serial number at Instart menu. 1) into the main ass’y mode (RS232 : aa 00 00)
CMD 1 CMD 2 Data 0
(2) Method & notice
A. Serial number D/L is using of scan equipment. A A 0 0
B. Setting of scan equipment operated by Manufacturing
Technology Group. 2) check the key download for transmitted command
C.Serial number D/L must be conformed when it is (RS232 : ci 00 10)
produced in production line, because serial number D/L
CMD 1 CMD 2 Data 0
is mandatory by D-book 4.0
* Manual Download (Model Name and Serial Number) C I 1 0
If the TV set is downloaded by OTA or service man,
sometimes model name or serial number is initialized.(Not 3) result value
always) - normally status for download : OKx
There is impossible to download by bar code scan, so It - abnormally status for download : NGx
need Manual download.
a. Press the ‘instart’ key of ADJ remote control. 2. Check the method of CI+ Key value (RS232)
b. Go to the menu ‘5.Model Number D/L’ like below photo. 1) into the main ass’y mode (RS232 : aa 00 00)
c. Input the Factory model name(ex 42LD450-ZA) or Serial
CMD 1 CMD 2 Data 0
number like photo.
A A 0 0

2) Check the method of CI+ key by command (RS232 :


ci 00 20)
CMD 1 CMD 2 Data 0
C I 2 0

3) Result value
i 01 OK 1d1852d21c1ed5dcx
CI+ key Value
d. Check the model name Instart menu -> Factory name
displayed (ex 42LE7500-ZA)
e. Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LE7500-ZA)

Copyright © 2010 LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
4. Manual Adjustment 4.2. EDID(The Extended Display Identification
4.1. ADC(GP2) Adjustment Data)/DDC(Display Data Channel) download
4.1.1. Overview (1) Overview
ADC adjustment is needed to find the optimum black level and It is a VESA regulation. A PC or a MNT will display an
gain in Analog-to-Digital device and to compensate RGB optimal resolution through information sharing without any
deviation. necessity of user input. It is a realization of “Plug and Play”.

(2) Equipment
4.1.2. Equipment & Condition - Adjust remote control
(1) Adjust Remocon - Since embedded EDID data is used, EDID download JIG,
(2) 801GF(802B, 802F, 802R) or MSPG925FA Pattern HDMI cable and D-sub cable are not need.
Generator
- Resolution : (3)Download method
480i, 720*480 (MSPG-925FA -> Model: 209, Pattern: 65) 1) Press Adj. key on the Adj. R/C, then select “10.EDID
- 480i D/L”, By pressing Enter key, enter EDID D/L menu.
1080p, 1920*1080 (MSPG-925FA -> Model: 225, Pattern: 2) Select [Start] button by pressing Enter key, HDMI1 /
65) - 1080p HDMI2 / HDMI3 / HDMI4 / RGB are Writing and display
- Pattern : Horizontal 100% Color Bar Pattern OK or NG.
- Pattern level: 0.7 ± 0.1 Vp-p
- Image For Analog EDID For HDMI EDID
D-sub to D-sub DVI-D to HDMI or HDMI to HDMI

(3) Must use standard cable (4) EDID DATA


A HDMI
4.1.3. Adjust method
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
(1) ADC 480i, 1080p Comp1
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ
1) Check connected condition of Comp1 cable to the equipment
0x01 ⓒ 01 03 80 10 09 78 0A EE 91 A3 54 4C 99 26
2) Give a 480i, 1080p Mode, Horizontal 100% Color Bar
0x02 0F 50 54 A1 08 00 71 4F 81 80 01 01 01 01 01 01
Pattern to Comp1.
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
(MSPG-925FA -> Model: 209, Pattern: 65) - 480i 0x04 45 00 A0 5A 00 00 00 1E 01 1D 00 72 51 D0 1E 20
(MSPG-925FA -> Model: 225, Pattern: 65) - 1080p 0x05 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
3) Change input mode as Component1 and picture mode 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ
as “Standard” 0x07 ⓓ 01 ⓔ
4) Press the In-start Key on the ADJ remote after at least 1 0x00 02 03 26 F1 4E 10 1F 84 13 05 14 03 02 12 20 21
min of signal reception. Then, select 7. External ADC -> 0x01 22 15 01 26 15 07 50 09 57 07 67 ⓕ
1. COMP 1080p on the menu. Press enter key. The 0x02 ⓕ E3 05 03 01 01 1D 80 18 71 1C 16 20 58 2C
adjustment will start automatically. 0x03 25 00 A0 5A 00 00 00 9E 01 1D 00 80 51 D0 0C 20
5) If ADC calibration is successful, “ADC RGB Success” is 0x04 40 80 35 00 A0 5A 00 00 00 1E 02 3A 80 18 71 38
displayed. 0x05 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 66 21 50 B0
If ADC calibration is failure, “ADC RGB Fail” is displayed. 0x06 51 00 1B 30 40 70 36 00 A0 5A 00 00 00 1E 00 00
6) If ADC calibration is failure, after recheck ADC pattern or 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 ⓔ
condition retry calibration Error message refer to 5).
A RGB
(2) ADC 1920*1080 RGB
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
1) Check connected condition of Component & RGB cable
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ
to the equipment
0x01 ⓒ 01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26
2) Give a 1920*1080 Mode, 100 % Horizontal Color Bar
0x02 0F 50 54 A1 08 00 81 80 61 40 45 40 31 40 01 01
Pattern to RGB port.
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
(MSPG-925 Series -> model:126 , pattern:65 )
0x04 45 00 A0 5A 00 00 00 1E 01 1D 00 72 51 D0 1E 20
3) Change input mode as RGB and picture mode as “Standard”. 0x05 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
4) Press the In-start Key on the ADJ remote after at least 1 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ
min of signal reception. Then, select 7. External ADC -> 0x07 ⓓ 00 ⓔ
1. COMP 1080p on the menu. Press enter key. The
adjustment will start automatically. A Reference
5) If ADC calibration is successful, “ADC RGB Success” is - HDMI1 ~ HDMI4 / RGB
displayed. - In the data of EDID, bellows may be different by S/W or
If ADC calibration is failure, “ADC RGB Fail” is displayed. Input mode.
6) If ADC calibration is failure, after recheck ADC pattern or
condition retry calibration Error message refer to 5).

Copyright © 2010 LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
ⓐ Product ID 4.3.4. Adj. Command (Protocol)
Model Name HEX EDID Table DDC Function <Command Format>
LEN CMD VAL CS
All Model 0001 01 00 Analog
0001 01 00 Digital - LEN: Number of Data Byte to be sent
- CMD: Command
ⓑ Serial No. : Controlled on product line - VAL: FOS Data value
ⓒ Month, Year: Controlled on production line: - CS: Checksum of sent data
ex) Monthly : ‘01’ -> ‘01’ - A: Acknowledge
Year : ‘2010’ -> ‘14’ Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
ⓓ Model Name(Hex):
A RS-232C Command used during auto-adj.
MODEL MODEL NAME(HEX)
RS-232C COMMAND Explanation
all 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20
[CMD ID DATA]
ⓔ Checksum: Changeable by total EDID data.
wb 00 00 Begin White Balance adj.
ⓕ Vendor Specific(HDMI)
wb 00 10 Gain adj.(internal white pattern)
INPUT MODEL NAME(HEX)
wb 00 1f Gain adj. completed
HDMI1 67 03 0C 00 10 00 B8 2D
wb 00 20 Offset adj.(internal white pattern)
HDMI2 67 03 0C 00 20 00 B8 2D
wb 00 2f Offset adj. completed
HDMI3 67 03 0C 00 30 00 B8 2D
wb 00 ff End White Balance adj.(Internal pattern disappears)
HDMI4 67 03 0C 00 40 00 B8 2D
HDMI5 67 03 0C 00 50 00 B8 2D Ex) wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
4.3. White Balance Adjustment jb 00 c0
...
4.3.1 Overview ...
(1) W/B adj. Objective & How-it-works wb 00 1f -> Gain adj. completed
(2) Objective: To reduce each Panel’s W/B deviation *(wb 00 20(Start), wb 00 2f(completed)) -> Off-set adj.
(3) How-it-works : When R/G/B gain in the OSD is at 192, it wb 00 ff -> End white balance auto-adj.
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of A Adj. Map
R/G/B is fixed at 192, and the other two is lowered to find
the desired value. ITEM Command Data Range Default
(4) Adj. condition : normal temperature (Hex.) (Decimal)
1) Surrounding Temperature : 25 ºC ± 5 ºC Cmd 1 Cmd 2 Min Max
2) Warm-up time: About 5 Min Cool R-Gain j g 00 C0
3) Surrounding Humidity : 20 % ~ 80 %
G-Gain j h 00 C0
B-Gain j i 00 C0
4.3.2 Equipment
1) Color Analyzer: CA-210 (LED Module : CH 14) R-Cut
2) Adj. Computer(During auto adj., RS-232C protocol is G-Cut
needed) B-Cut
3) Adjust Remocon Medium R-Gain j a 00 C0
4) Video Signal Generator MSPG-925F 720p/216-Gray
G-Gain j b 00 C0
(Model:217, Pattern:78)
B-Gain j c 00 C0
-> Only when internal pattern is not available
R-Cut
A Color Analyzer Matrix should be calibrated using CS-1000 G-Cut
B-Cut
4.3.3. Equipment connection MAP Warm R-Gain j d 00 C0
G-Gain j e 00 C0
Co lo r Analyzer
B-Gain j f 00 C0
Probe RS -232C
R-Cut
Co m p ut er
RS -232C G-Cut
RS -232C

Pat t ern Generat o r


Signal Source

* If TV internal pattern is used, not needed

Copyright © 2010 LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
4.3.5. Adj. method A Standard color coordinate and temperature using CA-
(1) Auto adj. method 210(CH 9)
1) Set TV in adj. mode using POWER ON key. Mode Color Coordination Temp ∆UV
2) Zero calibrate probe then place it on the center of the
Display. x y
3) Connect Cable (RS-232C) COOL 0.269 ± 0.002 0.273 ± 0.002 13000K 0.0000
4) Select mode in adj. Program and begin adjustment.
MEDIUM 0.285 ± 0.002 0.293 ± 0.002 9300K 0.0000
5) When adj. is complete (OK Sing), check adj. status pre
mode. (Warm, Medium, Cool) WARM 0.313 ± 0.002 0.329 ± 0.002 6500K 0.0000
6) Remove probe and RS-232C cable to complete adj.

A W/B Adj. must begin as start command “wb 00 00” , and 4.4. EYE-Q function check
finish as end command “wb 00 ff”, and Adj. offset if need. Step 1) Turn on TV
Step 2) Press EYE key of Adj. R/C
(2) Manual adj. method Step 3) Cover the Eye Q II sensor on the front of the using
1) Set TV in Adj. mode using POWER ON your hand and wait for 6 seconds
2) Zero Calibrate the probe of Color Analyzer, then place it Step 4) Confirm that R/G/B value is lower than 10 of the “Raw
on the center of LCD module within 10cm of the surface. Data (Sensor data, Back light)”. If after 6 seconds,
3) Press ADJ key -> EZ adjust using adj. R/C -> 7. White- R/G/B value is not lower than 10, replace Eye Q II
Balance then press the cursor to the right (KEY G). sensor.
(When KEY(G) is pressed 216 Gray internal pattern will Step 5) Remove your hand from the Eye Q II sensor and wait
be displayed) for 6 seconds.
4) One of R Gain / G Gain / B Gain should be fixed at 192, Step 6) Confirm that “ok” pop up. If change is not seen,
and the rest will be lowered to meet the desired value. replace Eye Q II sensor.
5) Adj. is performed in COOL, MEDIUM, WARM 3 modes
of color temperature.

A If internal pattern is not available, use RF input. In EZ


Adj. menu 7.White Balance, you can select one of 2
Test-pattern: ON, OFF. Default is inner(ON). By
selecting OFF, you can adjust using RF signal in 216
Gray pattern.

A Adj. condition and cautionary items


1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer (CA-210) probe should be within
10cm and perpendicular of the module surface (80°~
100°)
3) Aging time
4.5. Local Dimming Function Check
- After Aging Start, Keep the Power ON status during Step 1) Turn on TV.
5 Minutes. Step 2) Press Tilt key of Adj. R/C.
- In case of LCD, Back-light on should be checked Step 3) Confirm under the screen.
using no signal or Full-white pattern.

4.3.6. Reference (White Balance Adj. coordinate


and temperature)
A Luminance : 216 Gray
A Standard color coordinate and temperature using CS-1000
(over 26 inch)
Mode Color Coordination Temp ∆UV
x y
COOL 0.269 0.273 13000 K 0.0000
MEDIUM 0.285 0.293 9300 K 0.0000
WARM 0.313 0.329 6500 K 0.0000

Copyright © 2010 LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
4.6. Option selection per country 6. Audio
(1) Overview
- Option selection is only done for models in Non-EU No. Item Min. Typ. Max. Unit
- Applied model: LD03D/03E Chassis applied EU model 1. Audio practical max 9.0 10.0 12.0 W EQ Off
Output, L/R AVL Off
(2) Method
1) Press ADJ key on the Adj. R/C, then select Country (Distortion=10% 8.5 8.9 9.8 Vrms Clear Voice Off
Group Menu max Output)
2) Depending on destination, select Country Group Code
2. Speaker (8Ω 10.0 15.0 W EQ On
04 or Country Group EU then on the lower Country
option, select US, CA, MX. Selection is done using +, - Impedance) AVL On
or GF KEY. Clear Voice On

4.7. Tool Option selection Measurement condition:


- Method : Press Adj. key on the Adj. R/C, then select Tool 1. RF input: Mono, 1KHz sine wave signal, 100% Modulation
option. 2. CVBS, Component: 1KHz sine wave signal 0.4Vrms
3. RGB PC: 1KHz sine wave signal 0.7Vrms
MODEL Tool 1 Tool 2 Tool 3 Tool 4 Tool 5
47LE5*** 33024 31795 56364 22958 2066
7. USB S/W Download (option, Service only)
1) Put the USB Stick to the USB socket
4.8. Ship-out mode check(In-stop) 2) Automatically detecting update file in USB Stick
After final inspection, press IN-STOP key of the Adj. R/C and - If your downloaded program version in USB Stick is Low,
check that the unit goes to Stand-by mode. it didn’t work. But your downloaded version is High, USB
After final inspection, Always turn on the Mechanical S/W. data is automatically detecting
3) Show the message “Copying files from memory”

5. GND and Internal Pressure check


5.1. Method
1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET.
(If loose, re-insert)
2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX) 4) Updating is starting.
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.

5.2. Checkpoint
• TEST voltage
- GND: 1.5KV/min at 100mA
- SIGNAL: 3KV/min at 100mA
• TEST time: 1 second 5) Updating Completed, The TV will restart automatically
• TEST POINT 6) If your TV is turned on, check your updated version and
- GND TEST = POWER CORD GND & SIGNAL CABLE Tool option. (explain the Tool option, next stage)
METAL GND * If downloading version is more high than your TV have,
- Internal Pressure TEST = POWER CORD GND & LIVE & TV can lost all channel data. In this case, you have to
NEUTRAL channel recover. if all channel data is cleared, you didn’t
• LEAKAGE CURRENT: At 0.5 mArms have a DTV/ATV test on production line.

* After downloading, have to adjust TOOL OPTION again.


1. Push "IN-START" key in service remote control.
2. Select "Tool Option 1" and Push “OK” button.
3. Punch in the number. (Each model has their number.)

Copyright © 2010 LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
BLOCK DIAGRAM

Copyright © 2010 LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

710

920
400
830

521

820

900
910
540

880

840
LV2

530
LV1

810
800

A10
200

A5
A21
A2
120
300

500

Copyright LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
EXT IRQ
SMD GASKET GPIO_00, GPIO_01, GPIO_02,
RESET GPIO_11, GPIO_11, GPIO_39

MDS62110206

MDS62110206

MDS62110206

MDS62110206

MDS62110206
MDS62110206

MDS62110206
MDS62110206

MDS62110206

6.5T_GAS

6.5T_GAS
6.5T_GAS
IC100 IR_INT : GPIO_23

GAS4

GAS5

GAS6

GAS8

GAS9
GAS3

GAS7
GAS1

GAS2
LGE3556C (C0 VERSION) IR1_IN : GPIO_25
CI_A[0-13] IR2_IN : GPIO_29
IR_OUT : GPIO_26
J23 N26 OPT R1047
CI_A[3] 0
EBI_ADDR3 GPIO_00 POWER_DET INTERRUPT PIN PWM0 : GPIO_24
CI_A[4] J24 L26 0 R192
EBI_ADDR4 GPIO_01 DC INTERRUPT PIN DC 17page : Motion Remocon

OPT

OPT
PWM1 : GPIO_09

OPT

OPT

OPT
+3.3V_NORMAL

OPT
CI_A[2] H25 N25 INTERRUPT PIN
EBI_ADDR2 GPIO_02 ERROR_OUT
+3.3V_NORMAL CI_A[1] H24 L25
R1027

EBI_ADDR1 GPIO_03 MODEL_OPT_4


CI_A[0] H23 K27
10K

EBI_ADDR0 GPIO_04 MODEL_OPT_5

MDS62110204

MDS62110204

MDS62110204
GAS1-*4 CI_A[5] J25 K28

5.5T_GAS
SIDE_AV_DET

5.5T_GAS
EBI_ADDR5 GPIO_05

5.5T_GAS

GAS1-*1

GAS6-*1

GAS7-*1
R1045 F26 K24
CI_A[6]
MDS62110204 4.7K EBI_ADDR6 GPIO_06 CI_5V_CTL For CI
CI_A[8] H28 K26 1K R114
R1030 0 55LD650_5.5T EBI_ADDR8 GPIO_07 HDMI_HPD_4
SOC_RESET SYS_RESETb CI_A[9] J26 K25 DEMOD_RESET 22 R113
EBI_ADDR9 GPIO_08 DEMOD_RESET 28page : ISDB Demod
EBI_CS CI_A[13] H27 AA27 DEMOD_RESET
EBI_ADDR13 GPIO_09 PWM_DIM
GAS3-*4 CI_A[12] G26 AA28 R1029 1K R1042 100
EBI_ADDR12 GPIO_10 HDMI_HPD_3
MDS62110204 CI_A[11] J27 AA26
EBI_ADDR11 GPIO_11 MODEL_OPT_1
55LD650_5.5T CI_A[10] J28 L1

MDS62110205

MDS62110205

MDS62110205
EBI_ADDR10 GPIO_12 DSUB_DET

7.5T_GAS
L3

7.5T_GAS
CI_A[7] F27

7.5T_GAS

GAS1-*2

GAS6-*2

GAS7-*2
EBI_ADDR7 GPIO_13 BT_RESET
22 R116 G24 L2
/CI_WAIT EBI_TAB GPIO_14 /RST_HUB
22 R122 H26 Y25
EBI_WE EBI_WE1B GPIO_15 BCM_RX
R117 G27 Y26
33 EBI_CLK_IN GPIO_16 BCM_TX
G28 M27
EBI_CLK_OUT GPIO_17 SC_RE1
22 R127 K23 AA25
EBI_RW EBI_RWB GPIO_18 SC_RE2
22 G25 R25 R111 22
EBI_CS EBI_CS0B GPIO_19 CI_MOD_RESET
R140 N28
GPIO_20 MODEL_OPT_0
NAND_DATA[0-7] N27 BT_MUTE
MDS61887710 GPIO_21 DD DD 17page : Motion Remocon

MDS61887710
MDS61887710

MDS61887710

MDS61887710

MDS61887710

MDS61887710

MDS61887710
+3.3V_NORMAL NAND_DATA[0] U24 AH18 R105 56
GAS2-*3

GAS9-*3
AUD_MASTER_CLK

9.5T_GAS

9.5T_GAS
NAND_DATA0 GPIO_22
GAS1-*3

GAS3-*3

GAS4-*3

GAS5-*3

GAS6-*3

GAS8-*3
9.5T_GAS

9.5T_GAS

9.5T_GAS
9.5T_GAS

9.5T_GAS

9.5T_GAS
NAND_DATA[1] T26 P23 R199 1K
NAND_DATA1 GPIO_23 HDMI_HPD_2 IR_IN
NAND_DATA[2] T27 M23
NAND_DATA2 GPIO_24 A_DIM

4.7K
4.7K
NAND_DATA[3] U26 AD19 R106 1K 12K R1041 EMI
NAND_DATA3 GPIO_25 HDMI_HPD_1 IR_IN C173
NAND_DATA[4] U27 AE19 R1048 100 C180
NAND_DATA4 GPIO_26 5V_HDMI_1 100pF 22uF
NAND_DATA[5] V26 M4 R109 100 BB Add. 16V
NAND_DATA5 GPIO_27 EPHY_ACTIVITY 50V
NAND_DATA[6] V27 M5 R110 100

R194
R193
NAND_DATA6 GPIO_28 EPHY_LINK
NAND_DATA[7] V28 L23
NAND_DATA7 GPIO_29 /CI_CD1 For CI
T24 Y28 BCM_AVC_DEBUG_TX1
NVRAM NAND_CEb
NAND_ALE
NAND_REb
R23
T23
NAND_CS0B
NAND_ALE
GPIO_30
GPIO_31
Y27
G2
BCM_AVC_DEBUG_RX1
M_REMOTE_TX
M_REMOTE_RX
M_REMOTE_TX 17page : Motion Remocon
M_REMOTE_RX 17page : Motion Remocon
NAND_REB GPIO_32 VREG_CTRL
NAND_CLE T25 G3
+3.3V_NORMAL NAND_CLE GPIO_33 TUNER_RESET
From wireless_I2C to micom I2C NAND_WEb R24 G5 R107 100
NAND_WEB GPIO_34 DTV_ATV_SELECT
+3.3V_NORMAL NAND_RBb U25 G6 R108 100
NAND_RBB GPIO_35 5V_HDMI_2 R115 1.8K
G4 For CI
+3.3V_NORMAL GPIO_36 AV_CVBS_DET
L24 0 R1044
GPIO_37 CI_OUTCLK
W24 P25 R1033 22
GPIO_38 /CI_CD2
R1025

C103 SF_MISO
4.7K

IC102 U23 L5 R1046 22


M24M01-HRMN6TP 0.1uF SF_MOSI GPIO_39 /CI_IREQ
V23 K4
SF_SCK GPIO_40 MODEL_OPT_6
R173

V24 K1
10K
OPT

NC VCC SF_CSB GPIO_41 MODEL_OPT_3


1 8 L27
GPIO_42 WIRELESS_DL_RX
R1032 M26
0 E1 WP GPIO_43 WIRELESS_DL_TX
2 7 N23 R132 22 External Demod.
GPIO_44 FE_TS_VAL_ERR
R28 R1050 100
GPIO_45 5V_HDMI_3
E2
3 A8’h 6
SCL
R1026 22
SCL3_3.3V
R27 R161 100
GPIO_46 5V_HDMI_4
R26 R133 22
VSS SDA GPIO_47 MODEL_OPT_2
4 5 R1028 22 P28
SDA3_3.3V GPIO_48 SCART1_DET
G

Q103 P27
C171 C167 FDV301N GPIO_49 SIDE_COMP_DET SIDE_COMP_DET
8pF 8pF K6 R103 0
GPIO_50 RF_SWITCH_CTL_CHB RF_SWITCH_CTL_CHB 15page : CHB_SUB_TUNER
OPT OPT WIRELESS_SDA K5 22 R129
D

SDA2_3.3V GPIO_51 RGB_DDC_SCL


P26 100 R160 R1052 +3.3V_NORMAL
G

OPT FRC_RESET 4.7K +3.3V_NORMAL


Q104 GPIO_52
M3 22 R102
FDV301N * I2C MAP GPIO_53
M2 22 R1049
RGB_DDC_SDA
WIRELESS_SCL SCL2_3.3V GPIO_54
D

M1
OPT GPIO_55 COMP2_DET
* I2C_0 :

1.2K

1.2K

1.2K

1.2K

1.2K

1.2K

1.2K

1.2K
R187

R184

R183

R180

R177

R176

R171

R170
L4 22 R1051
GPIO_56 LG5111_RESET
L6 LOCAL DIMMING
GPIO_57 HP_DET LG5111_RESET
R123 0 WIRELESS * I2C_1 : W27
SGPIO_00 SCL0_3.3V
W28
SGPIO_01 SDA0_3.3V
R124 0 WIRELESS * I2C_2 : W26
SGPIO_02 SCL1_3.3V
W25
SGPIO_03 SDA1_3.3V
* I2C_3 : J2
SGPIO_04 SCL2_3.3V
J1
SGPIO_05 SDA2_3.3V
K3
SGPIO_06 SCL3_3.3V
K2
SGPIO_07 SDA3_3.3V

Boot Strap * NAND FLASH MEMORY 4Gbit (512M for BB)


Default Res. of all NAND pin is Pull-down
+3.3V_NORMAL
+3.3V_NORMAL
NAND_DATA[0-7] R1000
2.7K
NAND_DATA[0] OPT R1008
R1036 2.7K IC101
OPT 2.7K
NAND04GW3B2DN6E
NAND_DATA[1]
R1005
R1040 2.7K
OPT 2.7K
NC_1 NC_29
NAND_DATA[2] R169 1 48
NAND FLASH
R1039 2.7K NC_2 NC_28
2.7K

2.7K

2.7K 2 47
NAND_DATA[3] OPT R1004 NC_3 NC_27
3 46
2.7K
R1037OPT NC_4 NC_26 NAND_DATA[0-7]
NAND_DATA[4]
2.7K 4 45 MODEL OPTION
R191

R1003
R134

NC_5 I/O7 NAND_DATA[7] LOW


R1002 2.7K 5 44 PIN NAME PIN NO. HIGH
OPT 2.7K
NAND_DATA[5] NC_6 I/O6 NAND_DATA[6]
R1035 6 43 MODEL_OPT_0 N28 URSA3 NON_URSA3
R1034 2.7K Open Drain RB I/O5
2.7K NAND_RBb 7 42 NAND_DATA[5] +3.3V_NORMAL
MODEL_OPT_1 AA26 MAIN_MINI_LVDS MAIN_LVDS

EXTERNEL FRC/T_CON FRC


NAND_DATA[6] R I/O4

MINI_LVDS/NO LOCAL_D
OPT R1007 NAND_DATA[4]
NAND_REb 8 41
R1006OPT 2.7K MODEL_OPT_2 R26 DDR-256M DDR-512M
2.7K E NC_25
NAND_DATA[7] NAND_CEb 9 40

1K

1K

1K

1K
1K

1K
1K

DDR_512MB
R1038 MODEL_OPT_3 K1
NC_7 NC_24
+3.3V_NORMAL FHD HD
R158 OPT 2.7K 10 39
C116

FHD

FRC
GIP
2.7K

OLED
NAND_DATA[0-7]

4700pF NC_8 NC_23

R1017

R1022

R1011

R1020
MODEL_OPT_4 NON_FRC

R1009

R1013
11 38 C136 10uF L25 FRC

R118
R156 10V
NAND_ALE 2.7K
R157 OPT VDD_1 VDD_2 MODEL_OPT_5 NON-GIP
2.7K C114 12 37 C115 K27 GIP
0.1uF VSS_1 VSS_2 0.1uF
R1001 R1012 100
NAND_CLE 13 36 IF_AGC_SEL MODEL_OPT_0 MODEL_OPT_6 K4 OLED NON_OLED
2.7K R1019 100
NC_9 NC_22 LNA2_CTL/BOSTER_CTL MODEL_OPT_1
14 35 R1024 100
RF_SWITCH_CTL MODEL_OPT_2
NAND_IO[0] : Flash Select (1) NC_10 NC_21 R181 100
0 : Boot From Serial Flash 15 34 BT_ON/OFF MODEL_OPT_3 17page:M_RFMODULE_RESET *MODEL_OPT_0 & MODEL_OPT_4
1 : Boot From NAND Flash BCM BT MODULE REFER TO THIS OPTION
CL NC_20 MODEL_OPT_4 15page:TW_9910_RESET
NAND_CLE 16 33
NAND_IO[1] : NAND Block 0 Write (DNS) AL I/O3 NAND_DATA[3] MODEL_OPT_515page:CHB_RESET MODEL_OPT_0 MODEL_OPT_4
0 : Enable Block 0 Write NAND_ALE 17 32 R130 22
NO FRC/INTERNER FRC

/CI_SEL MODEL_OPT_6 LOW LOW NO FRC


1 : Disable Block 0 Write W I/O2 NAND_DATA[2]
NAND_WEb 18 31 HIGH LOW URSA3 Internal

LVDS/LOCAL_D
1K

1K

1K

1K

1K
1K

1K

NAND_IO[3:2] : NAND ECC (1, DNS) HIGH HIGH URSA3 External


DDR_256MB
WP I/O1 NAND_DATA[1]
NON_OLED

+3.3V_NORMAL
NON_GIP

00 : No ECC 19 30

NO_FRC
LOW HIGH PWIZ Pannel T-con
01 : 1 ECC Bit
HD

NC_11 I/O0 NAND_DATA[0] with LG FRC


10 : 4 ECC Bit 20 29
R119
R136
4.7K

R1021

R1015

R1014

R1018
R1023

R1010

11 : 8 ECC Bit NC_12 NC_19


21 28
NAND_IO[4] : CPU Endian (0) NC_13 NC_18
0 : Little Endian 22 27
1 : Big Endian NC_14 NC_17
FOR ESD 12V Pattern
C 23 26
NAND_IO[6:5] : Xtal Bias Control (1, DNS) B Q101 NC_15 NC_16
00 : 1.2mA (Fundmental Recommand) FLASH_WP 24 25 +12V
KRC103S
01 : 1.8mA
10 : 2.4mA (3rd over tune Recommand) E
11 : 3.0mA

NAND_IO[7] : MIPS Frequency (DNS)


C178 C179
0 : 405MHz
0.1uF 0.1uF
1 : 378MHz
50V 50V
NAND_ALE : I2C Level (DNS)
0 : 3.3V Switching
1 : 5V Switching

NAND_CLE
0 : Enable D2CDIFF AC (DNS)
1 : Disabe D2CDIFF AC

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (EUROBBTV) 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 & NAND FLASH 1

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
When usding FUNDMENTAl then series R = 0 ohm and CL = 8 pF
IC100 54MHz X-TAL
LGE3556C (C0 VERSION) When usding Dip-type X-tal then series R = 22 ohm and CL = 12 pF

D23 B4
FE_TS_DATA_CLK C24
PKT0_CLK LVDS_TX_0_DATA0_P
A4
LVDS_TX_1_DATA4_N013:E7;035:AK20
FE_TS_SERIAL B26
PKT0_DATA LVDS_TX_0_DATA0_N
C6
LVDS_TX_1_DATA4_P013:E7;035:AK19
FE_TS_SYNC PKT0_SYNC LVDS_TX_0_DATA1_P LVDS_TX_1_DATA3_N013:E7;035:AK19 C230
A25 B6 22
RMX0_CLK LVDS_TX_0_DATA1_N LVDS_TX_1_DATA3_P013:E7;035:AK19 12pF
TP4021 B25 B3 R212
TP4022 RMX0_DATA LVDS_TX_0_DATA2_P LVDS_TX_1_DATA2_N013:E7;035:AK17
A26 A3
TP4023 RMX0_SYNC LVDS_TX_0_DATA2_N LVDS_TX_1_DATA2_P013:E7;035:AK17
A1
CI_OUTDATA[0-7],CI_OUTSTART,CI_OUTVALID

1008LS-272XJLC 33pF
LVDS_TX_0_DATA3_P LVDS_TX_1_DATA1_N013:E7;035:AK17

C257
045:V14 A2
LVDS_TX_0_DATA3_N LVDS_TX_1_DATA1_P013:E7;035:AK16
CI_A[14] G23 D5
POD2CHIP_MCLKI LVDS_TX_0_DATA4_P LVDS_TX_1_DATA0_N013:E7;035:AK16
CI_OUTDATA[0] D25 D6

2
POD2CHIP_MDI0 LVDS_TX_0_DATA4_N LVDS_TX_1_DATA0_P013:E7;035:AK16

54MHz
CI_OUTDATA[1] D24 C5

X903

3
POD2CHIP_MDI1 LVDS_TX_0_CLK_P LVDS_TX_1_CLK_N 013:E7;035:AK18

L208
CI_OUTDATA[2] C25 B5 54MHz_XTAL_N
POD2CHIP_MDI2 LVDS_TX_0_CLK_N LVDS_TX_1_CLK_P 013:E7;035:AK18
CI_OUTDATA[3] E27 B1

1
POD2CHIP_MDI3 LVDS_TX_1_DATA0_P LVDS_TX_0_DATA4_N013:F7;035:AK15 54MHz_XTAL_P
CI_OUTDATA[4] E26 B2
POD2CHIP_MDI4 LVDS_TX_1_DATA0_N LVDS_TX_0_DATA4_P013:F7;035:AK14
CI_OUTDATA[5] D28 C2

R243
POD2CHIP_MDI5 LVDS_TX_1_DATA1_P LVDS_TX_0_DATA3_N013:F7;035:AK14

604
CI_OUTDATA[6] D27 C3
POD2CHIP_MDI6 LVDS_TX_1_DATA1_N LVDS_TX_0_DATA3_P013:F7;035:AK14
CI_OUTDATA[7] D26 D1
POD2CHIP_MDI7 LVDS_TX_1_DATA2_P LVDS_TX_0_DATA2_N013:F7;035:AK12
CI_OUTSTART E23 D2
POD2CHIP_MISTRT LVDS_TX_1_DATA2_N LVDS_TX_0_DATA2_P013:F7;035:AK12
CI_OUTVALID E24 E1
POD2CHIP_MIVAL LVDS_TX_1_DATA3_P LVDS_TX_0_DATA1_N013:E7;035:AK12
F25 E2 22
CHIP2POD_MCLKO LVDS_TX_1_DATA3_N LVDS_TX_0_DATA1_P013:E7;035:AK11 R211 12pF
C27 E3
CHIP2POD_MDO0 LVDS_TX_1_DATA4_P LVDS_TX_0_DATA0_N013:E7;035:AK11 C229
C26 E4
CHIP2POD_MDO1 LVDS_TX_1_DATA4_N LVDS_TX_0_DATA0_P013:E7;035:AK11
B28 D3 A1.2V A2.5V
CHIP2POD_MDO2 LVDS_TX_1_CLK_P LVDS_TX_0_CLK_N 013:E7;035:AK13
B27 D4
CHIP2POD_MDO3 LVDS_TX_1_CLK_N LVDS_TX_0_CLK_P 013:E7;035:AK13
A27
F24
CHIP2POD_MDO4 LVDS_PLL_VREG
F5
F1
C228
10uF
OPT
VIDEO INCM
CHIP2POD_MDO5 LVDS_TX_AVDDC1P2
F23 F4
CHIP2POD_MDO6 LVDS_TX_AVDD2P5_1
A3.3V A1.2V A2.5V E25 F2
CHIP2POD_MDO7 LVDS_TX_AVDD2P5_2
C28
A28
CHIP2POD_MOSTRT LVDS_TX_AVSS_1
C1
F3
PLACE NEAR BCM CHIP
CHIP2POD_MOVAL

0.1uF

0.1uF

0.1uF
LVDS_TX_AVSS_2

4.7uF

4.7uF
C4

C2013
0

0
R236

R237

C236

C239

C242

C295
L202 LVDS_TX_AVSS_3
A5
BLM18PG121SN1D LVDS_TX_AVSS_4 C258 0.1uF
AC18 E5 Near Q1705 TU_CVBS_INCM
VDAC_AVDD2P5 LVDS_TX_AVSS_5 Run Along TUNER_CVBS_IF_P Trace
AF20 E6 003:A3
VDAC_AVDD1P2 LVDS_TX_AVSS_6
AG20 D7
VDAC_AVDD3P3_1 LVDS_TX_AVSS_7
4.7uF

AG21 E7
0.1uF

0.1uF

0.1uF
VDAC_AVDD3P3_2 LVDS_TX_AVSS_8
C214

C219

C223
C212

F7
BROAD BAND STUDIO LVDS_TX_AVSS_9
G7
C2019 0.1uF
SC1_RGB_INCM
LVDS_TX_AVSS_10 A1.2V
Near J1500 003:A4
AF19 H7 Run Along SC1_R,SC_G,SC_B Trace
VDAC_AVSS_1 LVDS_TX_AVSS_11
AD20 A2.5V
R220 : BCM recommened resistor 562 ohm VDAC_AVSS_2

0.1uF
C2012
+3.3V_NORMAL AE20
R220 560AH22 VDAC_AVSS_3
AD27

0.1uF
P200 C215 VDAC_RBIAS CLK54_AVDD1P2 C261 0.1uF

C251
AH20 AD28 REAR_AV_CVBS_INCM
TJC2508-4A 0.1uF VDAC_1 CLK54_AVDD2P5
AG19 AD26 003:A3
VDAC_2 CLK54_AVSS
C213 AC26
54MHz_XTAL_N

R244

R248

R250
0.01uF CLK54_XTAL_N 002:I1
R238
75
1%

AH21 AC27
4.7uF
C2028

R200
1.5K

34

34

34
54MHz_XTAL_P
R201
1.5K

1 VDAC_VREG CLK54_XTAL_P 002:I2


AE25
CLK54_MONITOR
DTV/MNT_V_OUT Y23
PM_OVERRIDE
2 M25
BSC_S_SCL
M24 C262 0.1uF
BSC_S_SDA
AA23
Near J1603 Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace
COMP2_VID_INCM
A1.2V
3 VCXO_AGND_1
AB24
VCXO_AGND_2

R245
R6 AC24 L203
USB_AVSS_1 VCXO_AGND_3

34
T6 AF25 BLM18PG121SN1D
4
A3.3V USB_AVSS_2 VCXO_AVDD1P2
R7 AF24 C233 C235
A1.2V USB_AVSS_3 VCXO_PLL_AUDIO_TESTOUT 0.1uF 4.7uF
A2.5V T7
USB_AVSS_4
T8
USB_AVSS_5 +3.3V_NORMAL
R3 P24
USB_AVDD1P2 RESET_OUTB
U3 F6 SYS_RESETb
USB_AVDD1P2PLL RESETB 001:A6;001:B7 C2015 0.1uF
L200 T4 N24 4.7K Near P1600 R_VID_INCM
BLM18PG121SN1D USB_AVDD2P5 NMIB Run Along DSUB_R Trace 003:A5
T3 J5 R221
USB_AVDD2P5REF TMODE_0
R4 J4 A2.5V
USB_AVDD3P3 TMODE_1 C2016 0.1uF
U4 J6 L211 G_VID_INCM
USB_RREF TMODE_2 BLM18PG121SN1D Run Along DSUB_G Trace 003:A5
V1 J3
0.1uF
0.1uF
0.1uF

4.7uF
0.1uF

BT_DM USB_DM1 TMODE_3


V2 V25 A1.2V C264 0.1uF
Route INCM between associated BT_DP USB_DP1 SPI_S_MISO C231 C234 B_VID_INCM
C201 R209 U1 AH3 10uF 0.1uF
003:A5

R246

R247
left and right signals of same channel 3.9K SIDE_USB_DM Run Along DSUB_B Trace

R251
100pF USB_DM2 POR_OTP_VDD2P5
U2 AB8

34

34

34
D3.3V SIDE_USB_DP USB_DP2 POR_VDD1P2
The INCM trace ends at the T5 +3.3V_NORMAL
C207

C208
C209
C202
C203

R210 USB_MONCDR
same point where the connector 120 R5 H4
ground connects to the board ground USB_MONPLL EJTAG_TCK
R266 R1 H3
(thru-hole connector pin). OPT OPT
R235 USB_PWRFLT_1 EJTAG_TDI
2.7K R2 H2 R224 R225
Place test points, resistors USB_PWRFLT_2 EJTAG_TDO
2.7K T2 H1 2.7K 2.7K
near audio connector. USB_PWRON_1 EJTAG_TMS
T1 G1 1K R249
Connect the other side of C2011 0.1uF
USB_PWRON_2 EJTAG_TRSTB
the resistor to GND as close H6 Near J1500 SC1_CVBS_INCM 003:A3
as possible to the ground EJTAG_CE0 Run Along SC1_CVBS_IN Trace
H5
connection of the associated EJTAG_CE1
audio connector. R218 P6

R260
240 1K R219 EPHY_VREF R226
P5 L204 A1.2V R227

34
EPHY_RDAC BLM18PG121SN1D 2.7K 2.7K
P3 AB26
EPHY_RDN EPHY_RDN PLL_MAIN_AVDD1P2
P2 AC25
EPHY_RDP EPHY_RDP PLL_MAIN_AGND
N3 AB27 R240
A2.5V A1.2V
EPHY_TDN EPHY_TDN PLL_MAIN_MIPS_EREF_TESTOUT
N2 M6 390 L207 A1.2V C2023 0.1uF
BLM18PG121SN1D EPHY_TDP EPHY_TDP PLL_RAP_AVD_TESTOUT Near J1501 SIDE_AV_CVBS_INCM 003:A3
P1 N6 OPT BLM18PG121SN1D
BLM18PG121SN1D L209 Run Along SC2_CVBS_IN Trace
EPHY_AVDD1P2 PLL_RAP_AVD_AVDD1P2
P4 N7
0.1uF

4.7uF
0.1uF

BLM18PG121SN1D
4.7uF

C240
C241

C237

EPHY_AVDD2P5 PLL_RAP_AVD_AGND
C238

R261
N4
L212 EPHY_PLL_VDD1P2

34
C2026 C244 N1
0.1uF

4.7uF

L210
C2020

C2021

C2018
0.1uF

4.7uF

4.7uF 0.1uF EPHY_AGND_1


C247

N5 AA24
16V EPHY_AGND_2 BYP_CPU_CLK
P7 Y24
EPHY_AGND_3 BYP_DS_CLK
AE24 1K R222
BYP_SYS216_CLK
AD25 1K R262
BYP_SYS175_CLK
041:B5 R204 51 C206 0.015uF AE6
REAR_AV_L_IN AUDMX_LEFT1 TP is Necessory
041:B5 REAR_AV_R_IN
002:J6 REAR_AV_LR_INCM
R214 51 C210 0.015uF AD7
AF6
AUDMX_RIGHT1 AUDIO INCM
AUDMX_INCM1
COMP2_L_IN R215 51 C211 0.015uF AH4
R228 51 C232 0.015uF AG5
AUDMX_LEFT2 PLACE NEAR BCM CHIP
COMP2_R_IN
AUDMX_RIGHT2
002:J6 COMP2_LR_INCM
AG4
AUDMX_INCM2
PLACE NEAR Jacks
041:B5 R229 51 C220 0.015uF AG6
SC1_L_IN AUDMX_LEFT3 5.1
041:B5 R230 51 C221 0.015uF AF7
SC1_R_IN AUDMX_RIGHT3 SIDE_AV_LR_INCM
002:J7 AE7 Near J1501
SC1_LR_INCM AUDMX_INCM3 R256 002:C6
AH5 Route Between SC2_L_IN & SC2_R_IN 0.15uF
041:B5 R231 51 C224 0.015uF
SIDE_AV_L_IN AUDMX_LEFT4 C2014 0.47uF
041:B5 R232 51 C225 0.015uF AG7
SIDE_AV_R_IN AUDMX_RIGHT4 C271
AH6
002:J6 SIDE_AV_LR_INCM AUDMX_INCM4
009:I3 R233 51 C226 0.015uF AD8
PC_L_IN AUDMX_LEFT5 5.1
009:I3 R234 51 C227 0.015uF AF8
PC_R_IN AUDMX_RIGHT5 002:C6
REAR_AV_LR_INCM
002:J7
AE8 Near J1600 R258 Route Between AV1_L_IN & AV1_R_IN
PC_LR_INCM AUDMX_INCM5 0.15uF
AH7
AUDMX_LEFT6 C2024 0.47uF
AH8
AUDMX_RIGHT6 C2017
AG8
AUDMX_INCM6
AF5
AUDMX_AVSS_1
AB9
AUDMX_AVSS_2 5.1
AA10
C2027 0.047uF
0.047uF

0.047uF
0.047uF
0.047uF
0.047uF
0.047uF
0.047uF
0.047uF
0.047uF

COMP2_LR_INCM
AUDMX_AVSS_3
AB10 Near J1603 R259 Route Between COMP1_L_IN & COMP1_R_IN 0.15uF 002:C6
AUDMX_AVSS_4 C2025
0
0

AA11 C265
C222 AUDMX_AVSS_5 0.47uF
AB11
0.1uF AUDMX_AVSS_6
AC8
C277
C279
C296
C298
C299
C252
C253
C254
C256

AUDMX_LDO_CAP
R264

R265

AE5
AUDMX_AVDD2P5
5.1
SC1_LR_INCM
Near J1500 R257 Route Between SC1_L_IN & SC1_R_IN 0.15uF
002:C6
C2022 0.47uF
A2.5V C270

C217 5.1
10uF PC_LR_INCM
Near J1602 R252 Route Between PC_L_IN & PC_R_IN 0.15uF
002:C6
C269 0.47uF
C2010

Near Q1704
TU_SIF_INCM 003:A3
Route Along With TUNER_SIF_IF_N
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (EUROBBTV) 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 AUD_IN/LVDS 2

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
D1.2V
D3.3V
Place here for common circuit with ATSC D1.2V

+1.8V_AMP +1.8V_HDMI +3.3V_NORMAL A3.3V


C245 C255 C377 C375 C263 C373 C267 C289 C291
L111 C383 C246 C378 C376 C259 C374 C366 C266 C288 C290 4.7uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF 10uF
BLM18PG121SN1D L112 C243 C249 C250 C382 C381 C380 C379 C286 C287 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF
CIC21J501NE 0.1uF 4.7uF 1000pF 0.01uF 0.1uF 10uF 10uF 33uF 100uF

C2008 FOR ESD


C2007
0.1uF 0.1uF
16V 16V

D3.3V D1.8V
IC100
26page : TUNER(HALF NIM) LGE3556C (C0 VERSION)

AG28 AE18 C216 C268 C371 C370 C369 C292 C293 C294
TU_IF_AGC_1 DS_AGCI_CTL I2S_CLK_IN C274 C272 C275 C276 C278 C280 C297
AH28 AF18 0.1uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF C2004
TU_IF_AGC_2 DS_AGCT_CTL I2S_CLK_OUT AUD_SCK 0.1uF 0.1uF 0.1uF 0.1uF 4.7uF 4.7uF 4.7uF 33uF
AA21 AD17
EDSAFE_AVSS_1 I2S_DATA_IN
A2.5V AB22 AH19
TU_IF_AGC_1 EDSAFE_AVSS_2 I2S_DATA_OUT AUD_LRCH
AF26 AD18
EDSAFE_AVSS_3 I2S_LR_IN
TU_IF_AGC_2 A1.2V AF27 AG18
BLM18PG121SN1D EDSAFE_AVSS_4 I2S_LR_OUT AUD_LRCK
AF28 AG26
L102 EDSAFE_AVSS_5 AUD_LEFT0_N HP_LOUT_N A2.5V
AG27 AH26
EDSAFE_AVDD2P5 AUD_LEFT0_P HP_LOUT_P
TU_IF_N_1 AE26 AF23
EDSAFE_DVDD1P2 AUD_AVDD2P5_0
TU_IF_P_1 AE28 AA20 C147 C155 C162
C113 C172 EDSAFE_IF_N AUD_AVSS_0_1 0.01uF 0.1uF 10uF
A1.2V AE27 AB21
0.1uF 4.7uF EDSAFE_IF_P AUD_AVSS_0_2
C144 AD24 AC22
TU_IF_N_1 L103 0.1uF PLL_DS_AGND AUD_AVSS_0_3 D1.8V
AB19 AC23
PLL_DS_AVDD1P2 AUD_AVSS_0_4
TU_IF_P_1 BLM18PG121SN1D C119 C122 AB25 AD23
PLL_DS_TESTOUT AUD_AVSS_0_5 D1.8V
0.1uF 4.7uF AH25
A1.2V AUD_RIGHT0_N HP_ROUT_N
A2.5V AG25
AUD_RIGHT0_P HP_ROUT_P
AB18 AH23
BLM18PG121SN1D SD_V5_AVDD1P2 AUD_LEFT1_N BT_LOUT_N
C111 C112 AC17 AG23
SD_V5_AVDD2P5 AUD_LEFT1_P BT_LOUT_P
0.1uF 0.1uF AB17 AG24 C282 C283 C284 C285 C2005 C2006
L104 C120 C123
SD_V5_AVSS AUD_RIGHT1_N BT_ROUT_N C248 C281 C365 C364 C363 C357 C348 C320 C319 C318 C304
1000pF 0.01uF AD14 AH24 1000pF 1000pF 1000pF 1000pF 0.01uF 0.01uF 0.01uF 0.01uF C356
SD_V1_AVDD1P2 BT_ROUT_P 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
BLM18PG121SN1D AUD_RIGHT1_P
AD16 AE22 16V 16V 16V 10V 16V 16V 16V 16V 16V 16V
SD_V1_AVDD2P5 AUD_AVDD2P5_1
L105 AB15 AB20 C148 C156 C163
SD_V1_AVSS_1 AUD_AVSS_1_1 0.01uF 0.1uF 10uF
C117 AC15 AC21
SD_V1_AVSS_2 AUD_AVSS_1_2
1000pF C118 AD13 AE23
0.01uF SD_V2_AVDD1P2 AUD_AVSS_1_3
AE13 AF21 SCART1_Lout_N
SD_V2_AVDD2P5 AUD_LEFT2_N
DSUB AC13 AE21 SCART1_Lout_P
SD_V2_AVSS_1 AUD_LEFT2_P
AB14 AF22
SD_V2_AVSS_2 AUD_RIGHT2_N SCART1_Rout_N
DSUB_R AC14 AG22
SD_V2_AVSS_3 AUD_RIGHT2_P SCART1_Rout_P
R_VID_INCM AC12 AD21
DSUB_G SD_V3_AVDD1P2 AUD_AVDD2P5_2
AD12 AC20 C149 C157 C164
SD_V3_AVDD2P5 AUD_AVSS_2_1 0.01uF 0.1uF 10uF
G_VID_INCM AB13 AD22
DSUB_B SD_V3_AVSS_1 AUD_AVSS_2_2
AA14 AH2
COMPONENT SD_V3_AVSS_2 AUD_SPDIF SPDIF_OUT
B_VID_INCM AC11 AC6
SD_V4_AVDD1P2 SPDIF_AVDD2P5
R195 10 AD11 AE4
COMP2_Y SD_V4_AVDD2P5 SPDIF_AVSS C150
1%
C169 47pF

AB12 AF3 0.1uF


COMP2_Pr +5V_NORMAL IC100
C101 47pF

SD_V4_AVSS SPDIF_IN_N
C17047pF

C127 0.1uF AD10 AH1


COMP2_Pb
AC10
SD_R SPDIF_IN_P LGE3556C (C0 VERSION)
R2035

COMP2_VID_INCM SD_INCM_R
C104 OPT

C128 0.1uF AE9


R312 75

R131 75

R2036
R120 82

SD_G 1K D1.2V
0

AF9 AG1 IC100


1%

SD_INCM_G HDMI_RX_0_CEC_DAT AD5 P16


C129 0.1uF AH9 AA6 LGE3556C (C0 VERSION) DVSS_1 DVSS_62
1%

1%

SD_B HDMI_RX_0_HTPLG_IN AD6 R16


AG9 AA5 R309 10K DVSS_2 DVSS_63
A2.5V J7 T16
C130 SD_INCM_B HDMI_RX_0_HTPLG_OUT
0.1uF AG15 AB3 0 R307 DVSS_3 DVSS_64
SC1_RGB(EU)/COMPNENT1[NON_EU] SD_Y1 HDMI_RX_0_DDC_SCL HDMI_SCL K7 U16
C131 0.1uF AE15 Y6 0 R308 H8 DVSS_4 DVSS_65
SD_PR1 HDMI_RX_0_DDC_SDA HDMI_SDA VDDC_1 L7 V16
COMP1_Y ==> C132 0.1uF AF15 AC4 499 R152 J8 DVSS_5 DVSS_66
SC1_G VDDC_2 M7 AA16
SD_PB1 HDMI_RX_0_RESREF C3006 K8
COMP1_Pr ==> SC1_R AH15 AC1 DVSS_6 DVSS_67
SD_INCM_COMP1 HDMI_RX_0_CLK_N HDMI_CLK- 0.1uF VDDC_3 AB7 D17
COMP1_Pb ==> SC1_B C133 0.1uF AG16 AC2 L8 DVSS_7 DVSS_68
SD_Y2 HDMI_RX_0_CLK_P HDMI_CLK+ 16V VDDC_4 AC7 L17
C134 0.1uF AF16 AD1 M8 DVSS_8 DVSS_69
SC1_RGB_INCM VDDC_5 G8 M17
C105 OPT

HDMI_RX0-
75

75

75

SD_PR2 HDMI_RX_0_DATA0_N N8
0.1uF AH17 AD2 DVSS_9 DVSS_70
OPT 1%

C135 A3.3V VDDC_6 D9 N17


NON_EU SD_PB2 HDMI_RX_0_DATA0_P HDMI_RX0+
ONLY USE NON_EU P8 DVSS_10
NON_EU

AH16 AE1 DVSS_71


NON_EU
1%

AA9 P17
R135

1%

R135-*1 HDMI_RX1- VDDC_7


R315

R313

FOR COMP 1 SD_INCM_COMP2 HDMI_RX_0_DATA1_N R8


82 1% C174 0.1uF AG14 AE2 DVSS_11 DVSS_72
SD_Y3 HDMI_RX_0_DATA1_P HDMI_RX1+ VDDC_8 G10 R17
C175 0.1uF AE14 AF1 BLM18PG121SN1D AA8 DVSS_12 DVSS_73
SIDE COMPONENT SD_PR3 HDMI_RX_0_DATA2_N HDMI_RX2- VDDC_9 A11 T17
0.1uF AF14 AF2 L109 H9 DVSS_13 DVSS_74
R196 C176 VDDC_10 L11 U17
SD_PB3 HDMI_RX_0_DATA2_P HDMI_RX2+
10 AH14 AD3 A1.2V A2.5V H10 DVSS_14 DVSS_75
SIDE_COMP_Y SD_INCM_COMP3 HDMI_RX_0_VDD3P3 VDDC_11 M11 V17
AH10 AE3 H11 DVSS_15 DVSS_76
1% SD_L1 HDMI_RX_0_VDD1P2 VDDC_12 N11 AA17
SIDE_COMP_Pr
C177 OPT

H12
R165 82

R166 75

AG10 AC3 DVSS_16 DVSS_77


R167 75

SIDE_COMP_Pb SD_C1 HDMI_RX_0_VDD2P5 VDDC_13 P11 AC19


AE10 AD4 C145 C153 C160 H13 DVSS_17 DVSS_78
1%

SIDE_COMP_INCM NON_EU NON_EU SD_INCM_LC1 HDMI_RX_0_AVSS_1 VDDC_14 R11 G18


AE11 AB5 4.7uF 0.1uF 0.1uF H14 DVSS_18 DVSS_79
1%

R2112-*1 R141-*1
1%

SD_L2 HDMI_RX_0_AVSS_2 BLM18PG121SN1D VDDC_15 T11 L18


SIDE_COMP_Y AF11 AB6 H15 DVSS_19 DVSS_80
5% 12 5% 62 SD_C2 HDMI_RX_0_AVSS_3 L107 VDDC_16 U11 M18
SIDE_COMP_Pr AH11 AG2 H16 DVSS_20 DVSS_81
SD_INCM_LC2 HDMI_RX_0_AVSS_4 VDDC_17 V11 N18
SIDE_COMP_Pb R100 62 AH13 AB4 H17 DVSS_21 DVSS_82
SD_L3 HDMI_RX_0_AVSS_5 VDDC_18 D12 P18
SIDE_COMP_INCM R142 OPT AE12 AA7 H18 DVSS_22 DVSS_83
CVBS R143 62 SD_C3 HDMI_RX_0_AVSS_6 VDDC_19 G12 R18
EU AF12 Y8 H19 DVSS_23 DVSS_84
R2112
R141 75 1% EU SD_INCM_LC3 HDMI_RX_0_PLL_AVSS C158 C151 C165 VDDC_20 L12 T18
C110 0.1uF AD9 AC5 H21 DVSS_24 DVSS_85
TU_CVBS 1000pF 0.01uF 10uF VDDC_21 M12 U18
R2113 SD_CVBS1 HDMI_RX_0_PLL_DVDD1P2 J21
1% 18 C124 0.1uF AG11 W8 DVSS_25 DVSS_86
REAR_AV_CVBS SD_CVBS2 HDMI_RX_0_PLL_DVSS VDDC_22 N12 V18
12 R2114 C125 0.1uF AG12 K21 DVSS_26 DVSS_87
SC1_CVBS_IN SD_CVBS3 D3.3V VDDC_23 P12 D20
10K
10K

10K

10K

0 R2115 C100 0.1uF AF13 L21 DVSS_27 DVSS_88


R2037

SD_CVBS4 VDDC_24 R12 G20


OPT

SIDE_AV_CVBS M21 DVSS_28 DVSS_89


12 AC9 AA3
TU_CVBS_INCM SD_INCM_CVBS1 HDMI_RX_1_CEC_DAT VDDC_25 T12 H20
AF10 V4 N21 DVSS_29 DVSS_90
REAR_AV_CVBS_INCM VDDC_26 U12 A21
R310

R2039

SD_INCM_CVBS2 HDMI_RX_1_HTPLG_IN
R2038

A2.5V A2.5V AH12 U6 P21 DVSS_30 DVSS_91


SC1_CVBS_INCM SD_INCM_CVBS3 HDMI_RX_1_HTPLG_OUT VDDC_27 V12 E21
AG13 V5 R21 DVSS_31 DVSS_92
SD_INCM_CVBS4 HDMI_RX_1_DDC_SCL VDDC_28 L13 F21
SIDE_AV_CVBS_INCM AF17 V3 T21 DVSS_32 DVSS_93
SD_SIF1 HDMI_RX_1_DDC_SDA VDDC_29 M13 G21
R137 R4020 AG17 W4 499 R153 A3.3V U21 DVSS_33 DVSS_94
10K SD_INCM_SIF1 HDMI_RX_1_RESREF VDDC_30 N13 E22
10K AD15 W2 V21 DVSS_34 DVSS_95
0.1uF OPT VDDC_31 P13 F22
SD_FB HDMI_RX_1_CLK_N W21
R128 C106 A1.2V AE16 W3 DVSS_35 DVSS_96
SC1_ID SD_FS HDMI_RX_1_CLK_P R205 VDDC_32 R13 G22
0 L106 AE17 Y1 Y21 DVSS_36 DVSS_97
TU_SIF BLM18PG121SN1D SD_FS2 HDMI_RX_1_DATA0_N 20 VDDC_33 T13 H22
AB16 Y2 DVSS_37 DVSS_98
OPT

R3055 HDMI_RX_1_DATA0_P A3.3V U13 J22


R139 AA15 PLL_VAFE_AVDD1P2 AA2 DVSS_38 DVSS_99
240 C121 C140 V13 K22
12K PLL_VAFE_AVSS HDMI_RX_1_DATA1_N AH27
0.1uF 4.7uF AC16 AA1 DVSS_39 DVSS_100
HDMI_RX_1_DATA1_P AGC_VDDO G14 L22
TU_SIF_INCM AG3 PLL_VAFE_TESTOUT AB2 BLM18PG121SN1D D3.3V DVSS_40 DVSS_101
RGB_HSYNC L14 M22
R4021

HDMI_RX_1_DATA2_N L110
AF4 AB1 DVSS_41 DVSS_102
M14 N22
12K

C4020 RGB_VSYNC HDMI_RX_1_DATA2_P C2003


120
R3056

A1.2V A2.5V AA12 DVSS_42 DVSS_103


OPT

Y3
0.1uF HDMI_RX_1_VDD3P3 0.1uF VDDO_1 N14 P22
Y4 AA13 DVSS_43 DVSS_104
HDMI_RX_1_VDD1P2 VDDO_2 P14 R22
W5 AA18 DVSS_44 DVSS_105
HDMI_RX_1_VDD2P5 VDDO_3 R14 T22
W1 AA19 DVSS_45 DVSS_106
HDMI_RX_1_AVSS_1 VDDO_4 T14 U22
U5 C146 C154 C161 E28 DVSS_46 DVSS_107
RGB_HSYNC HDMI_RX_1_AVSS_2 VDDO_5 U14 V22
W6 4.7uF 0.1uF 0.1uF L28 DVSS_47 DVSS_108
RGB_VSYNC HDMI_RX_1_AVSS_3 VDDO_6 V14 W22
CONNECT NEAR BCM CHIP U7 U28 DVSS_48 DVSS_109
HDMI_RX_1_AVSS_4 FOR ESD VDDO_7 L15 Y22
V7 AB28 DVSS_49 DVSS_110
R2117 VDDO_8 M15 AA22
0 HDMI_RX_1_AVSS_5 BLM18PG121SN1D
W7 D1.8V DVSS_50 DVSS_111
SC1_FB HDMI_RX_1_AVSS_6 L108 C384 N15 W23
U8 33uF DVSS_51 DVSS_112
HDMI_RX_1_AVSS_7 P15 AB23
V8 10V A9 DVSS_52 DVSS_113
HDMI_RX_1_AVSS_8 DDRV_1 R15 F28
Y5 G9 DVSS_53 DVSS_114
HDMI_RX_1_AVSS_9 DDRV_2 T15 M28
0
R2116
OPT

V6 G11 DVSS_54 DVSS_115


HDMI_RX_1_PLL_AVSS DDRV_3 U15 T28
AA4 G13 DVSS_55 DVSS_116
HDMI_RX_1_PLL_DVDD1P2 DDRV_4 V15 AC28
Y7 C159 C152 C166 A14 DVSS_56 DVSS_117
HDMI_RX_1_PLL_DVSS DDRV_5 A16
1000pF 0.01uF 10uF G15 DVSS_57
DDRV_6 G16
G17 DVSS_58
DDRV_7 L16
A19 DVSS_59
DDRV_8 M16
G19 DVSS_60
DDRV_9 N16
DVSS_61

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EUROBBTV 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 VIDEO IN 3

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
D1.8V
A1.2V
IC100
LGE3556C (C0 VERSION) D1.8V

A6 0.1uF C403

0.047uF
0.047uF
DDR_BVDD0

0.047uF
0.047uF

0.047uF
C451

C454

C455

C456

C457

C458

C459

C460

C461
C441
0.047uF

C442
0.1uF

C443

C444

C445

C446

C447

C448

470pF

470pF

0.047uF

0.047uF
A24

C440
470pF

0.1uF

0.1uF

C469
10uF

C470

C471

C472

C473

C474

C475

C476

C477

C478

C479

C480

C481

C482

C495
0.1uF C404

C465
10uF

10uF

C462

C468
0.1uF

470pF

470pF
10uF

470pF

0.1uF

10uF

22uF

0.1uF

0.1uF
470pF

0.1uF

470pF

10uF

10uF

10uF
22uF
DDR_BVDD1

10uF
10uF
B7
DDR_BVSS0
B24
DDR_BVSS1
F20
DDR_PLL_TEST
B23 R411 0
DDR_PLL_LDO
B17 OPT DDR01_CKE
DDR01_CKE
C22
DDR_VTT
R412 240
DDR_COMP IC400 IC402
E16 1% DDR01_ODT DDR1_DQ[0-7]
DDR01_ODT NT5TU128M8DE_BD NT5TU128M8DE_BD
C23 DDR0_DQ[0-7] 004:B6 004:B5
DDR_EXT_CLK
DDR0_CLK
B12 DDR0_CLK 004:C7;004:C4 004:A7;004:C4 DDR0_CLK 004:A7;004:F4 DDR1_CLK DDR01_A[0-3,7-13] SI
C12 R406 R407
DDR0_CLKb 004:C7;004:C4 E8 C8 DDR0_DQ[0] E8 C8 DDR1_DQ[0] DDR01_RASb
DDR0_CLKB 100 CK DQ0 100 CK DQ0
A13 DDR1_CLK 004:F7;004:F4 1% F8 C2 DDR0_DQ[1] F8 C2
DDR1_CLK 004:A7;004:C4 DDR0_CLKb 004:A7;004:F4 DDR1_CLKb 1% DDR1_DQ[1] DDR01_A[2] C485
A12 CK DQ1 CK DQ1
DDR1_CLKb 004:F7;004:F4 DDR01_CKE F2 D7 DDR0_DQ[2] DDR01_CKE F2 D7 DDR1_DQ[5] DDR1_A[4-6] DDR01_A[0] 0.1uF
DDR1_CLKB CKE DQ2 CKE DQ2
B15 DDR01_A[0] D3 DDR0_DQ[3] D3
DDR01_A00 DDR1_DQ[3] DDR1_A[6] 75
E14 DDR01_A[1] DQ3 DQ3 AR400
DDR01_A[0-3] D1 DDR0_DQ[4] D1 DDR1_DQ[4] DDR0_A[4-6] DDR01_CASb
DDR01_A01 DQ4 DQ4 C486
A15 DDR01_A[2] F7 D9 DDR0_DQ[5] F7 D9 R408 75 0.1uF
DDR01_A02 DDR01_RASb DDR01_RASb DDR1_DQ[2]
D15 DDR01_A[3] RAS DQ5 RAS DQ5
DDR01_CASb G7 B1 DDR0_DQ[6] DDR01_CASb G7 B1 DDR1_DQ[6] DDR01_A[12] R409 75
DDR01_A03 CAS DQ6 CAS DQ6
E13 DDR0_A[4] DDR0_A[4-6] F3 B9 DDR0_DQ[7] F3 B9
DDR0_A04 DDR01_WEb DDR01_WEb DDR1_DQ[7] DDR01_A[9] C487
E12 DDR0_A[5] WE DQ7 WE DQ7
G8 G8 DDR01_A[7] 0.1uF
DDR0_A05 CS CS
F13 DDR0_A[6]
DDR0_A06 DDR01_BA0 DDR01_BA0 DDR1_A[5] 75
C14 DDR01_A[7] B7 B7 AR401
DDR01_A07 DDR01_BA1 DDR0_DQS0 004:A4 DDR01_BA1 DDR1_DQS0 004:A4 DDR1_A[4] C488
F14 DDR01_A[8] DQS DQS
G2 A8 DDR0_DQS0b G2 A8 DDR1_DQS0b 004:A3 DDR01_A[11] 75 0.1uF
DDR01_A08 BA0 DQS 004:A4 BA0 DQS
B14 DDR01_A[9] DDR01_A[7-13] G3 B3 G3 B3
DDR01_A09 DDR0_DM0 004:A4 DDR1_DM0 004:A4 DDR01_A[8]
D14 DDR01_A[10] BA1 DM/RDQS BA1 DM/RDQS
DDR01_BA2 G1 A2 DDR01_BA2 G1 A2 DDR01_A[13]
DDR01_A10 NC_1/BA2 NU/RDQS NC_1/BA2 NU/RDQS C489
C13 DDR01_A[11]
DDR01_A11 DDR01_A[0-3,7-13] DDR01_A[0-3,7-13] DDR01_A[3] AR402 0.1uF
D13 DDR01_A[12] D1.8V D1.8V
DDR01_A12 DDR01_A[1]
B13 DDR01_A[13] H8 A9 H8 A9
DDR0_A[4-6] DDR01_A[0] DDR01_A[0] DDR01_A[10]
DDR01_A13
F15 DDR1_A[4] A0 VDDQ_1 004:B6;004:F3;004:I7 DDR1_A[4-6] A0 VDDQ_1 C490
DDR1_A[4-6] DDR01_A[1] H3 C1 DDR01_A[1] H3 C1 DDR01_BA1 75 0.1uF
DDR1_A04 A1 VDDQ_2 A1 VDDQ_2
C15 DDR1_A[5] H7 C3 H7 C3 AR403
DDR1_A05 DDR01_A[2] DDR01_A[2] DDR01_BA0
D16 DDR1_A[6] A2 VDDQ_3 A2 VDDQ_3
DDR01_A[3] J2 C7 DDR01_A[3] J2 C7 DDR01_BA2
DDR1_A06 A3 VDDQ_4 A3 VDDQ_4
F16 DDR01_BA0 DDR0_A[4] J8 C9 DDR1_A[4] J8 C9
DDR01_BA0 DDR01_WEb
B16 A4 VDDQ_5 A4 VDDQ_5
DDR01_BA1 DDR0_A[5] J3 A1 DDR1_A[5] J3 A1 75
DDR01_BA1 A5 VDD_1 A5 VDD_1 DDR01_CKE C499
E15 DDR01_BA2 DDR0_A[6] J7 L1 DDR1_A[6] J7 L1 AR404 0.1uF
DDR01_BA2 A6 VDD_2 A6 VDD_2 DDR01_ODT
A17 DDR01_CASb K2 E9 K2 E9
DDR01_CASB DDR01_A[7] DDR01_A[7] R410 75
A8 A7 VDD_3 A7 VDD_3 C421
DDR0_DQ[0] DDR0_DQ[0-7] DDR01_A[8] K8 H9 DDR01_A[8] K8 H9 0.1uF
DDR0_DQ00 A8 VDD_4 A8 VDD_4
B11 DDR0_DQ[1] K3 K3
DDR0_DQ01 DDR01_A[9] DDR01_A[9]
B8 A9 A9 DDR_VTT
DDR0_DQ02
D11
DDR0_DQ[2]
DDR0_DQ[3]
DDR01_A[10]
DDR01_A[11]
H2
K7
A10/AP VSSQ_1
A7
B2
DDR01_A[10]
DDR01_A[11]
H2
K7
A10/AP VSSQ_1
A7
B2
PI
DDR0_DQ03 A11 VSSQ_2 A11 VSSQ_2
E11 DDR0_DQ[4] DDR01_A[12] L2 B8 L2 B8
DDR0_DQ04 DDR01_A[12]
C8 DDR0_DQ[5] A12 VSSQ_3 A12 VSSQ_3
DDR01_A[13] L8 D2 DDR01_A[13] L8 D2
DDR0_DQ05 A13 VSSQ_4 A13 VSSQ_4
C11 DDR0_DQ[6] D8 D8
DDR0_DQ06 DDR0_DQ[8-15] DDR01_RASb
C9 DDR0_DQ[7] VSSQ_5 VSSQ_5
A3 A3 DDR01_A[2]
DDR0_DQ07 VSS_1 VSS_1 C491
D8 DDR0_DQ[8] E3 E3 0.1uF
DDR0_DQ08 DDR01_A[0]
E10 L3 VSS_2 L3 VSS_2
DDR0_DQ[9] NC_2/A14 J1 NC_2/A14 J1 DDR0_A[6] 75
DDR0_DQ09 L7 VSS_3 DDR0_VREF0 L7 VSS_3 DDR1_VREF0
E9 DDR0_DQ[10] NC_3/A15 K9 NC_3/A15 K9 AR405
DDR0_DQ10 DDR01_A[3]
F11 DDR0_DQ[11] VSS_4 VSS_4
DDR0_DQ11 DDR01_A[1] C483
F12 004:A7;004:C5;004:C2;004:F2;004:I4;004:I6
DDR0_DQ[12] F9 E2 F9 E2 DDR01_A[10] 0.1uF
DDR0_DQ12 DDR01_ODT DDR01_ODT
E8 DDR0_DQ[13] ODT VREF ODT VREF
E1 E1 C463 C466 DDR01_BA1 75
DDR0_DQ13 VDDL C449 C452 VDDL
D10 DDR0_DQ[14] E7 E7
DDR0_DQ14 DDR01_A[12] AR406
F8 DDR0_DQ[15] VSSDL VSSDL 470pF 0.1uF
DDR1_DQ[0-7] 0.1uF 470pF DDR01_A[9]
DDR0_DQ15 C484
C18 DDR1_DQ[0] 0.1uF
DDR1_DQ00 DDR01_A[7]
C20 DDR1_DQ[1]
DDR1_DQ01 DDR0_A[5] 75
A18 DDR1_DQ[2] AR407
DDR1_DQ02 DDR0_A[4]
B21 DDR1_DQ[3]
DDR1_DQ03 DDR01_A[11] C492
DDR1_DQ04
C21 DDR1_DQ[4] DDR1_DQ[8-15]
Close to IC Close to IC DDR01_A[8] 0.1uF
B18 DDR1_DQ[5]
DDR1_DQ05 DDR01_A[13] 75
B20 DDR1_DQ[6] AR408
DDR1_DQ06 DDR01_BA0
D18 DDR1_DQ[7]
DDR1_DQ07 DDR01_BA2 C493
E18 DDR1_DQ[8] 0.1uF
DDR1_DQ08 DDR01_WEb
D21 DDR1_DQ[9]
DDR1_DQ09 75
F18 DDR1_DQ[10] DDR01_CKE
AR409
DDR1_DQ10 DDR01_ODT
E20 DDR1_DQ[11]
DDR1_DQ11 R404 75
A22 DDR1_DQ[12] C494
DDR1_DQ12 0.1uF
F17 DDR1_DQ[13]
DDR1_DQ13
B22 DDR1_DQ[14]
DDR1_DQ14
E17 DDR1_DQ[15]
DDR1_DQ15
A10 DDR0_DM0 004:E6
DDR0_DM0 IC401 IC403 DDR1_DQ[8-15] C496
C10 DDR0_DM1 004:E3 0.1uF
DDR0_DM1 NT5TU128M8DE_BD DDR0_DQ[8-15]
NT5TU128M8DE_BD
A20 DDR1_DM0 004:H6 004:B5
DDR1_DM0
F19 DDR1_DM1 004:H3 004:A7;004:C7 DDR0_CLK DDR1_CLK C497
DDR1_DM1 0.1uF
B10 DDR0_DQS0 004:E6 E8 C8 E8 C8
DDR0_DQS0 DDR0_DQ[9] DDR1_DQ[9]
B9 CK DQ0 CK DQ0
DDR0_DQS0b 004:E6 DDR0_CLKb F8 C2 DDR0_DQ[8] DDR1_CLKb F8 C2 DDR1_DQ[8]
DDR0_DQS0B 004:A7;004:C7 CK DQ1 CK DQ1 C498
F10 DDR0_DQS1 004:E3 F2 D7 F2 D7
DDR0_DQS1 DDR01_CKE DDR0_DQ[12] DDR01_CKE DDR1_DQ[12] 0.1uF
F9 CKE DQ2 CKE DQ2
DDR0_DQS1b 004:E3 004:A7;004:C7;004:F7;004:F4 D3 DDR0_DQ[13] D3 DDR1_DQ[13]
DDR0_DQS1B DQ3 DQ3
B19
DDR1_DQS0
C19
DDR1_DQS0 004:H6
DDR1_DQS0b 004:H6 F7
DQ4
D1
D9
DDR0_DQ[15]
DDR0_DQ[11] F7
DQ4
D1
D9
DDR1_DQ[15]
DDR1_DQ[14]
SI
DDR1_DQS0B DDR01_RASb RAS
DDR01_RASb
RAS
E19 DQ5 DQ5
DDR1_DQS1 004:H3 DDR01_CASb G7 B1 DDR0_DQ[10] DDR01_CASb G7 B1 DDR1_DQ[10]
DDR1_DQS1 CAS DQ6 CAS DQ6
D19 DDR1_DQS1b 004:H3 F3 B9 F3 B9
DDR1_DQS1B DDR01_WEb DDR0_DQ[14] DDR01_WEb DDR1_DQ[11]
C16 DDR0_VREF0 WE DQ7 WE DQ7
DDR01_RASb G8 G8
DDR01_RASB CS CS
A7 DDR1_VREF0
DDR_VREF0 DDR01_BA0 DDR01_BA0
A23 B7 B7
DDR_VREF1 DDR01_BA1 DDR0_DQS1 004:A4 DDR01_BA1 DDR1_DQS1 004:A3
C17 D1.8V DQS DQS
DDR01_WEb G2 A8 DDR0_DQS1b G2 A8 DDR1_DQS1b 004:A3
C410

DDR01_WEB 004:A4
C400
C401

C409
C408
C405
C402

C407

C7 BA0 DQS BA0 DQS


G3 B3 DDR0_DM1 G3 B3 DDR1_DM1 004:A4
DDR_VDDP1P8_1 BA1 DM/RDQS 004:A4 BA1 DM/RDQS
D22 G1 A2 G1 A2
DDR_VDDP1P8_2 DDR01_BA2 DDR01_BA2
NC_1/BA2 NU/RDQS NC_1/BA2 NU/RDQS
C406 C415
470pF
470pF

DDR01_A[0-3,7-13] DDR01_A[0-3,7-13]
470pF
470pF
1uF

1uF

D1.8V D1.8V
1uF
1uF

0.1uF 0.1uF
DDR01_A[0] H8 A9 DDR01_A[0] H8 A9
A0 VDDQ_1 DDR1_A[4-6] A0 VDDQ_1
DDR01_A[1] H3 C1 DDR01_A[1] H3 C1
DDR0_A[4-6] A1 VDDQ_2 004:B6;004:F6;004:I7 A1 VDDQ_2
DDR01_A[2] H7 C3 DDR01_A[2] H7 C3
A2 VDDQ_3 A2 VDDQ_3
DDR01_A[3] J2 C7 DDR01_A[3] J2 C7
A3 VDDQ_4 A3 VDDQ_4
DDR0_A[4] J8 C9 DDR1_A[4] J8 C9
A4 VDDQ_5 A4 VDDQ_5
DDR0_A[5] J3 A1 DDR1_A[5] J3 A1
A5 VDD_1 A5 VDD_1
DDR0_A[6] J7 L1 DDR1_A[6] J7 L1
A6 VDD_2 A6 VDD_2
* DDR_VTT DDR01_A[7] K2
A7 VDD_3
E9 DDR01_A[7] K2
A7 VDD_3
E9
DDR01_A[8] K8 H9 DDR01_A[8] K8 H9
A8 VDD_4 A8 VDD_4
DDR01_A[9] K3 DDR01_A[9] K3
A9 A9
DDR01_A[10] H2 A7 DDR01_A[10] H2 A7
DDR_VTT D3.3V
DDR01_A[11] K7
A10/AP VSSQ_1
B2 DDR01_A[11] K7
A10/AP VSSQ_1
B2
A11 VSSQ_2 A11 VSSQ_2
DDR01_A[12] L2 B8 DDR01_A[12] L2 B8
A12 VSSQ_3 A12 VSSQ_3
DDR01_A[13] L8 D2 DDR01_A[13] L8 D2
A13 VSSQ_4 A13 VSSQ_4
D8 D8
VSSQ_5 VSSQ_5
A3 A3
IC404 VSS_1 VSS_1
C426 C425 E3 E3
10K

C417 C419 D1.8V


R418

C413 BD35331F-E2 L3 VSS_2 L3 VSS_2


22uF 22uF 10uF 10uF NC_2/A14 J1 NC_2/A14 J1
10V 10V 0.1uF L7 VSS_3 DDR0_VREF0 L7 VSS_3
10V 10V K9 K9 DDR1_VREF0
16V NC_3/A15 NC_3/A15
VSS_4 VSS_4
GND VTT
1 8 F9 E2 F9 E2
DDR01_ODT DDR01_ODT
ODT VREF ODT VREF
E1 E1
VDDL C450 C453 VDDL C464 C467
EN VTT_IN E7 E7
2 7
DDR1_VREF0 VSSDL VSSDL
0.1uF 470pF 470pF 0.1uF
VTTS VCC
3 6
DDR0_VREF0
R417
R414 0 VREF VDDQ 220
4 5

C418
Close to IC Close to IC
R415 0 C416 C420
C422 1uF
1uF 10uF 0.1uF
10V
10V 10V 16V
16V

C423
C414

C411 C412
0.1uF 0.1uF 10uF
0.1uF

16V 16V 10V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (EUROBBTV) 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR HONG YEON HYUK
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR Memory 4

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
New Item Development
EARPHONE BLOCK
HP_LOUT

OPT
C902
1000pF
50V C E
OPT
OPT JK901
Q900 B +3.3V_NORMAL KJA-PH-0-0177
MMBT3904-(F) MMBT3904-(F)
B Q903
GND 5
E

R917
C

10K
L 4
R912
1K DETECT 3
HP_DET
HP_ROUT
R 1

OPT
C903
1000pF C E
50V OPT OPT
Q901 B
MMBT3904-(F) MMBT3904-(F)+3.5V_ST
B Q902
E C

OPT
R914
10K
SIDE_HP_MUTE

COMPONENT
+3.3V_NORMAL

R902
10K
Rear CVBS
R903
1K
COMP2_DET
REAR_AV
D900 C931
5.6V REAR_AV_CVBS
100pF R957
50V REAR_AV 0 REAR_AV
C909
L904 D906 47pF
270nH 5.5V 50V
COMP2_Y
[GN]E-LUG C932 C904
D903
6A 5.1V 27pF 27pF +3.3V_NORMAL
[GN]O-SPRING 50V REAR_AV
D910 50V JK902 REAR_AV
5A 5.1V R925
PPJ233-01 10K
[GN]CONTACT REAR_AV
L903 [RD]E-LUG
4A 270nH 5C
R926
AV_CVBS_DET
[BL]E-LUG-S COMP2_Pb REAR_AV 1K
D909
D904
5.5V

C933 C906 4C [RD]O-SPRING C910


7B 5.6V
[BL]O-SPRING 27pF 27pF REAR_AV 100pF
50V 50V
50V 3C [RD]CONTACT
5B L902
[RD]E-LUG-S 270nH C941 R928
4B [WH]C-LUG 25V 0
7C COMP2_Pr
5.5V

[RD]O-SPRING_1 C934 C905 REAR_AV_R_IN


REAR_AV
D905

1uF
5C
27pF 27pF 3A [YL]CONTACT
REAR_AV
50V R921 C916
[WH]O-SPRING 50V D908
470K
C935 R910 [YL]O-SPRING 5.6V 100pF
5D 25V 4A REAR_AV 50V
0 REAR_AV
[RD]CONTACT COMP2_L_IN REAR_AV
1uF 5A [YL]E-LUG
4E D901 R907 C939 REAR_AV
[RD]O-SPRING_2 5.6V 470K C940
100pF R927
25V 0
50V
5E REAR_AV_L_IN
[RD]E-LUG 1uF
C936 R909 REAR_AV
25V REAR_AV REAR_AV REAR_AV
6E 0 R920 C915
COMP2_R_IN D907
470K 100pF
PPJ234-01 1uF 5.6V
R961 50V
JK900 D902 C937
5.6V 470K
100pF
50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EUROBBTV 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETC SUB BOARD I/F 9

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
+5V_TU

CAN H-NIM/NIM TUNER for EU L2700


BLM18PG121SN1D

VERTICAL_NIM R2738 Q2701 R2742


TU2701-*1 0 ISA1530AC1
TDFR-G155D E R2740 10K
HORIZONTAL_NIM R2754 0 RF_SWITCH_CTL 2.2K

1
RF_S/W_CNTL
TU2701 CN B
C
R2755
BST_CNTL
C
R2720 0 10K
2

3
+B1[5V] TDFR-G135D Q2703
2SC3052
B

4
NC[RF_AGC] LNA2_CTL/BOSTER_CTL
5
AS C2718 E
6
SCL[A_DEMOD]
close to TUNER 0.01uF
7
SDA[A_DEMOD] +5V_TU 25V
8
NC(IF_TP) RF_S/W_CNTL OPTION : RF AGC IC2702 +3.3V_TU
9
SIF 1 NL17SZ08DFT2G
NC C2701 C2709
10
C2708 10uF
11
VIDEO BST_CNTL 0.1uF C2706 0.1uF
GND 2 16V C2704 10V
12
0.1uF 16V FE_TS_VAL
1.2V 100pF OPT +5V_TU 1 5
13 16V OPT C2736
14
3.3V +B1[5V] 50V C
0.1uF
RESET 3 R2724
15
10K R2746 16V
2.5V Q2700 B
16 470 R2749 2
SCL[D_DEMOD] NC[RF_AGC] 2SC3052 IF_AGC_SEL 82
17
R2700 0 OPT FE_TS_ERR
18
SDA[D_DEMOD] 4 OPT
E E
TU_SIF
R2758
ERR
19
OPT 47
SYNC AS 3 4 FE_TS_VAL_ERR
20

21
VALID 5 B ISA1530AC1
MCL
22
33 R2726 R2743 Q2704
23
D0 SCL[A_DEMOD] +5V_TU 4.7K
C
24
D1 6 SCL0_3.3V
D2
25

26
D3 SDA[A_DEMOD] 33 R2727
27
D4 7 SDA0_3.3V
D5 R2739 R2741
28
C2712 C2714 200 200
29
D6 NC(IF_TP) 18pF 18pF
31
30
D7 8 50V 50V

SHIELD SIF C2702 close to TUNER TU_CVBS


9
E
0.1uF 16V R2736 0
NC
10 B Q2702
CN_VERTICAL_LGS8G85 VIDEO ISA1530AC1
C
TU2701-*2 11 +3.3V_TU
TDFR-C155D
GND +3.3V_TU
1
RF_S/W_CNTL
12 +1.2V_TU
BST_CNTL
2

3
+B1[+5V]
1.2V R2721
R2723
100K
4
NC[RF_AGC]

NC_1
13 C2700 C2703 C2705
C2707
100 TUNER_RESET
5 100pF 0.1uF 100pF 0.1uF +5V_TU
6
SCLT
3.3V 50V 16V 50V 16V C2710
7
SDAT

NC_2
14 0.1uF
8 16V
9
SIF
RESET +2.5V_TU
R2702 R2712
10
NC_3

VIDEO
15 200 200
11

12
GND
2.5V R2701 0
13
+B2[1.2V]

+B3[3.3V]
16 C2733
14 0.1uF ATV_OUT
15
RESET
SCL[D_DEMOD]
16V SCL2_3.3V
E
16
NC_4

SCL
17 R2728 33
17

18
SDA
SDA[D_DEMOD] SDA2_3.3V B Q2705
19
ERR

SYNC
18 R2729 33
ISA1530AC1
20 C
21
VALID
ERR C2713
22
MCL
19 C2711 CN CN
23
D0 10pF 10pF
50V 50V R2731-*1 R2756-*1
24
D1
SYNC 0 30K
25
D2

D3
20
26 1/16W 1/10W
27
D4
VALID 5% 1%
28
D5

D6
21 C2716
29

31
30
D7
MCL EU R2757-*1
+3.3V_TU
22 47 100pF EU
SHIELD
CN R2757 50V EU R2756
0 R2731
D0 FE_TS_ERR 18K
CN_HORIZONTAL_LGS8G85
23 EU R2717-*1
1% 22K
47
TU2701-*3 CN R2717
IC2701 1%
TDFR-C135D D1 0
FE_TS_SYNC L2703 MP2212DN Close to IC
R1 +1.2V_TU
24 EU R2716-*1
RF_S/W_CNTL 47 CIC21J501NE
1
BST_CNTL D2 CN R2716 0 10K
2
+B1[+5V] 25 EU R2711-*1 FE_TS_VAL CN EU FB EN/SYNC R2732
3
47 1 8 POWER_ON/OFF2_2
4
NC[RF_AGC] R2713-*1 R2713
NC_1 D3 CN R2711 0 FE_TS_DATA[0-7] 56K 75K L2704
5
FE_TS_DATA_CLK R2
6
SCLT 26 EU R2709-*1 1/8W GND SW_2 3.6uH
47 1/8W 1% 2 7
7

9
SDAT

NC_2

SIF 27
D4 CN R2709 0
EU R2708-*1
FE_TS_DATA[0] 1%

IN
3A SW_1
NR8040T3R6N
10
NC_3 47 3 6 C2730
CN R2708 C2731 C2735
11
VIDEO D5 0 FE_TS_DATA[1] 22uF 0.1uF 22uF
12
GND 28 EU R2707-*1 10V
+B2[1.2V] 47 BS VCC 10V
13
4 5 C2720
14
+B3[3.3V] D6 CN R2707 0 FE_TS_DATA[2] C2715
0.1uF
15
RESET 29 EU R2710-*1
22uF
+B4[2.5V] 10V 16V
16 47
17
SCL D7 CN R2710 0 FE_TS_DATA[3]
18
SDA 30 EU R2705-*1 R2719 0
19
ERR 31 47
20
SYNC CN R2705 0 FE_TS_DATA[4] R2718
21
VALID
EU R2706-*1 10 Vout=0.8*(1+R1/R2)
MCL 47 C2717
22
CN R2706 1/10W 1uF
23
D0 0 FE_TS_DATA[5] 1%
24
D1 SHIELD EU R2704-*1 10V
25
D2 47
26
D3 CN R2704 0 FE_TS_DATA[6]
D4
27 EU R2703-*1
D5
28 47
29
D6 CN R2703 0 FE_TS_DATA[7]
D7
30
31
0

SHIELD
+3.3V_NORMAL
R2725

Close to the tuner


EU

+3.3V_TU
EU_VERTICAL_NIM_T2 EU_HORIZONTAL_NIM_T2
R2722 0
TU2701-*4 TU2701-*5 FE_TS_SERIAL L2702
TDFR-G055D TDFR-G035D CN
CIC21J501NE 60mA
+3.3V_TU +2.5V_TU
RF_S/W_CNTL RF_S/W_CNTL
1 1
BST_CNTL BST_CNTL
2 2
C2722 C2724 C2734
3
+B1[5V]
3
+B1[5V] C2728 IC2700
0.1uF 0.1uF 0.1uF
NC[RF_AGC] NC[RF_AGC] 22uF
4 4
16V 16V 16V AZ2940D-2.5TRE1
5
AS
5
NC_1 10V
SCL[A_DEMOD] SCLT
6 6
SDA[A_DEMOD] SDAT VIN 1 VOUT
7
NC(IF_TP)
7
NC(IF_TP)
$0.11 3
8 8

9
SIF
9
SIF 2 R2744
NC NC_2 1
10 10
+5V_NORMAL +5V_TU GND
11
VIDEO
11
VIDEO C2719
12
GND
12
GND 0.1uF
16V C2723 C2726
13
1.2V
13
+B2[1.2V]
L2701 200mA 10uF
3.3V +B3[3.3V] 0.1uF
14
RESET
14
RESET
BLM18PG121SN1D 10V 16V
15 15
2.5V +B4[2.5V]
16 16
SCL[D_DEMOD] SCL[D_DEMOD]
17 17 C2721 C2725 C2727 C2729
18
SDA[D_DEMOD]
18
SDA[D_DEMOD]
0.1uF 0.1uF 22uF 22uF
ERR ERR 16V 10V 10V
19 19 16V
SYNC SYNC
20 20
VALID VALID
21 21
MCL MCL
22 22
D0 D0
23 23
D1 D1
24 24
D2 D2
25 25
D3 D3
26 26
D4 D4
27 27
D5 D5
28 28
D6 D6
29 29
D7 D7
30 30
31 31

SHIELD SHIELD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 27
Tuner ( Full Nim )

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
USB2 OPTION
+3.3V_NORMAL
USB / DVR Ready
IC2202
AP2191SG-13 +5V_USB
R2220
L2202 NC 8 1 GND 4.7K
MLB-201209-0120P-N2 OPT
OUT_2 7 2 IN_1
120-ohm OUT_1 6 3 IN_2
SIDE_USB_DP

SIDE_USB_DM
C2218 C2220
FLG 5 C2222
4 EN 10uF
100uF R2226 0.1uF
EAN60921001 2.7K 10V
16V
C2206

USB_CTL1
1uF
10V

KJA-UB-4-0004
P2201
R2225 0 /USB_OCD1

1
C2207
0.1uF

USB DOWN STREAM

2
USB_DM1
C2208
C2210
15pF
15pF

3
USB_DP1
SUSP_IND/LOCAL_PWR/NON_REM0

R2202
1M 1%
1/10W 1%

4
D2201 D2203
CDS3C05HDMI1 CDS3C05HDMI1
R2203
R2201

5
5.6V
100K

X2201 5.6V
12K

+3.3V_NORMAL +3.3V_USB 24MHz


L2201
BLM18PG121SN1D
+3.3V_USB
XTAL1/CLKIN
VDD33PLL

VDD18PLL

USBUP_DP

USBUP_DM

VDDA33_3
RBIAS

XTAL2
VSS

C2212
36

35

34

33

32

31

30

29

28

USBDN1_DM VBUS_DET 0.1uF R2209


USB_DM1 1 27 100K
+3.3V_USB THERMAL OPT
R2214
USBDN1_DP RESET_N 0
2 26
USB_DP1

USB_DM2
USBDN2_DM 3
37

25 HS_IND/CFG_SEL1 R2210
100K
C2215
0.1uF
/RST_HUB
USB +3.3V_NORMAL
+3.3V_USB
USBDN2_DP SCL/SMBCLK/CFG_SEL0 OPT
USB_DP2 4 24
IC2201
VDDA33_1 VDD33 R2212 100K OPT IC2203 +5V_USB
5 USB2512A_AEZG 23 AP2191SG-13
R2221
C2201 NC_1 SDA/SMBDATA/NON_REM1 R2211 100K OPT L2203 NC 8
C2202 C2203 C2204 C2205 6 22 1 GND 4.7K
1uF MLB-201209-0120P-N2 OPT
10V 0.1uF 0.1uF 0.1uF 0.1uF NC_2 NC_8 OUT_2 7 2 IN_1
7 21
R2213 100K OPT 120-ohm OUT_1 6 3 IN_2
NC_3 8 20 NC_7 C2221
C2219 C2223
0 R2207 OPT FLG 5 4 EN 10uF
NC_4 NC_6 SCL2_3.3V 100uF R2223 0.1uF
9 19 EAN60921001 2.7K 10V
0 R2208 KJA-UB-4-0004 16V
OPT
10

11

12

13

14

15

16

17

18

SDA2_3.3V P2202
R2204

R2205

USB_CTL2
R2206
100K

100K
100K
VDDA33_2

TEST

PRTPWR1

OCS1_N

VDD18

VDD33CR

PRTPWR2

OCS2_N

NC_5

1
+3.3V_USB R2227 0 /USB_OCD2

USB DOWN STREAM


040:J6

2
USB_DM2
C2211

3
0.1uF

C2213 C2214 USB_DP2


4.7uF
0.1uF
4

D2202 D2204
CDS3C05HDMI1 CDS3C05HDMI1
5

5.6V
C2209

5.6V
1uF
10V
/USB_OCD1

/USB_OCD2
USB_CTL2
USB_CTL1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
40
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
USB

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
+5V_NORMAL
+12V

+3.3V_NORMAL

R4126
10K
EU
EU
C4134 R4163
SCART1_DET
R4129 0.1uF 10K
D4107 EU 16V
1K L4105
5.6V C4116
OPT 0.1uF DTV_ATV_SELECT
IC4101
16V EU
EU EU EU C4119 NLASB3157DFT2G
E R4135 C4118
D4101 ISA1530AC1 0.1uF
470 0.1uF
30V Q4104 16V 16V
EU EU
OPT SC1_CVBS_IN B SELECT B1
6 1
R6166

R4164 EU R4123 C4115 EU ATV_OUT


C4113 EU EU
CN

12 0 C
220pF Q4105
0

R4115 EU 47pF EU R4136


62 50V 50V C 2SC3052 47K EU VCC GND
OPT R4133 C4117 5 2
AV_DET
22 390 B 47uF
COM_GND 16V
A B0
21 4 3
E DTV/MNT_V_OUT
SYNC_IN EU EU
20

75
R4178
1%
EU R4132 R4138
EU 390 0
19 SYNC_OUT
EU
R4112 Rf EU R4137
SYNC_GND2 D4106 75 C4114 Rg
18 R4134 15K
D4102 30V 100uF Gain=1+Rf/Rg 180
SYNC_GND1 16V
17 5.6V OPT Selece = High ==> A = B1
RGB_IO OPT EU
FIX-TER 16 SC1_FB Selece = Low ==> A = B0
R4122
R_OUT 22
15 SC1_R R4131
11 [GN]GND 0
RGB_GND D4103 R4111
10 14 OPT
30V R4104 EU 75
[GN]G R_GND 75 1%
13 OPT
9
[GN]C_DET 12
R4168 0
D2B_OUT EU
1%
Audio Out Amp
8 G_OUT EU
11
[BL]B
D2B_IN
D4104
R4101
R4108
0
SC1_G EU 30V
REC_8
EU_SCART [OPT]
7 10 30V R4128
75 D4112 EU
[RD]R G_GND OPT 1% 0
9 R4146 IC4100
6 EU 1K LM324D
8 ID DTV/MNT_L_OUT
[WH]L_IN SC1_ID EU
OPT EU C4126 EU R4149
5 B_OUT D4111 EU C4123
7 SC1_B R4127 +12V OPT OPT 33K 1 14
[RD]R_IN 30V 15K R4130 10uF 6800pF 1 14
AUDIO_L_IN D4110 3.9K R4141 R4142 16V 50V
4 6 R4102 C4127
30V 68K 68K
75 33pF 2 13
[RD]MONO B_GND
5 OPT 1% 2 13
13 C4122
AUDIO_GND OPT EU R4176
4 33pF EU 10K EU
PPJ-230-01 C4105 R4116 5.6K R4148 3 12
AUDIO_L_OUT 25V SCART1_Lout_N 3 12
JK4101 3 0
SC1_L_IN 5.6K R4147
SCART1_Lout_P
CN AUDIO_R_IN 1uF 4 11
2 EU
R4103 4 11
AUDIO_R_OUT D4109 C4112
1 470K C4120
5.6V 100pF EU
OPT 50V EU 0.1uF 5.6K R4143 5 10
16V SCART1_Rout_P 5 10
EU EU
SCART1_Rout_N R4150
C4104 5.6K R4144 33K 6 9
PSC008-01 25V
R4113 6 9
0
JK4100 SC1_R_IN 002:C6 +12V
EU 1uF C4128 33pF 7 8
D4108 7 8
R4100

EU
5.6V C4111 OPT OPT
470K R4177
OPT 100pF R4139 R4140 R4145 10K EU
50V 68K 68K EU 1K
DTV/MNT_R_OUT
EU
[SCART2 PIN 8] C4121
33pF
OPT
C4124
10uF
EU
C4125
6800pF
+12V L4100 16V
BLM18PG121SN1D R4105 50V
EU_SCART [OPT] 0 EU
041:F4;041:G2
DTV/MNT_L_OUT
EU 1/16W EU
5%
C4100 C4107
R4156 D4105 EU 4700pF
1000pF
10K R4157 R4160 C 5.6V 50V
50V DTV/MNT_L_OUT
EU 0 EU
EU 0 B Q4111 OPT EU
R4152 L4101 EU
2SC3052 BLM18PG121SN1D R4107
4.7K EU EU
R4159 0 Q4106 R4151
EU E DTV/MNT_R_OUT 041:F3;041:G2
EU 12K 2SC3052
EU 1/16W 2K
C 5% 1/16W
EU C4101 C4108 RT1P141C-T112
EU EU
B Q4110 D4100 1000pF EU 4700pF Q4109
SC_RE1
2SC3052 5.6V 50V 50V EU
R4154 DTV/MNT_R_OUT SCART1_MUTE
1K E OPT
3 1
EU C4130
EU EU
R4153 2 0.1uF
C
EU Q4107
EU 2K
B Q4108
SC_RE2
2SC3052 REC_8 For Frequency Response 2SC3052 1/16W
R4155
1K E

EARPHONE BLOCK

+3.3V_NORMAL

EARPHONE AMP L4102


10uH

C4140 C4142
10uF 0.1uF
10V 16V
R4119 L4104
0 BG2012B080TF
HP_LOUT
1/16W C4146
C4139
0.22uF
1uF Close to the IC
16V
10V
OUTL

SGND

VDD

+3.3V_NORMAL
EN

R4172
C4143 100K
C4135 16 15 14 13 2.2uF OPT
1uF 10V R4109 OPT
10V INL- HPVDD 4.7K R4174
1 12
HP_LOUT_N 0
C4136
1uF C
10V INL+ CPP R4175
2 11 1K
HP_LOUT_P Q4117 B
C4137 IC4102 C4144 2SC3052 SIDE_HP_MUTE
1uF TPA6132A2 2.2uF
10V INR+ PGND 10V
3 10 E
HP_ROUT_N
C4138
1uF
10V INR- CPN
4 EAN60724701 9
HP_ROUT_P

5 6 7 8
R4170
4.7K
4.7K
R300

OUTR

G0

G1

HPVSS

R4173 L4103
R4171

BG2012B080TF
R4169

0
OPT
OPT

HP_ROUT
C4141 1/16W C4145
2.2uF 0.22uF
10V
16V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EUROBBTV 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETC SUB BOARD I/F 41

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
BLUETOOTH +3.3V_NORMAL

G
BCM BT MODULE

S
BCM BT MODULE

D
C1108

BCM BT MODULE
Q1801
RTR030P02
R1889
1uF

10
BLUETOOTH FOR BCM BCM BT MODULER1886 BCM BT MODULE
R1887 47K
47K
R1888 C

L1899
BT_ON/OFF 4.7K B

OPT
500
2SC3052
BCM BT MODULE Q1800
E
BCM BT MODULE
11

10
BCM BT MODULE
C1899
22uF
9 10V
R1896
27
BT_DM
8
D1899 BCM BT MODULE
CDS3C05HDMI1
7 5.6V
BCM BT MODULE R1897
27
BT_DP
6 D1898
CDS3C05HDMI1BCM BT MODULE
5.6V
5 BCM BT MODULE
R1898
0
BT_RESET
4
BCM BT MODULE

3
R1899
0
VREG_CTRL
2
BCM BT MODULE

12507WR-10L
P1895
BCM BT MODULE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 43
Bluetooth

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
CI POWER ENABLE CONTROL
+5V_NORMAL Q4501 +5V_CI_Vs
RSR025P03
S D

C4506
G C4508 C4510
0.1uF C4509 47uF

R4514
0.1uF

22K
16V 4.7uF 16V 16V
CI CONTROL BUFFER R4512
16V
AR4515
10K 10K
OPT
CI_A[0]
CI_A[1]
CI_A[2]
R4526
CI_A[3]
D3.3V 2.2K
D3.3V

AR4517
R4503

IC4500 10K C
R4513
10K
MC74LCX541DTR2G
0.1uF

CI_A[4] 10K
C4500

B Q4500
CI_5V_CTL
16V

VCC OE1 CI_A[5] 2SC3052


20 1 /CI_SEL 007:H5
CI_A[6] 007:H7 [GP27]
OE2
19 2
D0 E
EBI_CS
CI_A[7]
016:G13;016:AJ2 /CI_CE1
O0
18 3
D1
007:E7;007:E6;016:AL23
O1 D2
AR4501
016:T13;016:AJ2 /CI_CE2 17 4
NAND_WEb 007:C2;007:E5 10K
O2 D3 CI_A[8]
016:H12 /CI_WE 16 5
EBI_WE 007:E6
O3 D4
CI_A[9]
016:T12 /CI_IOWR 15 6 NAND_REb 007:C3;007:E6
CI_A[10]
O4 D5
016:G13 /CI_OE 14 7
NAND_ALE 007:C2;007:E6 CI_A[11]
O5 D6
13 8
016:T13 /CI_IORD
O6 D7
12 9
AR4504
O7 GND 10K
11 10
CI_A[12]
CI_A[13] D3.3V

0.1uF
C4507
EBI_RW

16V
007:E6 IC4501
74LVC245A
EBI_CS
CI_A[0-13]
016:F16CI_D[0-7] 007:E7;007:E6;016:K26
007:E7;016:C13 DIR
1 20
VCC

NAND_DATA[0-7]
CI_D[0] A0
2 19
OE

NAND_DATA[0]
CI_D[1] A1
3 18
B0

CI_D[2] A2
4 17
B1 NAND_DATA[1]

CI_D[3] A3
5 16
B2 NAND_DATA[2]

CI_D[4] A4
6 15
B3 NAND_DATA[3]

CI_D[5] A5
7 14
B4 NAND_DATA[4]

CI_D[6] A6
8 13
B5 NAND_DATA[5]

CI_D[7] A7
9 12
B6 NAND_DATA[6]
GND
10 11
B7 NAND_DATA[7]

016:AG22 CI_D[0-7] +5V_CI_Vs

AR4511
CI_D[3] 33
CI_D[4]
CI_D[5] R4510
CI_D[6] 100
P4500 /CI_CD1 007:H6;016:AJ3
10067972-000LF C4505
0.1uF
AR4507 1 35
CI_D[7] 33
2 36
CI_D[0]
3 37 AR4502 33 CI_OUTCLK,CI_OUTDATA[0-7],CI_OUTSTART,CI_OUTVALID
CI_D[1] CI_OUTDATA[4]
4 38
CI_D[2] CI_OUTDATA[5]
5 39 DVB-CI PULL-DOWN (Near CI Slot)
CI_OUTDATA[6]
CI_A[0-14] 6 40
47 R4501 CI_OUTDATA[7]
/CI_CE1 7 41
33
AR4518 8 42 /CI_CE2 016:H25;016:AJ2
CI_A[10] 47 R4502 9 43
/CI_OE /CI_VS1 [GP26] 016:AJ3 /CI_INPACK
CI_A[11] 10 44 016:O9
/CI_IORD 016:H24
CI_A[9] 11 45 /CI_IOWR 016:H25
CI_A[8] 12 46 AR4512 33 FE_TS_DATA[0-7]

10K
CI_A[13] 13 47 FE_TS_DATA[0]
CI_A[14] 14 48 FE_TS_DATA[1]
CI_A[12] 47 R4500 15 49 FE_TS_DATA[2]
/CI_WE

R4520
16 50 FE_TS_DATA[3]
/CI_IREQ
0.1uF

[GP39] 17 51
C4501

AR4509 AR4516 33
007:H5;016:AJ3 R4505 R4507 100
16V

33 C4502 18 52 C4503
0.1uF 0 OPT 0.1uF FE_TS_DATA[4]
19 53
FE_TS_DATA[5] External Demod.
20 54
33 FE_TS_DATA[6]
AR4506 21 55
CI_A[7] 22 56 FE_TS_DATA[7]
CI_A[6] 23 57 AR4505 33
007:G6;016:AJ2
CI_A[5] 24 58 CI_MOD_RESET [GP49]
CI_A[4] 25 59 47 R4511
/CI_WAIT 007:E6;016:AJ3
R4506 016:AL9
100
CI_A[3] 26 60 /CI_INPACK DVB-CI PULL-UP (Near CI Slot)
CI_A[2] 27 61 CI_OUTCLK
CI_A[1] 28 62 0 R4508 CI_OUTVALID
CI_A[0] 29 63 CI_OUTSTART +5V_NORMAL
AR4513 30 64
33 31 65 AR4514 33
32 66

10K

22K

10K

10K

10K
CI_OUTDATA[0]

10K

10K

10K

10K
10K
R4504 100
016:AJ3 [GP41] /CI_IOIS16 33 67 CI_OUTDATA[1]
34 68 CI_OUTDATA[2]

R4517

R4519

R4521

R4523

R4524
R4516

R4518

R4522

R4525
CI_OUTDATA[3]

OPT

OPT
OPT
R4515
G1 69 G2
/CI_IOIS16
R4509 AR4520 33
100 /CI_IREQ
/CI_CD2 /CI_VS1
[GP38] 007:H5;016:AJ2 /CI_WAIT
C4504

0.1uF

CI_OUTCLK
/CI_CD1
/CI_CD2
/CI_CE1
AR4519 /CI_CE2
33 CI_MOD_RESET
FE_TS_SYNC
FE_TS_VAL_ERR

FE_TS_DATA_CLK

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EUROBBTV 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. CI 45

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
Mini LVDS

[Right FFC Connector]


(60Pin Mini-LVDS)

0 NON_GIP
0 NON_GIP
0 NON_GIP
0 NON_GIP
0 NON_GIP
0 NON_GIP
[LEFT FFC Connector]
P7401
(60Pin Mini-LVDS)
104060-6017
P7400 MINI_LVDS
104060-6017

R7405
R7406
R7407
R7408
R7410
R7411
MINI_LVDS
1 GND
VGH_M
2 Z_OUT R7412 0 MINI_LVDS Z_OUT (+25V)
1 GND 3 CLK1 CLK1
2 GMA1 4 CLK2 CLK2
GMA1
3 GMA3 5 CLK3 CLK3
GMA3 R7414 0 NON_GIP GSC/GCLK3_I
4 GMA4 6 CLK4 CLK4
GMA4 R7415 0 NON_GIP GOE/GCLK1_I
5 GMA6 7 CLK5 CLK5
GMA6
6 GMA7 8 CLK6 CLK6
GMA7 R7416 0 NON_GIP
7 GMA9 9 VGI_N VGI_N VGL
GMA9 R7417 0 NON_GIP (-5V)
8 GMA10 10 VGI_P VGI_P VGL_I
GMA10
9 GMA12 11 VGH_ODD VDD_ODD
GMA12
10 GMA13 12 VGH_EVEN VDD_EVEN
GMA13 VCC_LCM R7418 0 NON_GIP
11 GMA15 13 VSS R7409 0 GIP
GMA15 R7419 0 NON_GIP
12 GMA16 14 VST VST
GMA16
13 GMA18 R7402 15 GND
GMA18
14 GND 3.3K 16 VCOM_FB VCOMRFB
MINI_LVDS 17 VCOM_IN
15 OPT_N VCOMR
18 GND VDD_LCM
16 H_CONV H_CONV
17 VST_IN 19 VDD To reduce
GSP/GVST_I Audible Noise
18 POL 20 VDD
POL C7408
19 SOE 21 HALF_VDD C7406
SOE 1uF 0.1uF
20 GND VCC_LCM 22 HALF_VDD 50V 50V
23 GND MINI_LVDS
21 LV0+ RXD1-
24 VCC MINI_LVDS
22 LV0- RXD1+
23 LV1+ 25 VCC
RXD0- HVDD
24 LV1- C7400 C7402 26 GND
RXD0+ 0.1uF 0.01uF
25 LV2+ 27 RV0+ RXA1-
RXC4- 16V 50V
26 LV2- MINI_LVDS MINI_LVDS 28 RV0- RXA1+
RXC4+ C7409
27 LVCLK+ 29 RV1+ RXA0-
RXC3- 10uF
28 LVCLK- VDD_LCM 30 RV1- RXA0+ 16V
RXC3+ VCC_LCM
HVDD To reduce 31 RV2+ MINI_LVDS
29 LV3+ RXC2- RXB4-
Audible Noise 32 RV2-
30 LV3- RXC2+ RXB4+
2012 33 RVCLK+
31 LV4+ RXC1- RXB3-
C7401 C7404 34 RVCLK- C7405 C7407
32 LV4- RXC1+ C7403 RXB3+ 0.1uF 0.01uF
10uF 1uF 0.1uF 35 RV3+
33 LV5+ RXC0- 16V 50V 50V RXB2- 16V 50V
MINI_LVDS MINI_LVDS 36 RV3- MINI_LVDS MINI_LVDS
34 LV5- RXC0+ RXB2+
35 GND MINI_LVDS 37 RV4+ RXB1-
36 VCC 38 RV4- RXB1+
37 VCC 39 RV5+ RXB0-
38 GND 40 RV5- RXB0+
39 HALF_VDD 41 GND VCC_LCM
40 HALF_VDD 42 SOE SOE
41 VDD 43 POL POL
42 VDD VGL 44 VST_IN GSP/GVST_I R7413
43 GND (-5V) 45 H_CONV H_CONV 3.3K
VGL_I MINI_LVDS
44 VCOM_IN 46 OPT_N
VCOML
45 VCOM_FB 47 GND
VCOMLFB
46 GND 48 GMA18 GMA18
47 VST 49 GMA16 GMA16
VST R7403 0 NON_GIP
48 VSS R7401 0 GIP 50 GMA15 GMA15
49 VGH_EVEN 51 GMA13 GMA13
VDD_EVEN
50 VGH_ODD 52 GMA12 GMA12
VDD_ODD
51 VGI_P 53 GMA10 GMA10
VGI_P
52 VGI_N 54 GMA9 GMA9
VGI_N
53 CLK6 55 GMA7 GMA7
CLK6
54 CLK5 56 GMA6 GMA6
CLK5
55 CLK4 57 GMA4 GMA4
CLK4 VCC_LCM
56 CLK3 58 GMA3 GMA3
CLK3
57 CLK2 R7400 0 GIP 59 GMA1 GMA1
CLK2 R7404
58 CLK1 3.3K 60 GND
CLK1
59 Z_OUT NON_GIP
Z_OUT
60 GND 61

.
61

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS COMMON 09/10/xx
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
URSA3 120Hz MINI_LVDS
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 74

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
LVDS

[51Pin LVDS Connector]


(For FHD 60/120Hz) [41Pin LVDS Connector]
(For FHD 120Hz)
PANEL_VCC

L7700
500
FHD_120Hz
P7700
TF05-51S
FHD_120Hz
C7700 C7701 C7702
10uF 1000pF 0.1uF P7701
25V 50V 50V
1 OPT TF05-41S
FHD_120Hz
2

3
1
4
2
5
3 RXD4-
6
4 RXD4+
7
5 RXD3-
8
6 RXD3+
9 R7700 0
NON_LGD_22 7
10 R7701 0
NON_LGD_22 8 RXDCK-
11 RXA4- 9 RXDCK+
12 RXA4+ 10
13 RXA3- 11 RXD2-
14 RXA3+ 12 RXD2+
15
13 RXD1-
16 RXACK- 14 RXD1+
17 RXACK+ 15 RXD0-
18
16 RXD0+
19 RXA2- 17
20 RXA2+ 18
21 RXA1- 19 RXC4-
22 RXA1+ 20 RXC4+
23 RXA0- 21 RXC3-
24 RXA0+ 22 RXC3+
25
23
BIT_SEL
26 R7710
10BIT OPEN 24 RXCCK-
10K
27 RXB4- 8BIT
8BIT GND 25 RXCCK+
28 RXB4+ 26
29 RXB3- 27 RXC2-
30 RXB3+ 28 RXC2+
31
29 RXC1-
32 RXBCK- 30 RXC1+
33 RXBCK+ 31 RXC0-
34
32 RXC0+
35 RXB2- 33
36 RXB2+ 34
37 RXB1- 35
38 RXB1+ 36
39 RXB0- R7708-*1 0 37
40 RXB0+ FHD_OPC 38
41 NON_SCAN R7706 0 SCAN_BLK2 39
R7702 0 LD60_SCAN
42 R7707 0 +3.3V_NORMAL
OPC_EN 40
FHD_OPC
43 R7708 0 SCAN_BLK1/OPC_OUT
LD60_SCAN 41
R7711
44 R7709 0 PWM_DIM 3.3K
FHD_OPC 42
45 JEIDA

46 R7703 33 FRC_RESET R7712


240Hz 10K
47 R7704 33 SCL3_3.3V VESA
240Hz
48 R7705 33 SDA3_3.3V
240Hz
49 LVDS_SEL
50 HIGH JEIDA

51 GND(NC) VESA

52

TP7700 OPC_OUT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 35
URSA3 120Hz LVDS

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
FROM LIPS & POWER B/D
L_VS
R_VS
MO_SCLK
+3.5V_ST
RT1P141C-T112 M2_SCLK
15V-->3.6V +12V +3.5V_ST
Q8002 MO_MOSI
20V-->3.5V R8068 +3.5V_ST
M2_MOSI
24V-->3.48V 100K

R8075
PD_+3.5V
PD_+12V
R8004

R8067
1 3

R8063
12V-->3.58V

10K
+24V

OPT
4.7K NORMAL_26~52 IC8007

12K
C

1K

1%
R8000 P8000

1%
RL_ON 10K
B Q8000
2SC3052
2
FW20020-24S
+5V_NORMAL ST_3.5V-->3.5V
NCP803SN293
R8081 POWER_DET

NON_PD_+3.5V
100
E PWR ON 1 24V
L8005 400Hz_VSYNC/42_47_LOCAL DIMMING
MAX 350mA Power_DET VCC 3 2 RESET

R8064-*1
2 MLB-201209-0120P-N2 R8078 +12V +5V_NORMAL 1
24V 24V C8024 0 IC8003

R8064

1/16W

PD_+3.5V
3 4 GND

5.1K
GND GND 68uF AOZ1072AI
+3.5V_ST 5 6 R_VS

27K
35V

5%
L8003 C8018 ESD

1%
GND 7 8 GND
MLB-201209-0120P-N2 0.1uF L8010 C8065
3.5V 3.5V 400Hz_VSYNC L8007
9 10 50V PGND LX_2 3.6uH 0.1uF
R8036 1 8 16V
3.5V 3.5V
C8000 C8004 C8006
11 12 0 L_VS CIC21J501NE
100uF GND 13 14 GND NR8040T3R6N
0.1uF 0.1uF 400Hz_MO_SCLK/42_47_LOCAL DIMMING

R8053
16V GND GND/V-sync R8082 0 V_SYNC VIN LX_1
16V 16V 15 16 2 7
R8077 0

1%
47K
12V 17 18 INV ON 400Hz_VSYNC M2_SCLK C8068
0.1uF R8079
12V 19 20 A.DIM R8028 0
MO_SCLK 16V AGND
3
2A 6
EN POWER_ON/OFF2_2
C8047 C8066 C8049 +3.5V_ST +24V 100K not to RESET at 8kV ESD
+12V 12V P.DIM1 R1

5.6K
R8054
21 22 400Hz_MO_SCLK 22uF 22uF 0.1uF

1%
L8002 C8028 C8030 R8050
GND/P.DIM2 23 24 Err OUT 10K 10V 10V 16V IC8008
MLB-201209-0120P-N2 10uF 10uF
FB COMP
400Hz_MD_MDSI/42_47_LOCAL DIMMING

OPT POWER 24V POWER 20V NCP803SN293


LD650/LD750

SLIM_32~52 +3.3V_NORMAL 25V 25V 4 5 NON_PD_+3.5V


OPT R8080 R8061-*1 R8061
400Hz_MD_MDSI

SCAN_LIPS

NON_CMO
R8015

C8003 C8005 R8026 24K 1% R8074


NON_SCAN_LIPS

C8001 25 12K C8046 24K 1%


R8085

0.1uF 0.1uF R8019 1K 2200pF 14K 1% 100


100uF R8049 100pF VCC RESET
0

100 3 2
0

50V 50V SMAW200-H24S2 C8040


25V 50V
0
C8011
0.1uF
0

R8018 1
P8001
OPT

POWER 24V POWER 20V


16V

100 GND
R8005

R8076

C
R8007

R8055
R8023 R8032 R8062-*1 R8062

1%
CMO

10K
B 10K INV_CTL 4.3K 1% 5.1K 5%
6.8K R2
R8009

SCAN

OPT
E
Q8005
2SC3052
Vout=0.8*(1+R1/R2)
R8039
0

10K
SHARP

R8029 OPT
MO_MOSI

M2_MOSI

CMO 0
C8012

R8014
OPT
1uF
25V

AUO R8030 0
SCAN_BLK2

R8031 0 A_DIM
BCM core 1.2V volt
SCAN_PSU

R8083
0

LGD_IOP A_DIM_LGD
R8084 R8021
<OS MODULE PIN MAP> 0 AUO R8027
0 0 R8044
R8022 PWM_NON_OPC PWM_DIM
SCAN_PSU MAX 3.1A
AUO
+3.3V_NORMAL

R8047
PIN No LGD CMO(09) SHARP R8020 0 R8033 10K

3.9K
OPT
NON_SCAN_PSU C8017 C8021 0 POWER_ON/OFF2_1
0 1uF SCAN_BLK1/OPC_OUT
0.1uF SCAN/FHD_OPC +12V
25V ESD
INV_ON OPT EP ESD
18 INV_ON A-DIM INV_ON OPT R8034 D8000
R8045-*1 MAX 2.3A
0 5.6V
100K D1.2V A1.2V
OPC_OUT
HD_OPC AGND FB R8045
V4:VBR-A 1 14
20 NC Err_out Err_out R8035

THERMAL
V5:NC 0
0 +3.3V_NORMAL NON_ESD R8060

15
SS EN/SYNC
2 13 R8043 R8046 R8048 POWER_ON/OFF2_2
+3.3V_NORMAL
R8037

C8026 L8013 10K D3.3V


22 PWM_DIM PWM_DIM A-DIM PWM_DIM
4.7K
OPT

R8024 470K 20K 910K


0.1uF PGND_1 PGND_2 CIC21J501NE

R8066
0

3.9K
3 12 1%

OPT
AUO/SHARP ERROR_OUT L8009 1% 1%
IC8001 L8011
Err_out INV_ON PWM_DIM 2uH R1 R2 BLM18PG121SN1D
24 GND R8025
SW_1
4 11
SW_2
L8015 L8016
0 C8069 VIN 3.6uH CIC21J501NE
LGD 0.1uF
IN_1 IN_2
C8036

2
5 10

R8069
0.1uF EN 6
+3.5V_ST

1%
27K
NC POK R8040
6 9
IC8005
MLB-201209-0120P-N2

100K FB LX
R8041 C8037 C8041 C8043 C8045 4 7
BS VCC R8042

4.7K
R8070
7 8 22uF 22uF 22uF 0.1uF C8057 C8059 C8063 C8064

1%
0 16V C8051 C8052 C8067
10 10V 10V 10V COMP AOZ1024DI 22uF 22uF 0.1uF 0.1uF
MP2208DL-LF-Z 0.1uF 22uF 5 10uF 16V 16V
L8006

10V 10V
50V 25V
R8058
10V

1
20K
+12V

AGND

PGND
L8000
PANEL_POWER C8054
2200pF

R8071
CIC21J501NE 50V

1%
10K
C8029 C8032 C8033 C8035
C8027 1uF
22uF 0.1uF 22uF
0.1uF 10V
C8009 C8010 16V
C8008
0.1uF 10uF
0.01uF
25V 50V 25V
OPT
Vout=0.8*(1+R1/R2)
Q8004
AO3407A
S

D
R8010
10K

C8013 PANEL_VCC
4.7uF
G
50V OPT
R8011

R8003 C8015
1.8K

22K 1uF
25V

OPT C
R8002
10K B Q8003
2SC3052
C C8022
R8001
47K B Q8001
R8008
22K
E 0.1uF
50V BCM DDR 1.8V Max 1100 mA
PANEL_CTL

1:AK10
E
2SC3052

+3.5V_ST
+3.3V_NORMAL
A2.5V A2.5V
D1.8V
Vout=0.9*(1+R1/R2) IC8004
L8012 SC4215ISTRT
Replaced Part 3.6uH VOUT : 2.533V
CIC21J501NE

L8014
500

L8017
500
IC8002 NR8040T3R6N 1 8
L8008

MP2108DQ NC_1 GND R8073


0.01uF

R8059 18K R2
C8034

10K 2 7 1%
25V

10K
BST RUN R8052 EN ADJ R8072
1 10 POWER_ON/OFF1 39K R1

+5V_USB VIN
2 9
VREF
C8053 VIN
3 6
VO
1%

+12V
+5V_USB
LX
3A COMP
C8042
10uF
16V
C8055
0.1uF OPT
NC_2
4 5
NC_3
C8058 C8061 C8062

MAX 1500mA 0.01uF OPT C8056 10uF


Placed on SMD-TOP 3 8 50V 0.1uF
10uF 0.1uF
IC8000 25V
100pF R1 16V 16V
L8001

MP8706EN-C247-LF-Z
500

PGND FB C8044 R8057 Placed on SMD-TOP


4 7
C8031
C IN 22uF C8039 R2 10K
IN GND 10V 1%
1 8 SGND SS 3300pF
OPT 5 6 R8056
R8016

C8014 50V C8048 C8050


C8016 10K
1%
33K

SW_1 VCC 1uF 100pF OPT 1/10W 22uF 0.1uF


C8038 R8051
2 7 50V 50V C8019 1% 10V
0.01uF 6.8K
C8002 100pF C8020 C8023 C8025
R1 25V
10uF
25V
SW_2
3
3A 6
FB
R8012
10K 50V
22uF
10V
0.1uF
16V
0.1uF
16V
Vout=0.8*(1+R1/R2)
C8007
0.1uF
R8017

BST EN/SYNC POWER_ON/OFF2_1


6.2K
1%

4 5
R8006 R8013
22 10K
R2

L8004
3.6uH +5V_USB

NR8040T3R6N

Vout=(1+R1/R2)*0.8

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (EUROBBTV)
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 15

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
FLMD0
GND

+3.5V_ST

10K
47K
0

R8143
50V 50V MICOM_DOWNLOAD

OPT
10Mhz Crystal Ready
15pF 15pF R8146
C8101 C8102

R8140
10MHz
X8100

27pF
22pF
0

WIRELESS_DETECT

WIRELESS_PWR_EN
R8138

C8106
C8105
R8139

MICOM_RESET
10K

+3.5V_ST
OPT X8101

32.768KHz
R8175
4.7M

47K
22
+3.5V_ST

R8180

R8184
P122/X2/EXCLK/OCD0B
for Debugger GND SW8100
JTP-1127WEM
2 1

22
+3.5V_ST

P120/INTP0/EXLVI
P8100
12505WS-12A00 C8103

P124/XT2/EXCLKS
0.1uF C8108
4 3

0.1uF
0.1uF
1

R8178
P121/X1/OCD0A
+3.5V_ST

2
MICOM_RESET
R8113 22

C8104
3
NEC_ISP_Tx
4

R8115 22

P123/XT1
5 NEC_ISP_Rx
6
R8186 20K

7 R8116 22 1/16W

FLMD0

RESET
OCD1A 1%

REGC
8

R8185

1/16W
VDD
VSS

P40
P41
R8118 22 EDID_WP

20K
9
OCD1B

1%
C
10
B Q8100
11 R8119 22 2SC3052
FLMD0
12
E

48
47
46
45
44
43
42
41
40
39
38
37
13
R8104 10K

R8127 22
P60/SCL0 1 36 P140/PCL/INTP6 R8187 22
SCL1_3.3V RL_ON

R8128 22
P61/SDA0 2 35 P00/TI000 R8188 22
SDA1_3.3V SCART1_MUTE
+3.5V_ST +3.5V_ST
NEC_EEPROM_SCL
P62/EXSCL0 3 34 P01/TI010/TO00 R8189 10K
R8108 10K
NEC_ISP_Tx
P63 4 33 P130 R8192 22
R8105 10K
NEC_ISP_Rx
OPT
R8126
NEC_EEPROM_SDA
P33/TI51/TO51/INTP4 IC8101 P20/ANI0
WIRELESS_SW_CTRL

10K HDMI_CEC
R8129 22
5 32 R8194 22 FLASH_WP
R8106 10K
OCD1A R8130 22 P75 6 UPD78F0513AGA-GAM-AX 31 ANI1/P21 R8195 22
POWER_ON/OFF2_1 MODEL1_OPT_3

R8107 10K R8131 22 P74 7 30 ANI2/P22 R8196 22


OCD1B AMP_MUTE MODEL1_OPT_2
R8132 22 P73/KR3 NEC_MICOM ANI3/P23
MODEL1_OPT_0 8 29 R8190 22
POWER_ON/OFF1
R8133 22 P72/KR2 9 28 ANI4/P24 R8193 22
SOC_RESET MICOM_DOWNLOAD
R8134 22 P71/KR1 10 27 ANI5/P25 R8191 22
INV_CTL SIDE_HP_MUTE
EEPROM for Micom R8135 22 P70/KR0 11 26 ANI6/P26
+3.5V_ST MODEL1_OPT_1 KEY2
R8136 22 P32/INTP3/OCD1B 12 25 ANI7/P27
OCD1B KEY1
IC8100 NON_M-REMOTE

13
14
15
16
17
18
19
20
21
22
23
24
M24C16-WMN6T

1 8
1 8

P31/INTP2/OCD1A
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RXD6
P13/TXD6
P12/SO10
P11/SL10/RXD0
P10/SCK10/TXD0
AVREF
AVSS
R8122 4.7K

R8125 4.7K
R8100
47K

C8100

0.1uF

2 7
2 7
+3.5V_ST
3 6 R8117
3 6 NEC_EEPROM_SCL
22
4 5 R8114
4 5 NEC_EEPROM_SDA
22

C8107 1uF
FOR ATSC Assy
SCART1_MUTE TP8100

22

22
+3.5V_ST

22 NON_M-REMOTE

R8179
R8177
R8181 10K
+3.5V_ST OPT
MICOM MODEL OPTION
R8182 10K
OPT
10K

10K

10K
10K

TACT_KEY
TOUCH_KEY

LOGO_BUZZ

22

22

22
OLED/3D

MODEL OPTION
PDP/3D
R8109

R8111

R8123
R8120

R8142

R8144

R8145

R8176
PIN NAME PIN NO. HIGH LOW

R8102 100 MODEL_OPT_0


AMP_RESET_N MODEL1_OPT_0 8 OLED/3D LCD/PDP R8183 10K
R8103 100 OPT
PANEL_CTL MODEL1_OPT_1
R8101 100 MODEL_OPT_1 11 LOGO_BUZZ PWM_LED
OPC_EN MODEL1_OPT_2
OPC
MODEL1_OPT_3 MODEL_OPT_2 30 TOUCH_KEY TACT_KEY
LED_R/BUZZ
LED_B/LG_LOGO
10K

10K

10K

10K

POWER_DET

IR

NEC_ISP_Rx

NEC_ISP_Tx

POWER_ON/OFF2_2

NEC_RXD

NEC_TXD
OCD1A
LCD/OLED

TACT_KEY

PWM_LED

LCD/PDP

MODEL_OPT_3 31 PDP/3D LCD/OLED


R8110

R8112

R8121

R8124

LCD PDP OLED 3D

MODEL_OPT_0 0 0 1 1

MODEL_OPT_3 0 1 0 1

LOW LOW_SMALL TBD HIGH

MODEL_OPT_1 0 0 1 1

MODEL_OPT_2 0 1 0 1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS GP2_Saturn7M Ver. 1.4
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 5

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
+3.5V_ST

EYEQ
R8225
IR & KEY NEC_EEPROM_SCL
100 D8204
CDS3C05HDMI1 P8200
R8213 5.6V 12507WR-12L
R8211
10K 10K C8213
1% 1% 1000pF
50V
L8200 OPT
R8209 BLM18PG121SN1D 1
100 EYEQ
KEY1 R8226
L8201 100
R8210 D8201 2
100 BLM18PG121SN1D NEC_EEPROM_SDA
5.6V D8205
KEY2 C8214
AMOTECH CDS3C05HDMI1
C8206 C8207 1000pF
50V 5.6V 3
0.1uF 0.1uF
D8200 OPT
5.6V
AMOTECH 4
+3.5V_ST

+3.5V_ST 5
L8202
BLM18PG121SN1D
+3.5V_ST 6
R8202
47K
R8200
22 +3.5V_ST R8227 1.5K
IR R8204 C8208 C8209 7
0.1uF 1000pF LED_B/LG_LOGO
47K 16V 50V TACT_KEY 10K
R8203
Q8200 C 10K R8287
B R8206 8
2SC3052 LD650/LD750
E 3.3K
R8205 OPT R8224
C 47K 100
B 9
Q8201 E D8206
2SC3052 C8212 5.6V
100pF AMOTECH
+3.5V_ST +3.3V_NORMAL 50V 10
COMMERCIAL L8203
BLM18PG121SN1D
R8201 +3.5V_ST 11
0 R8214
47K
OPT R8207 COMMERCIAL_EU R8276
22 LED_R/BUZZ 12
IR_OUT R8218 C8211
C8210 1.5K
COMMERCIAL 47K 1000pF OPT
0.1uF
R8216 COMMERCIAL 16V 50V R8280 13
Q8202 C 10K 10K
2SC3052 B
COMMERCIAL_EU E R8220
COMMERCIAL_EU C 47K

Q8204 E
B
COMMERCIAL
ETHERNET CONNECT A2.5V
2SC3052
COMMERCIAL
L8204
JK8200
CIC21J501NE
R8212 XRJV-01V-D12-180
0
COMMERCIAL_US R8283
0
Zener Diode is EPHY_TDP
OPT
1

C8218
10pF 2
close to wafer

D8207
50V

5.6V
+3.5V_ST R8284
WIRELESS 0
3
EPHY_TDN OPT
C8220
+3.5V_ST R8285 10pF
R8215 0 50V
EPHY_RDP 4
47K
R8208 WIRELESS

D8212
OPT C8216
22

5.6V
D8208
R8219 C8221 1000pF

5.6V
IR_PASS 10pF 5
WIRELESS 47K 50V 50V
R8217 WIRELESS
Q8203 C 10K R8286
B 0
2SC3052 6
E WIRELESS EPHY_RDN
WIRELESS R8221

D8209
C 47K

5.6V
OPT
B C8222 C8217 7
Q8205 E WIRELESS 10pF
2SC3052 50V 1000pF
WIRELESS
8
D3.3V
R8281 510
D1

D2
EPHY_LINK

D8210

5.6V
R8282 510
D3

EPHY_ACTIVITY D4

D8211

5.6V
9

RS232C
Trace impedance : 100 ohm differenctial impedance to GND plane
10 5 mils trace width with 7 mils air gap on P/N pair.
+3.5V_ST
5
Adjacent TX/RX differential pairs should be separated by more than
15 mils to each other
9
OPT
IR_OUT 4
R8279
0
R8277 8
100
C8200 0.33uF 3

IC8200 7
C8205 R8278
MAX3232CDR 0.1uF 100
2

D8202 D8203 6
C1+ VCC
1 16 CDS3C30GTH CDS3C30GTH
30V 30V 1
C8201
0.1uF V+ GND
2 15
+3.5V_ST
C8202 SPG09-DB-009
0.1uF C1- DOUT1 P8201
3 14

R8222 R8223
C2+ RIN1 4.7K 4.7K
4 13 OPT OPT
C8203
0.1uF C2- ROUT1 R8273 0
5 12 BCM_RXD1

R8274 0
V- DIN1 NEC_RXD
6 11
C8204
0.1uF DOUT2 DIN2
7 10 R8272 0
BCM_TXD1
RIN2 ROUT2
8 9 R8275 0
NEC_TXD
EAN41348201

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
* HDMI CEC
E E +3.3V_HDMI
+3.3V_NORMAL
JACK_GND
D8302 KRC104S D8308 KRC104S HDMI_HPD_4
HDMI_HPD_1 L8300
5.5V Q8305 B 5.5V GND Q8307 B
GND E ESD E R8321 BLM18PG121SN1D
OPT R8311 GND 5V_HPD4
SHIELD C 4.7K 5V_HPD1 C 4.7K
KRC104S KRC104S
GND GND Q8306 B
20 Q8302 B 20 5V_HDMI_4 C8324
5V_HDMI_1
R8302 HP_DET R8316 C +3.5V_ST 0.1uF
HP_DET C
19 19
5V 1K 5V 1K

18 18
GND
GND D8311
D8305

CDS3C05HDMI1
R8317 JP8306

CDS3C05HDMI1
17 R8307 17 5.5V
DDC_DATA 5.5V DDC_DATA 0
0 OPT DDC_SDA_4 ESD R8326
DDC_SDA_1

G
16 22K

R8349
16 JP8304 DDC_CLK
DDC_CLK

27K
DDC_SCL_4

ESD
D8313
DDC_SCL_1 15

D8314
15 NC R8318

5.6V
R8308

5.6V
NC JP8305

ESD
GND 0 JP8307 GND

Q8308
0 14

D
B
S

BSS83
14 CE_REMOTE D8312
CE_REMOTE
CEC_REMOTE CEC_REMOTE
13 13 MMBD301LT1G
CK- CK-
CK-_HDMI1 CK-_HDMI4
12 12
CK_GND
CK_GND

EAG42463001
CEC_REMOTE HDMI_CEC
EAG59023302

11 11 GND
CK+ CK+
JK830210 JK830310 CK+_HDMI4
CK+_HDMI1
D0- D0-
9 9 D0-_HDMI4
D0-_HDMI1
D0_GND D0_GND
8 8
D0+ D0+
7 7 D0+_HDMI4
D0+_HDMI1
D1- D1-
6 6 D1-_HDMI4
D1-_HDMI1
D1_GND D1_GND
5 5
D1+ D1+
4 4 D1+_HDMI4
D1+_HDMI1
D2- D2-
3 3 D2-_HDMI4 +3.3V_HDMI
D2-_HDMI1
D2_GND D2_GND
2 2
D2+ D2+
1 1 D2+_HDMI4
D2+_HDMI1

KJA-ET-0-0032 GND
YKF45-7058V

0.1uF

C8308

0.1uF

C8310
0.1uF

C8305
0.1uF

C8307

0.1uF

C8309

0.1uF

C8311
GND
UI_HW_PORT1 SIDE_HDMI_PORT4
HDMI4
C8319

HDMI_HPD_4
D2-_HDMI4

D1-_HDMI4
D2+_HDMI4

D1+_HDMI4

CK+_HDMI4
HDMI_CLK-
HDMI_CLK+

HDMI_RX0-
HDMI_RX0+

HDMI_RX1-
HDMI_RX1+

D0-_HDMI4

CK-_HDMI4

DDC_SCL_4
DDC_SDA_4
D0+_HDMI4
HDMI_RX2-
HDMI_RX2+
HDMI_SDA
HDMI_SCL
+5V_NORMAL +5V_NORMAL
E 0.1uF
5V_HDMI_1 5V_HDMI_2
HDMI_3 C8320
D8300 KRC104S HDMI_HPD_2
5.5V Q8303 B
GND E 0.1uF
A2

A1

A2

A1
OPT R8309 HDMI_3 5V_HDMI_4
SHIELD HDMI_3 C 4.7K 5V_HPD2 5V_HPD2 HDMI_3 +5V_NORMAL C8321
KRC104S 5V_HPD1 D8309
D8306
20 HDMI_3 GND Q8300 B
5V_HDMI_2 0.1uF
C

C
HP_DET R8300 C R8325 C8322
1.8K C8312
19
5V 1K 0.1uF

33
33
0.1uF

33
33

33
33
R8312 R8314 R8319 R8322 16V
18
GND R8324

R8329
R8330
HDMI_3 47K 47K 47K 47K

R8331
R8332

R8333
R8334
D8303 1.8K
17 R8303 JP8300 5.5V HDMI_3 HDMI_3
DDC_DATA 0
DDC_SDA_2 OPT
16 DDC_SDA_1 DDC_SDA_2

R8339
DDC_CLK

OPT
DDC_SCL_2 DDC_SCL_1 DDC_SCL_2

0
15
NC R8304 JP8301 GND +1.8V_HDMI
0
14 HDMI_3
CE_REMOTE
CEC_REMOTE
13
CK-
CK-_HDMI2 C8318 C8323
12 C8316
CK_GND 0.1uF 0.1uF
0.1uF
16V

VDDDC[1V8]_3
EAG59023302

16V 16V

VDDH[3V3]_8

VDDH[3V3]_7

RXD_DDC_CLK
RXD_DDC_DAT
11
CK+ +5V_NORMAL
JK830010 +5V_NORMAL

VDDO[1V8]
CK+_HDMI2 5V_HDMI_3 HDMI3
5V_HDMI_4

OUT_D0-
OUT_D0+

OUT_D1-
OUT_D1+

OUT_D2-
OUT_D2+

RXD_D2+
RXD_D2-

RXD_D1+
RXD_D1-

RXD_D0+
RXD_D0-

RXD_HPD
D0-

VSS_12

VSS_11

VSS_10

RXD_C+
RXD_C-

RXD_5V
9 D0-_HDMI2
D0_GND Place close 5V_HDMI_3
A2

A1

A2

A1

8 to TDA9996
5V_HPD3 5V_HPD4
D0+ HDMI1
7 D0+_HDMI2 D8307 D8310

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
D1-
C

6 VSS_1 1 75 VDDH[1V8]_2
D1-_HDMI2 C8317
5V_HDMI_1 OUT_C+ R12K R8344
D1_GND 2 74 0.1uF
5
OUT_C- 3 73 VSS_9 12K 16V
D1+ R8313 R8315 R8320 R8323
4 D1+_HDMI2 VDDO[3V3] 4 72 RXC_D2+
47K 47K 47K 47K D2+_HDMI3
D2- OUT_DDC_CLK 5 71 RXC_D2-
3 C8302 D2-_HDMI3
D2-_HDMI2 DDC_SDA_3 DDC_SDA_4 OUT_DDC_DAT VDDH[3V3]_6
0.1uF 6 70
D2_GND
2 16V VSS_2 7 69 RXC_D1+
DDC_SCL_4 D1+_HDMI3
D2+ DDC_SCL_3 OPT VDDDC[1V8]_1 RXC_D1-
1 D2+_HDMI2 R8328 RXA_HPD
8
9
IC8300 68
67 VSS_8
D1-_HDMI3
HDMI_HPD_1
0 RXA_5V 10 66 RXC_D0+
RXA_DDC_DAT 11 TDA19997 65 RXC_D0-
D0+_HDMI3
D0-_HDMI3
DDC_SDA_1 RXA_DDC_CLK VDDH[3V3]_5
12 64
HDMI_3 DDC_SCL_1 RXA_C- 13 63 RXC_C+
YKF45-7058V
UI_HW_PORT3 EDID Pull-up CK-_HDMI1 RXA_C+ 14 62 RXC_C-
CK+_HDMI3
CK-_HDMI3
GND CK+_HDMI1 VDDH[3V3]_1 15 61 RXC_DDC_CLK
DDC_SCL_3
RXA_D0- 16 60 RXC_DDC_DAT
D0-_HDMI1 DDC_SDA_3
RXA_D0+ 17 59 RXC_5V
D0+_HDMI1 VSS_3 RXC_HPD
18 58 HDMI_HPD_3
RXA_D1- 19 57 CEC R8345
D1-_HDMI1 0 Ready for TDA19997
RXA_D1+ 20 56 VSS_7
OPT
D1+_HDMI1 VDDH[3V3]_2 VDDS[3V3]
E 21 55
+3.3V_HDMI
RXA_D2- 22 54 CDEC_STBY
D8301 KRC104S HDMI_HPD_3 D2-_HDMI1 OPT
5.5V RXA_D2+ 23 53 INT_N/MUTE R8346 0 R8347
GND Q8304 B D2+_HDMI1
OPT E R8310 VDDH[1V8]_1 RXE_DDC_DAT 4.7K
24 52 OPT
SHIELD C 4.7K 5V_HPD3
KRC104S AUX_5V 25 51 RXE_DDC_CLK OPT
GND

C8315
0.1uF
20 Q8301 B 4.7K

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
5V_HDMI_3 R8348
HP_DET R8301 C

VSS_4
TEST1
RXB_HPD
RXB_5V
RXB_DDC_DAT
RXB_DDC_CLK
RXB_C-
RXB_C+
VDDH[3V3]_3
RXB_D0-
RXB_D0+
VSS_5
RXB_D1-
RXB_D1+
VDDH[3V3]_4
RXB_D2-
RXB_D2+
VSS_6
CDEC_DDC
VDDDC[1V8]_2
VDDDC[1V8]_4
R8336 0 TEST2
PD
I2C_SDA
I2C_SCL
19
5V 1K
+5V_NORMAL
18
GND
JP8302 D8304 R8327
17 R8305
DDC_DATA 0 5.5V
DDC_SDA_3 OPT C8300 0 0 OPT
16
DDC_CLK 0.1uF R8343
15 DDC_SCL_3
NC R8306
JP8303 GND
0 C8313
14
CE_REMOTE 0.1uF C8314
CEC_REMOTE 16V 0.1uF
13
CK- 16V
CK-_HDMI3

R8335
12 5V_HDMI_2

OPT
CK_GND +1.8V_HDMI
EAG59023302

0
11
CK+
JK830110 CK+_HDMI3
D0- C8306

R8338 22
9

R8340
D0-_HDMI3 C8301 C8303 C8304 0.1uF
D0_GND 0.1uF 0.1uF 0.1uF 16V

22
8 16V
16V 16V
D0+
7 D0+_HDMI3 R8337
D1- 0
6 D1-_HDMI3

DDC_SCL_2
DDC_SDA_2

CK-_HDMI2
CK+_HDMI2

D0-_HDMI2
D0+_HDMI2

D1+_HDMI2

D2-_HDMI2
D2+_HDMI2
D1-_HDMI2
HDMI_HPD_2

D1_GND
5
D1+
4 D1+_HDMI3
D2-
3 D2-_HDMI3
D2_GND
2

SDA2_3.3V
SCL2_3.3V
D2+ HDMI2
1 D2+_HDMI3

YKF45-7058V

GND
UI_HW_PORT2

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (EUROBBTV) 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR LEE GI YOUNG
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 8

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
RGB PC
IC8401-*1
R1EX24002ASAS0A
IC8400 +5V_NORMAL
74F08D A0 VCC
+5V_NORMAL
1 8

A1 WP
D0A VCC 2 7 D8409
1 14 A2
ENKMC2838-T112
SCL A1
3 6
DEV C
D0B D3B C8401 VSS SDA
2 13 0.1uF
4 5
A2
R8401
22 Q0 D3A RGB_EDID_RENESAS
RGB_HSYNC 3 12

0.1uF
IC8401

C8404

R8414
D1A Q3

R8413
2.7K

2.7K
RGB_VSYNC M24C02-RMN6T

16V
4 11
R8402 R8420
22 E0 1 8 VCC 10K
D1B D2B R8422
5 10 E1 2
7 WC 100
EDID_WP
E2 3 SCL R8416
Q1 D2A 6 RGB_DDC_SCL
6 9 22
VSS 4 SDA R8415
5 RGB_DDC_SDA

18pF 50V

18pF 50V
22
GND Q2 0IMMR00014A
7 8

R8417

R8421
ADUC30S03010L_AMODIODE

ADUC30S03010L_AMODIODE

C8405

C8406
RGB_EDID_ST
R8406

0
22
OPT
D8410
CDS3C05HDMI1
5.6V
R8405 OPT OPT +3.3V_NORMAL

C8403
OPT

C8402

22pF
22pF

50V
50V
BCM Reference 22 D8408
CDS3C05HDMI1

D8401

D8403
30V

30V
5.6V R8424
10K
1K
L8408 60-ohm R8425
DSUB_B DSUB_DET
RGB_BEAD
OPT
L8409 60-ohm 0 OPT C8409
DSUB_G D8411
R8423 100pF
RGB_BEAD 5.6V
50V
ADMC5M03200L_AMODIODE
L8410 60-ohm
DSUB_R

GREEN_GND

DDC_CLOCK
RGB_BEAD

DDC_DATA

BLUE_GND

SYNC_GND
RED_GND

DDC_GND
H_SYNC

V_SYNC
GND_2

GREEN

GND_1
BLUE
RED

NC
BCM Reference
R8403
75
R8404
75
R8407
75 D8402 D8404 D8405
30V 30V 30V
RGB IN
L8408-*1 0

SHILED
11

12

13

14

15
RGB_0OHM

16
10
6

9
L8409-*1 0
RGB_0OHM

5
L8410-*1 0 SPG09-DB-010
P8400

+3.3V_NORMAL RGB_0OHM
JK8400
JP8401 JST1223-001
GND RGB AUDIO IN
1

Fiber Optic

JP8402 JK8401
R8400
VCC PEJ027-01
2

1K
JP8400 3 E_SPRING
SPDIF_OUT
VINPUT
3

6A T_TERMINAL1
4

D8400 C8400
30V 0.1uF C8407
OPT 16V FIX_POLE 7A B_TERMINAL1
PC_R_IN
D8406 1uF R8418
4 R_SPRING 0
AMOTECH R8411 25V
5.6V 470K
5 T_SPRING

C8408
7B B_TERMINAL2
PC_L_IN
1uF R8419
T_TERMINAL2 D8407 R8412 0
6B AMOTECH 25V
470K
5.6V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EUROBBTV 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. ETC SUB BOARD I/F 9

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
(New Item Developmen H:9.2mm)

SIDE_AV SIDE_AV
R8503
SIDE_AV_CVBS
+3.3V_NORMAL 0 C8503
D8503
47pF
5A [YL]E-LUG 5.5V SIDE_AV 50V SIDE_AV
SIDE_AV R8502
4A 2.7K R8504
[YL]O-SPRING
SIDE_AV_DET
1K
3A [YL]CONTACT C8500 SIDE_AV
D8500
100pF
5.6V
4B 50V
[WH]O-SPRING
SIDE_AV SIDE_AV
R8505
3C SIDE_AV
[RD]CONTACT SIDE_AV_L_IN
SIDE_AV 0
R8500 C8504
4C D8501 25V 1uF
[RD]O-SPRING 470K 100pF
5.6V C8501
SIDE_AV SIDE_AV
5C SIDE_AV
[RD]E-LUG
SIDE_AV
PPJ235-01 R8506
JK8500 SIDE_AV_R_IN
SIDE_AV 0
SIDE_AV D8502 R8501 C8505
25V 1uF
5.6V 470K C8502 100pF
SIDE_AV SIDE_AV
SIDE_AV

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SIDE_AV

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
WIRELESS READY MODEL

JK8700
KJA-PH-3-0168

Wireless power VCC[24V/20V/17V]_1


1
VCC[24V/20V/17V]_2
2
VCC[24V/20V/17V]_3
3
VCC[24V/20V/17V]_4
4
VCC[24V/20V/17V]_5
+24V 5
VCC[24V/20V/17V]_6
6
+3.3V_NORMAL DETECT
7
C8700 R8704
22K C8701 INTERRUPT
0.1uF 8
2.2uF TP8700
50V GND_1
S R8714
9
10K
G RESET
10
R8705 TP8701
Q8701 R8713 1K GND_2
2.2K D WIRELESS_DETECT 11
AO3407A L8700
I2C_SCL
R8702 C WIRELESS_SCL 12
10K MLB-201209-0120P-N2
WIRELESS_PWR_EN I2C_SDA
B WIRELESS_SDA 13
Q8700 GND_3
C8702 14
E 0.01uF C8704 C8705
50V 10uF 10uF UART_RX
WIRELESS_RX 15
35V 35V
UART_TX
WIRELESS_TX 16
GND_4
17
IR
IR_PASS 18
GND_5
19
GND_6
20

21

SHIELD

+3.5V_ST

NON_WIRELESS WIRELESS
R8703 0
R8707
0
IC8700
WIRELESS MC14053BDR2G
R8700
WIRELESS_DL_RX
0
Y1 VDD
WIRELESS_TX 1 16
WIRELESS
C8703 RS232C & Wireless
Y0 Y BCM_TXD1 0.1uF
BCM_TX 2 15

Z1 X BCM_RXD1
3 14
R8708 0
WIRELESS_DL_TX WIRELESS_SW_CTRL SELECT PIN STATUS
Z X1 WIRELESS
4 13
WIRELESS_RX
R8706 HIGH X1/Y1/Z1 WIRELESS Dongle connect --> WIRELESS RS232
0 NON_WIRELESS +3.5V_ST
Z0 X0
5 12 BCM_RX
LOW X0/Y0/Z0 WIRELESS Dongle Dis_con --> S7 RS232
4.7K

INH A
OPT

R8711

6 11

R8701 0 VEE B
7 10
WIRELESS
47K

VSS C
OPT

WIRELESS_SW_CTRL
R8712

8 9

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
12
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
WIRELESS

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
+24V +24V_AMP

L8803
MLB-201209-0120P-N2

C8827
0.1uF
50V

+1.8V_AMP

+3.3V_NORMAL
IC8800 CCFL = 20V
AP1117E18G-13
R8800

IN 3 Vd=1.4V 1 ADJ/GND Edge_LED 32~47 Inch = 20V


120 mA
1

2
C8800 OUT
C8802 C8803 55 Inch & IOP Module = 24V
0.1uF 10uF 0.1uF
16V 10V 16V

+24V_AMP

SPK_L+
D8800
1N4148W R8812 R8819 L8805
EMI 100V 12 12 AD-9060 R8820
R8809 C8841
OPT 2S 2F 0.1uF 4.7K
3.3 C8835 50V
390pF
EMI
C8832
50V C8839
0.47uF
SPEAKER_L
C8826 1S 1F 50V
C8820 C8824 10uF 0.01uF
0.1uF 0.1uF 50V C8836 C8842
50V 50V 35V 390pF 0.1uF R8821
+3.3V_NORMAL D8801 50V 15uH 50V
1N4148W R8813 R8817 4.7K
BLM18PG121SN1D

100V 12 12
C8819 OPT
22000pF SPK_L-
50V C8823
L8802 22000pF
50V
PGND1A_2
PGND1A_1

PVDD1A_2
PVDD1A_1
PVDD1B_2
PVDD1B_1

PGND1B_2
PGND1B_1
C8825
OUT1A_2
OUT1A_1

OUT1B_2
OUT1B_1
1uF
EP_PAD

25V

BST1B
VDR1B
AMP_RESET_N
C8808
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1000pF
50V
BST1A 1 42 NC C8828 SPK_R+
AUD_MASTER_CLK C8816 25V1uF
VDR1A 2 THERMAL 41 VDR2A C8830
1uF 25V /RESET 57 BST2A 22000pF
3 40 D8802 R8818
+1.8V_AMP 50V R8814
C8811 AD 4 39 PGND2A_2 1N4148W 12 12 L8804
+1.8V_AMP 0.1uF DGND_1 PGND2A_1 100V AD-9060 C8843 R8822
5 38 OPT 2S 2F
BLM18PG121SN1D

GND_IO 37 OUT2A_2 C8837 0.1uF 4.7K


6 IC8801
CLK_I 7 36 OUT2A_1
390pF
50V
C8840
0.47uF
50V SPEAKER_R
BLM18PG121SN1D

L8801 50V
C8810 VDD_IO 8 35 PVDD2A_2 1S 1F
C8806 1000pF EAN60969601 C8838
L8800 50V DGND_PLL 9 34 PVDD2A_1 390pF
100pF 50V
R8806 AGND_PLL 33 PVDD2B_2 D8803 15uH C8844 R8823
50V 10
3.3K LF PVDD2B_1 1N4148W R8815 R8816 0.1uF 4.7K
11 NTP-7000 32 100V 12 12 50V
AVDD_PLL 12 31 OUT2B_2 OPT SPK_R-
DVDD_PLL 13 30 OUT2B_1 +24V_AMP
GND 14 29 PGND2B_2
OPT
C8801 C8804 OPT
10uF 0.1uF C8805 C8807
15
16
17
18
19
20
21
22
23
24
25
26
27
28

10V 16V 10uF 0.1uF


10V 16V
DGND_2
DVDD
SDATA
WCK
BCK
SDA
SCL
MONITOR0
MONITOR1
MONITOR2
/FAULT
VDR2B
BST2B
PGND2B_1

+1.8V_AMP C8834
C8831 C8833 10uF
0.1uF 0.1uF 35V
50V 50V
OPT
C8815 C8822
10uF C8818 1uF
0.1uF 25V C8829
10V
16V
22000pF
50V
R8801 100
AUD_LRCH
R8802 100 R8807
AUD_LRCK 0
R8803 100 POWER_DET
AUD_SCK
R8804 100 C8821 OPT
SDA1_3.3V 1000pF
R8805 100 50V
SCL1_3.3V +3.5V_ST
C8809 C8812 C8813 C8814 C8817
33pF 33pF 47pF 47pF 47pF
50V 50V 50V 50V 50V
R8810 WAFER-ANGLE
EMI EMI EMI R8808 100 10K
C R8824
0
B R8811 SPK_L+
Q8800 AMP_MUTE 4
2SC3052 10K R8825
0
E SPK_L-
3
R8826
0
SPK_R+
2
R8827
0
SPK_R-
1

P8800

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (EUROBBTV) 2009.06.18
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR KIM JONG HYUN
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. NTP7000 38

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
+1.5V_MEMC D1.5V_DDR3
D1.5V_DDR3 DDR3 1.5V By CAP - Place these Caps near Memory

L8900

C8902
C8908

C8922
C8904

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
C8913

C8914

C8915

C8916

C8917

C8918

C8919

C8920

C8921

C8923

C8924

C8925

C8926

C8927

C8928

C8929

C8930
10uF

10uF 0.1uF
10V 16V

Close to DDR Power Pin


+3.3V_MEMC
+12V +3.3V_MEMC
IC8903
AOZ1072AI
L8905
PGND LX_2 3.6uH
L8902 1 8
D1.5V_DDR3 CIC21J501NE
D1.5V_DDR3 NR8040T3R6N

R8933
VIN LX_1
2 7

1%
27K
R8900

1K 1%

R8919

2A
1K 1%

AGND EN POWER_ON/OFF2_2
C8942 C8944
3 6 R1

4.7K
R8934
22uF 0.1uF

1%
C8932 C8934 R8928
MVREFDQ 10K 10V 16V
0.1uF

10uF 10uF
1000pF

MVREFCA FB COMP
1%

0.1uF

1000pF

25V 25V
R8904

4 5
1%

OPT
R8920

9.1K C8940
C8903

2200pF
C8901

R8925 100pF
C8910
1K

C8909

OPT C8937
1K

50V
OPT

R8935

1%
10K
R2
Vout=0.8*(1+R1/R2)
AR8900
FRC_DQL[5] DDR3_DQL[5]
FRC_DQL[7] DDR3_DQL[7]
FRC_DQL[3] DDR3_DQL[3]
FRC_DQL[1] DDR3_DQL[1]
10

AR8901
IC8900
FRC_A[9] DDR3_A[9]
H5TQ1G63BFR-12C
FRC_A[2] DDR3_A[2] DDR3_A[0-12]
FRC_A[0] DDR3_A[0]
M8 N3 DDR3_A[0]
FRC_BA2
10

AR8902
DDR3_BA2 MVREFCA VREFCA A0
A1
A2
P7
P3
DDR3_A[1]
DDR3_A[2]
URSA3 DDR3 1.5V
H1 N2 DDR3_A[3]
FRC_DQL[0] DDR3_DQL[0] MVREFDQ VREFDQ A3
P8 DDR3_A[4]
FRC_DQL[2] DDR3_DQL[2] A4
P2 DDR3_A[5] +3.3V_MEMC +1.5V_MEMC
FRC_DQL[6] DDR3_DQL[6] R8921 A5
L8 R8 DDR3_A[6]
FRC_DQL[4] DDR3_DQL[4] ZQ A6
R2 DDR3_A[7]
240
IC8901

CIC21J501NE
10 A7 1074 mA
1% T8 DDR3_A[8]
A8

L8903
AR8903 B2 R3 DDR3_A[9]
FRC_DQU[7] DDR3_DQU[7] D9
VDD_1 A9
L7 DDR3_A[10]
AP1117EG-13
FRC_DQU[1] DDR3_DQU[1] VDD_2 A10/AP
G7 R7 DDR3_A[11]
FRC_DQU[5] DDR3_DQU[5] VDD_3 A11
K2 N7 DDR3_A[12]
FRC_DQU[3] DDR3_DQU[3] VDD_4 A12/BC
K8 T3
10 VDD_5 A13
N1
VDD_6
IN OUT
R8909 N9 M7
VDD_7 A15

R8936
FRC_DMU DDR3_DMU R1
10
R9
VDD_8
M2
ADJ/GND
R8910

1
270
R8927
VDD_9 BA0 DDR3_BA0

1%
FRC_DQSL DDR3_DQSL N8
10 BA1 DDR3_BA1
M3
BA2 DDR3_BA2 C8935
R8913 A1 C8938 C8946
DDR3_MCLK 10uF
VDDQ_1 0.1uF
R8922

FRC_DQSLB DDR3_DQSLB A8 J7 16V 22uF


150

10 R8929 16V
OPT

VDDQ_2 CK
C1 K7 56
R8914 VDDQ_3 CK
FRC_DML DDR3_DML C9 K9 DDR3_MCLKB
VDDQ_4 CKE 1%
10 D2
VDDQ_5 DDR3_CKE
D1.5V_DDR3 E9 L2
R8911 VDDQ_6 CS
F1 K1
FRC_DQSU DDR3_DQSU VDDQ_7 ODT DDR3_ODT
10 H2 J3
R8912 VDDQ_8 RAS DDR3_RASB
H9 K3
FRC_DQSUB DDR3_DQSUB VDDQ_9 CAS DDR3_CASB
10 L3 D1.5V_DDR3
WE DDR3_WEB R8923
J1 10K
AR8904 NC_1
J9 T2
FRC_DQU[2] DDR3_DQU[2] NC_2 RESET
L1 DDR3_RESETB
FRC_DQU[6] DDR3_DQU[6] NC_3
L9
FRC_DQU[0] DDR3_DQU[0] NC_4
T7 F3
FRC_DQU[4] DDR3_DQU[4] NC_6 DQSL DDR3_DQSL
G3
10 DQSL DDR3_DQSLB

A9 C7
VSS_1 DQSU DDR3_DQSU
AR8906 B3 B7
VSS_2 DQSU DDR3_DQSUB
FRC_A[3] DDR3_A[3] E1
VSS_3
FRC_A[5] DDR3_A[5] G8 E7
VSS_4 DML DDR3_DML
FRC_A[7] DDR3_A[7] J2 D3 DDR3_DQL[0-7]
VSS_5 DMU DDR3_DMU
FRC_DDR3_RESETB DDR3_RESETB J8
10 VSS_6
M1
M9
P1
VSS_7
VSS_8
DQL0
DQL1
E3
F7
F2
DDR3_DQL[0]
DDR3_DQL[1]
DDR3_DQL[2]
URSA3 CORE 1.26V
AR8905 VSS_9 DQL2
P9 F8 DDR3_DQL[3]
FRC_CASB DDR3_CASB VSS_10 DQL3
T1 H3 DDR3_DQL[4]
FRC_ODT DDR3_ODT VSS_11 DQL4
T9 H8 DDR3_DQL[5]
FRC_WEB DDR3_WEB VSS_12 DQL5
G2 DDR3_DQL[6]
FRC_BA0 DDR3_BA0 DQL6
H7 DDR3_DQL[7]
10 DQL7
B1 +1.26V_MEMC
VSSQ_1 +12V
R8915 B9 D7 DDR3_DQU[0] IC8902
VSSQ_2 DQU0 AOZ1072AI
FRC_RASB DDR3_RASB D1 C3 DDR3_DQU[1]
10 VSSQ_3 DQU1

L8901
D8 C8 DDR3_DQU[2] L8904
VSSQ_4 DQU2
E2 C2 DDR3_DQU[3] PGND LX_2 3.6uH
VSSQ_5 DQU3 1 8
E8 A7 DDR3_DQU[4]
VSSQ_6 DQU4
R8916 F9 A2 DDR3_DQU[5] NR8040T3R6N
VSSQ_7 DQU5

R8930
FRC_MCLK DDR3_MCLK G1 B8 DDR3_DQU[6] VIN LX_1

3.3K
10 2 7

1%
VSSQ_8 DQU6
R8917 G9 A3 DDR3_DQU[7]
VSSQ_9 DQU7
FRC_MCLKB
10
DDR3_MCLKB AGND
3
2A 6
EN POWER_ON/OFF2_1
R1
C8941 C8943

3.9K
R8931
22uF 0.1uF

1%
C8931 C8933 R8926
10K 10V 16V
10uF 10uF
DDR3_DQU[0-7] FB COMP
R8918 25V 25V 4 5
OPT
FRC_CKE DDR3_CKE 6.2K C8939
10 3300pF
R8924 100pF
C8936 50V
AR8908

R8932
FRC_A[8] DDR3_A[8]

1%
12K
FRC_A[6] DDR3_A[6] R2
FRC_A[4]
FRC_BA1
DDR3_A[4]
DDR3_BA1
Vout=0.8*(1+R1/R2)
10
AR8907
FRC_A[10] DDR3_A[10]
FRC_A[12] DDR3_A[12]
FRC_A[1] DDR3_A[1]
FRC_A[11] DDR3_A[11]
10

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS COMMON 2009.09.11
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
URSA3 DDR & Power
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 89

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
C9038 C9039

LVDS_TX_0_DATA0_P
LVDS_TX_0_DATA0_N
LVDS_TX_0_DATA1_P
LVDS_TX_0_DATA1_N
LVDS_TX_0_DATA2_P
LVDS_TX_0_DATA2_N
LVDS_TX_0_DATA3_P
LVDS_TX_0_DATA3_N
LVDS_TX_0_DATA4_P
LVDS_TX_0_DATA4_N
LVDS_TX_1_DATA0_P
LVDS_TX_1_DATA0_N
LVDS_TX_1_DATA1_P
LVDS_TX_1_DATA1_N
LVDS_TX_1_DATA2_P
LVDS_TX_1_DATA2_N
LVDS_TX_1_DATA3_P
LVDS_TX_1_DATA3_N
LVDS_TX_1_DATA4_P
LVDS_TX_1_DATA4_N

LVDS_TX_0_CLK_P
LVDS_TX_0_CLK_N
LVDS_TX_1_CLK_P
LVDS_TX_1_CLK_N
22pF 22pF FRC OPTION LOW HIGH
X9000
K14 NON_MIRROR MIRROR

12MHz T10 LVDS MINI_LVDS

Serial Flash R9029


1M
R10
R9
GIP

SCAN_OFF
NON_GIP

SCAN_ON
U10 LD NON_LD

URSA3_LOCAL_DIMMING URSA3_NON_LOCAL_DIMMING
+3.3V_MEMC
+3.3V_MEMC
IC9000-*1 R9017 R9023 R9037 0
W25X40BVSSIG FRC_CONF0 DPM_A

URSA3_SCANNING_OFF URSA3_SCANNING_ON
+3.3V_MEMC MINI_LVDS
100 100
CS VCC

URSA3_LVDS URSA3_MINI_LVDS
1 8
R9018 R9024

URSA3_GIP URSA3_NON_GIP
URSA3_MIRROR

100
R9042
DO[IO1] HOLD
2 7
100 100
0.1uF
C9028

WP CLK
3 6
R9019 R9025

FRC_CONF0

FRC_RESET
R9033

R9035
GND DI[IO0]

R9052

R9054

R9056
4.7K

4.7K
IC9000 4 5

4.7K

4.7K

4.7K
100 100

H_CONV
MX25L4005CM2I-12G SW9000

FRC_SPI_CK
FRC_SPI_CZ
FRC_SPI_DI
FRC_SPI_DO
R9020 R9026
URSA3_FLASH_WINBOND_NEW JTP-1127WEM
R9000 10 CS#
1 8
VCC
100 100
FRC_SPI_CZ 1 2

R9053

R9055

R9057
R9001 10 SO HOLD#

4.7K

4.7K

4.7K
FRC_SPI_DO 2 7 R9021 R9027

URSA3_NON_MIRROR

R9036
R9034
R9002 10K 3 4

4.7K
WP# SCLK R9005 10

4.7K
3 6
FRC_SPI_CK IC9000-*2 100 100
W25X40VSSIG
GND SI R9006 10 R9022 R9028

R9030 URSA3
4 5

0
FRC_SPI_DI CS VCC
1 8
EAN61009401
100 100
DO HOLD
URSA3_FLASH_MACRONIX 2 7

FRC_CONF1
WP CLK
3 6

100
100
GND DIO
4 5

R9031
R9032
EAN35097301

R9041
URSA3_FLASH_WINBOND_OLD
820

K14
J13
H14
G13
F14
E13

U14
U15
R13
T13
T14

T10
T11
R10
U11

U12
U10
R11

R12

T12

U13

P13
N14
N12
N13

M14
C13
A2
B2
A4
B4
C3
C4
B3
A3
C1
C2
B1
A1

A6
B6
A8
B8
C7
C8
B7
A7
C5
C6
B5
A5

A9
B9

D3
D4
E4
D5
D7
F4

R7
U8
U7
T8
T7

R9

U9

T9

R8
RECKP
RECKN
RE0P
RE0N
RE1P
RE1N
RE2P
RE2N
RE3P
RE3N
RE4P
RE4N

ROCKP
ROCKN
RO0P
RO0N
RO1P
RO1N
RO2P
RO2N
RO3P
RO3N
RO4P
RO4N

XTALO
XTALI

GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[12]
GPIO[13]
GPIO[14]

M_S_PIF_CLK_1
M_S_PIF_CLK_2
M_S_PIF_CS
M_S_PIF_DA1
M_S_PIF_FC

S_M_PIF_CLK
S_M_PIF_CS
S_M_PIF_DA0
S_M_PIF_DA1
S_M_PIF_FC

LTD_CLK_L
LTD_CLK_R
LTD_DA0_L
LTD_DA0_R
LTD_DA1_L
LTD_DA1_R
LTD_DE_L
LTD_DE_R

OP_SYNC_L
OP_SYNC_R

PLL_LOCK_L
PLL_LOCK_R

SOFT_RST_L
SOFT_RST_R

SPI_CK
SPI_CZ
SPI_DI
SPI_DO

RESET
REXT
FRC_A[0-12]

FRC_A[0] E2 B14
AVDD_PLL DDR3_A0/DDR2_NC A0P/RV0+ RXB0+
+3.3V_MEMC FRC_A[1] U6 A14
DDR3_A1/DDR2_A6 A0M/RV0- RXB0-
+3.3V_MEMC AVDD FRC_A[2] E3 C14
DDR3_A2/DDR2_A7 A1P/RV1+ RXB1+
L9004 FRC_A[3] G2 C15
CIC21J501NE DDR3_A3/DDR2_A1 A1M/RLV1- RXB1-
L9005 FRC_A[4] R4 A15
CIC21J501NE DDR3_A4/DDR2_CASZ A2P/RV2+ RXB2+
C9004 C9009 FRC_A[5] G1 B15
DDR3_A5/DDR2_A10 A2M/RV2- RXB2-
10uF 0.1uF FRC_A[6] U5 B16
C9019 C9024 C9029 C9032 DDR3_A6/DDR2_A0 ACKP/R3+ RXBCK+
10uF 0.1uF 0.1uF FRC_A[7] F3 A16
10uF DDR3_A7/DDR2_A5 ACKM/RV3- RXBCK-
FRC_A[8] T5 A17
DDR3_A8/DDR2_A2 A3P/RV4+ RXB3+
FRC_A[9] F1 B17
DDR3_A9/DDR2_A9 A3M/RV4- RXB3-
FRC_A[10] R6 C16
DDR3_A10/DDR2_A11 A4P/RV5+ RXB4+
FRC_A[11] R5 C17
DDR3_A11/DDR2_A4 A4M/RV5- RXB4-
FRC_A[12] T6
AVDD_MEMPLL AVDD_LVDS DDR3_A12/DDR2_A8
+3.3V_MEMC +3.3V_MEMC D16
B0P/RV6+ RXA0+
G3 D17
FRC_BA0 DDR3_BA0/DDR2_BA2 B0M/RV6- RXA0-
L9000 L9006 U4 D15
CIC21J501NE CIC21J501NE FRC_BA1 DDR3_BA1/DDR2_ODT B1P/RV7+ RXA1+
E1 E15
FRC_BA2 DDR3_BA2/DDR2_A12 B1M/RV7- RXA1-
C9000 C9005 F16
C9020 C9025 C9030 C9033 C9034 C9035 B2P/RV8+ RXA2+
10uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF U1 F17
10uF FRC_MCLK DDR3_MCLK/DDR2_MCLK B2M/RV8- RXA2-
U2 F15
FRC_MCLKB DDR3_MCLKZ/DDR2_MCLKZ BCKP/WPWM RXACK+
T4 G15
FRC_CKE DDR3_CKE/DDR2_RASZ BCKM/OPT_P RXACK-
G17
B3P/OPT_N RXA3+
H2 G16
FRC_ODT DDR3_ODT/DDR2_BA1 B3M/FLK RXA3-
J1 H16
+3.3V_MEMC VDDP FRC_RASB DDR3_RASZ/DDR2_WEZ B4P/GCLK6 RXA4+
H3 H17
FRC_CASB DDR3_CASZ/DDR2_CKE B4M/GLCK5 RXA4-
L9001
CIC21J501NE
FRC_WEB
H1
DDR3_WEZ/DDR2_BA0 IC9001 C0P/LV0+
H15
RXC0+
F2 J15
FRC_DDR3_RESETB DDR3_RESET/DDR2_A3 C0M/LV0- RXC0-
C9006 C9010 C9013 C9016 C9021 C9026 J17
C9001
10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
FRC_DQSL
M3
DDR2_DQS0/DDR3_DQS0
LGE7378A[FRC_TCON_URSA3] C1P/LV1+
C1M/LV1-
J16
RXC1+
RXC1-
N2 K16
FRC_DQSU DDR2_DQS1/DDR3_DQS1 C2P/LV2+ RXC2+
K17
C2M/LV2- RXC2-
N1 K15
FRC_DQSLB
FRC_DQSUB
N3
DDR2_DQSB0/DDR3_DQSB0
DDR2_DQSB1/DDR3_DQSB1
URSA3 CCKP/LV3+
CCKM/LV3-
L15
L17
RXCCK+
RXCCK-
C3P/LV4+ RXC3+
R2 L16
FRC_DML DDR2_DQ7/DDR3_DQM0 C3M/LV4- RXC3-
K3 M16
FRC_DMU DDR2_DQ11/DDR3_DQM1 C4P/LV5+ RXC4+
M17
C4M/LV5- RXC4-
AVDD_DDR FRC_DQL[0] K2
+1.5V_MEMC DDR2_DQ6/DDR3_DQ0
FRC_DQL[1] R3 M15
DDR2_DQ0/DDR3_DQ1 D0P/LV6+ RXD0+
L9002 FRC_DQL[2] K1 N15
DDR2_DQ1/DDR3_DQ2 D0M/LV6- RXD0-
CIC21J501NE FRC_DQL[3] T1 N17
DDR2_DQ2/DDR3_DQ3 D1P/LV7+ RXD1+
FRC_DQL[4] J2 N16
C9007 C9011 C9014 C9017 C9022 C9027 C9031 DDR2_DQ4/DDR3_DQ4 D1M/LV7- RXD1-
C9002 FRC_DQL[5] T3 P15
10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF DDR2_NC/DDR3_DQ5 D2P/LV8+ RXD2+
FRC_DQL[6] J3 R15
DDR2_DQ3/DDR3_DQ6 D2M/LV8- RXD2-
FRC_DQL[7] T2 R17
DDR2_DQ5/DDR3_DQ7 DCKP/GOE RXDCK+
FRC_DQL[0-7] R16
DCKM/GSC/GCLK3 RXDCK-
FRC_DQU[0] P2 T16
DDR2_DQ8/DDR3_DQ8 D3P/GSP_R RXD3+
FRC_DQU[1] L3 T17
DDR2_DQ14/DDR3_DQ9 D3M/GSP RXD3-
FRC_DQU[2] R1 T15
DDR2_DQ13/DDR3_DQ10 D4P/SOE RXD4+
FRC_DQU[3] L1 U17
DDR2_DQ12/DDR3_DQ11 D4M/POL RXD4-
FRC_DQU[4] P1
DDR2_DQ15/DDR3_DQ12
FRC_DQU[5] L2 P16
VDDC DDR2_DQ9/DDR3_DQ13 GCLK4 GCLK4
+1.26V_MEMC FRC_DQU[6] P3 P17
DDR2_DQ10/DDR3_DQ14 GCLK2 GCLK2
FRC_DQU[7] M1
L9003 DDR2_DQM1/DDR3_DQ15
FRC_DQU[0-7] D1
CIC21J501NE I2CS_SDA URSA3_SDA
M2 D2
DDR2_DQM0/DDR3_NC I2CS_SCL URSA3_SCL
C9003 C9008 C9012 C9015 C9018 C9023
10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF P14
PWM0 FRC_PWM0
R9011 100 C9 R14
I2CM_SDA PWM1 FRC_PWM1
R9012 100 D9
I2CM_SCL
R9013 100 P7 B13
V_SYNC
DVDD_DDR[1.26V]

I2CM_SDA2_L LPLL_FBCLK R9043


R9014 100 N8 U16 0
I2CM_SCL2_L LPLL_OUTCLK OPT
R9015 100 P9 A13
AVDD_LVDS_1
AVDD_LVDS_2
AVDD_LVDS_3
AVDD_LVDS_4

AVDD_MEMPLL

I2CM_SDA2_R LPLL_REFIN
AVDD_DDR_1
AVDD_DDR_2
AVDD_DDR_3
AVDD_DDR_4
AVDD_DDR_5
AVDD_DDR_6

AVDD_PLL_1
AVDD_PLL_2

R9016 100 N10


I2CM_SCL2_R
VDD_EVEN

VB1_TEST
VDD_ODD

TESTPIN
AVDD_1
AVDD_2

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

A10
A11
A12
B10
B11
B12
C11
D11
P9000 +3.3V_MEMC
12505WS-04A00
F8
F9

L5
L6
L7
L8
M7
M8

G12
H12
J12
K12

M6

F11
F12

J5

E16
E17

F6
F7
G5
G6
G7
H5
H6
J6

G11
K5
K6
M10
M11

C10
C12
G8
G9
G10
H7
H8
H9
H10
H11
J4
J7
J8
J9
J10
J11
K7
K8
K9
K10
K11
L9
L10
L11
M9
N4
P6

A10
A11
A12
B10
B11
B12
C11
D11

L13
F10

1K

1K

1K

1K
1
URSA3_SDA
22 R9003

OPT
R9044
R9040

R9046

R9048

R9050
2 AVDD AVDD_DDR AVDD_LVDS AVDD_PLL VDDC VDDP
URSA3_SCL 0
22 R9004 FRC_CONF0
SCL3_3.3V
22 R9007
3 FRC_CONF1
AVDD_MEMPLL
SDA3_3.3V
GVDD_ODD

FRC_PWM1
GVDD_EVEN

22 R9008
4 FRC_PWM0

R9049 OPT 1K

R9051 OPT 1K
R9047 OPT1K
1K
OPT
5
URSA3_SCL SCL1_3.3V
22 R9009

R9045
OPT LD_SCAN
SCAN_BLK2 R9038 100
URSA3_SDA SDA1_3.3V VDDC FRC_PWM1
22 R9010 LD_SCAN
L9007
CIC21J501NE R9039 100 FRC_PWM0
SCAN_BLK1/OPC_OUT
C9036 C9037
10uF 0.1uF

I2C ADR: GPIO1: HI:B8 LOW:B4


CHIP_CONF: {GPIO8, PWM1, PWM0}


CHIP_CONF= 3 d5: boot from internal SRAM


CHIP_CONF= 3 d6: boot from EEPROM
Separate DVDD_DDR Power


CHIP_CONF= 3 d7: boot from SPI Flash

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS COMMON 2009.09.11
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. URSA3 (NO L.D.) 90

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
D9103
[LEVEL Shift Block] MMSD4148T1G VDD_LCM

VCC_LCM
[POWER Block] 100V
EN2 (+16V)

(+3.3V) * Voltage Target CHECK Value!!


VDD_LCM = 16.25V
VGH = 28.50V R9156 R9165 C9134 C9138 To reduce
R9108
VGL = -5.35V 150K
1%
18K
1%
OPT Audible noise
100 TCON_42_FHD OPT 0.1uF
50V To reduce C9153
GIP C9150 R9182
C9139 Audible noise C9142 100uF
1uF 1uF 9.1K
C9135 C9141 50V 25V
C9102 R9109 R9168-*1 R9157 R9166 OPT 1uF 50V 47uF 50V 1/8W
OPT 3K 75K 15K 25V
FLK

DISCHG 1% 1%
OPT GIP 33K TCON_42_FHD TCON_42_FHD
NON_GIP
VDD_LCM L9102
(+16V) C9128-*1 D9106 MBRA340T3G 22UH
C9136
470pF D9104 MBRA340T3G C9148
50V 27pF 50V 2.8A
R9113 NON_GIP 22uF
NON_GIP
EP[VGOFF]

10K 25V
R9146
GIP 33K C9128 R9168 C9145-*1
VSENSE

NON_GIP R9169 C9145


YDCHG
FLK1

FLK2

FLK3

1000pF 10K 560pF


GND

50V 2.2 1000pF 50V


RE

GIP 50V
R9147-*1 R9147 VGH GIP NON_GIP

PGOOD
D9100 0 2.7K GIP

AGND
CRST

COMP

PGND
NON_GIP (+25V)
28

27

26

25

24

23

22

VGH MMSD4148T1G

FB1
SW0
SW1
LX1
LX1
GIP
GVDD_ODD_I A9 1 21 Y9 (+25V) EN2 VGH_M
VDD_ODD 100V R9152 0 PANEL_VCC
THERMAL (+25V) C9143
A8 Y8 OPT NON_GIP (+12V)

40
39
38
37
36
35
34
33
32
31
GVDD_EVEN_I 2 29 20 VDD_EVEN 4.7uF/50V(3216) D9101 0.1uF
R9132 KDS226 THR PGND
A7 Y7 R9153 0 1 30 50V
GSP/GVST_I 3 19 C9122

NCP18WB473F10RB
VST C9116 0 C NON_GIP DRVP 2 29 EN2
EN2

TH9000
A6 IC9101 Y6 1uF C9117 R9180

GIP
AC

47k-ohm
4 18 MINI_LVDS 1uF A 0.47uF GND2 3 28 VL
GCLK6_I MAX17119DS CLK6 R9124 R9125 C9112 R9129 50V 50V 25V 360
4.7uF R9154 0 GIP SRC 4 27 DEL2
A5 5 GIP 17 Y5 18K 18K 56K 1%
GCLK5_I CLK5 50V GON EN1
R9150 0 GIP 5 IC9103 26
TCON_42_FHD PANEL_VCC
A4 6 DEV 16 Y4 R9148 R9155 DRN 6 MAX17113ETL+ 25 FSEL
GCLK4_I CLK4 510 NON_GIP MODE R9171 R9194 (+12V)
510 NON_GIP MINI_LVDS VIN
A3 Y3 R9130 R9133 R9134 VDD_LCM 7 24
GSC/GCLK3_I 7 EAN60987201 15 10 10 C9125 68pF NON_GIP 360
CLK3 220K 1% (+16V) DLP 8 23 IN2 0
GIP GIP C9126 0.047uF DEV OPT
10

11

12

13

14

TCON_42_FHD NON_GIP FBP IN2


9 22
8

Value should VGH_FB


GPGND 10 EAN60924401 21 OUT C9147
be checked VGH_FB
A2

A1

GON1

GOFF

GON2

Y1

Y2

1uF R9173 C9152 C9155 C9162


C9144

11
12
13
14
15
16
17
18
19
20
50V 1K 1uF 22uF 22uF
R9131 0.1uF 10V
50V 25V 25V

CTL
DRVN
AGND
FBN
REF
DEL1
FB2
BST
LX2
LX2
11K 1%
TCON_42_FHD R9133-*1 R9134-*1 R9148-*1 R9174
GCLK2_I 200 200 0 OPT
NON_GIP NON_GIP GIP R9158 R9167
R9155-*1 0 0
GOE/GCLK1_I GIP NON_GIP
0
GIP VCC_LCM
CLK2
(+3.3V)
CLK1 L9101
C9101 VGH
0.22uF R9105 R9110 22UH

FLK
C9140

REF
VGL_FB
(+25V) 22 22
50V
GIP GIP GIP 0.1uF 2.8A
C9104 C9123 VCC_LCM 50V
R9111 C9107 R9114 R9115 R9116 1uF (+3.3V) C9137 C9146 C9149 C9151
1uF 10 OPT 10 10 10V 0.1uF D9105 0.1uF C9154 R9181
50V 1uF MBRA340T3G 150pF 22uF OPT
GIP OPT GIP GIP REF 50V 40V 50V 5.1K
GIP 50V 50V 10V
VGL GIP GIP
R9135 C9118 TCON_42_FHD
(-5V) 3.6K 10uF R9144 1% OPT
VGH 16V C9124 R9149 R9151
(+25V) 27K 1uF 0 0
VGL 50V C9137-*1
VGL_FB 2200pF
(-5V) D9102
KDS226 50V
R9145 1%
C9127 NON_GIP
150K C
TCON_42_FHD A AC 1uF
50V

R9170
DPM EN2
10

[P-GAMMA Block] R9172


1K
Slave Address : 0xE8h
(AO Pin - GND)
SCL3_3.3V

GMA16

GMA15

VDD_LCM Signal Name Change VCC_LCM


(+16V)
To reduce
Audible noise [HVDD Block] (+3.3V)
R9103

1uF/50V(2012) R9112
33

R9143
C9106 10 3.3K
1/8W
EP[GND]

1uF GIP R9159 R9175


AVDD_2

50V R9136 0 0
RXA3-
GMA8

GMA7

NC_2

FLK RXD3- GSP/GVST_I GCLK2 GCLK2_I


SCL

10 NON_GIP GIP
MINI_LVDS
C9129 C9156
6.8uH/1.8A C9119 15pF 15pF
20

19

18

17

16

VCC_LCM (6x6x2mm) HVDD 15pF


(+3.3V) SDA3_3.3V R9100 SDA GMA6 50V 50V 50V
1 15 GMA13 VDD_LCM PANEL_VCC L9100 R9160
6.8uH NON_GIP 0 NON_GIP OPT
33 THERMAL (+16V) (+12V)
A0 2 21 14 GMA5 DEV RXD3+
GMA12 NON_GIP
DVDD IC9100 GMA4 R9176
BLM18PG121SN1D

BLM18PG121SN1D

3 13 GSP_R 0
GMA7 MINI_LVDS
C9100 MAX9668ETP+ VCC_LCM GCLK4 GCLK4_I
AGND_AMP 4 12 GMA3 VGH GIP
0.1uF GMA6 C9157
L9104

L9103

MINI_LVDS (+3.3V)
OPT

50V (+25V) 15pF


VCOM 5 11 GMA2
VCOM DEV GMA4 50V
R9121 R9123
10

OPT
0 1M
6

R9197
GIP NON_GIP R9139 0 3.3K
VGI_P
VCOM_FB

AVDD_AMP

AVDD_1

NC_1

GMA1

PGND_2

GIP NON_GIP
R1 R9161 R9177
SW_2

SW_1

R9126 C9113 C9114 C9115 R9193 R9195


10uF/25V(3216) MINI_LVDS 0 0
510K 22pF 22uF 10uF 6.2K 6.2K
PG

RXDCK+ GOE/GCLK1_I RXA4- GCLK5_I


TCON_42_FHD 50V 16V 16V OPT OPT GIP
C9108 C9109 VGL C9158
VDD_LCM 10uF 10uF
(-5V) 15pF
16

15

14

13

VCOM_FB0 GMA3 (+16V) 25V 25V C9130


TCON_42_FHD

PGND_1 GND_2 15pF 50V


1 12
1K

1K

DEV OPT
50V
VIN_1 GND_1
OPT

MINI_LVDS 2 11 NON_GIP
IC9102 R9140 0
R9101

R9104

VGI_N
VIN_2 3 TPS62110RSAR 10 FB GIP
C9103 C9105 R9162 R9178
R9117 MINI_LVDS 0 0
0.1uF 0.1uF EN 4 9 AGND R2 GSC/GCLK3_I
1%

50V 50V EAN60985901 VGL RXDCK- RXA4+ GCLK6_I


47K C9131 C9159
R9127 R9128 (-5V) GIP
5

OPT R9118 C9110 150K 200K R9141 15pF 15pF


10K 1uF TCON_42_FHD 50V 50V
TCON_42_FHD
SYNC

LBO

LBI

VINA

OPT 25V 0 NON_GIP OPT


VCOMRFB

VCOMLFB

R9142
DISCHG VGL_I
0
R9196 24K Vo = 1.153*(1+R1/R2) R9163
R9122 OPT 0 R9179
EN2 10 DPM_A
For P-Gamma Data Download GVDD_ODD GVDD_ODD_I DPM
GIP 0
D9107 100V
P9100 C9111 C9132 C9160
12505WS-03A00 1uF 15pF 15pF
MMSD4148T1G 50V
50V 50V
VCOM_FB0

PANEL_VCC OPT
R9137
RXD4- POL
1 SCL3_3.3V 0
R9164
R9119 C9120 0
20K 15pF GVDD_EVEN GVDD_EVEN_I
2 SDA3_3.3V 50V GIP
C9133
1% TCON_42_FHD
R9120 15pF
R9102 3 7.5K 50V
OPT
1K R9138
4 RXD4+ SOE
0
R9106
VCOMR C9121
0 15pF
R9107 50V
VCOM VCOML
0

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS COMMON 09/09/10
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. T-Con (NO L.D.) 91

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only
32_FHD 37_FHD 42_FHD
VGH VGL VGH VGL VGH VGL

R9129-*1
22K
R9130-*1
220K
R9144-*1
51K
R9129-*2
47K
R9130-*2
220K
R9144-*2
20K 91 or 95 91 or 95
1% 1% 1% 1% 1% 1%
TCON_32_FHD TCON_32_FHD TCON_32_FHD TCON_37_FHD TCON_37_FHD TCON_37_FHD Sheet Sheet
R9131-*1 R9145-*1 R9131-*2 R9145-*2
270K 12K 150K
11K 1%
1% 1% 1%
TCON_32_FHD TCON_37_FHD TCON_37_FHD
TCON_32_FHD

VDD VDD VDD HVDD


HVDD HVDD
R9156-*1 R9165 OPEN R9126-*1
150K 510K R9156-*2 R9165-*2 R9126-*2
1%
TCON_32_FHD
1%
TCON_32_FHD
910K
1%
TCON_37_FHD
470K
1%
TCON_37_FHD
470K
1%
TCON_37_FHD
91 or 95 91 or 95
R9157-*1 R9166-*1 R9127-*1 R9128-*1 R9157-*2
56K
R9166-*2
56K R9127-*2
R9128 OPEN Sheet Sheet
27K 24K 150K 200K 91K
1% 1% 1% 1% 1% 1% 1%
TCON_32_FHD TCON_32_FHD TCON_32_FHD TCON_32_FHD TCON_37_FHD TCON_37_FHD TCON_37_FHD

VCOM FEED BACK VCOM FEED BACK VCOM FEED BACK

R9101-*1 R9104-*1 R9101-*2 R9104-*2


1K 1K 1K 1K
1%
TCON_32_FHD
1%
TCON_32_FHD
1%
TCON_37_FHD
1%
TCON_37_FHD
91 or 95
R9102-*1
1K
R9102-*2
1.5K
Sheet
1% 5%
TCON_32_FHD TCON_37_FHD

47_FHD 55_FHD
VGH VGL VGH VGL

R9129-*3 R9130-*3 R9144-*3 R9129-*4 R9130-*4 R9144-*4


51K 220K 51K 510K 68K 27K
1% 1% 1% 1% 1% 1%
TCON_47_FHD TCON_47_FHD TCON_47_FHD TCON_55_FHD TCON_55_FHD TCON_55_FHD

R9131-*3 R9145-*3 R9131-*4 R9145-*4


11K 270K 150K
1% 27K 1%
1% 1%
TCON_47_FHD TCON_47_FHD TCON_55_FHD
TCON_55_FHD

VDD HVDD VDD HVDD


R9156-*3 R9165 OPEN R9126-*3 R9165 OPEN
180K 510K R9156-*4 R9126-*4
1% 1% 150K 180K
1% 1%
TCON_47_FHD TCON_47_FHD
TCON_55_FHD TCON_55_FHD

R9157-*3 R9166-*3 R9127-*3 R9128-*3 R9127-*4 R9128-*4


75K 20K 150K 220K R9157-*4 R9166-*4 68K 56K
1% 1% 1% 75K 15K
1% 1% 1% 1% 1%
TCON_47_FHD TCON_47_FHD TCON_47_FHD TCON_47_FHD TCON_55_FHD TCON_55_FHD
TCON_55_FHD TCON_55_FHD

VCOM FEED BACK VCOM FEED BACK

R9101-*3 R9104-*3
1K R9101 OPEN R9104 OPEN
1K
1% 1%
TCON_47_FHD TCON_47_FHD
R9102-*3 R9102-*4
1K 0
1% 5%
TCON_47_FHD TCON_55_FHD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS Common 09/12/15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. T-Con Power Option 98

Copyright © 2010 LG Electronics. Inc. All rights reserved.


Only for training and service purposes LGE Internal Use Only

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