Anda di halaman 1dari 48

5 4 3 2 1

SYSTEM DC/DC
Project code: 91.4CQ01.001 TPS51125 36

JM41/JM51 Discrete Block Diagram PCB P/N


REVISION
: 48.4CQ01.0SB
: 08274-1
INPUTS

DCBATOUT
OUTPUTS
5V_S5(6A)
3D3V_S5(5A)

D 5V_AUX_S5 D

UMA LVDS 3D3V_AUX_S5


PCB STACKUP
UMA CRT Switchable LVDS LCD
Thermal Sensor 19 RT8202 37
CLK GEN. Intel CPU DIS LVDS Graphic RGB CRT
TOP L1
SMSC ICS9LPRS365B Penryn SFF DIS CRT 40, 41 S L2 INPUTS OUTPUTS
EMC2103 27 3 VCC/GND L3
DCBATOUT 1D05V_S0(10A)
4,5,6 S L4
HOST BUS 38
VRAM(DDR3) VCC/GND L5 RT8202
667/800/1066MHz@1.05V
4
64Mbx16x4 (512MB)
DDR3 Cantiga-GS SFF
57 GND/VCC L6 INPUTS OUTPUTS
800/1066 17,18
MHz AGTL+ CPU I/F
S L7 DCBATOUT 1D5V_S3(11A)

www.kythuatvitinh.com
DDR Memory I/F BOTTOM L8
PCIe x 16 RT9026 39
C
DDR3 INTEGRATED GRAHPICS
LVDS, CRT I/F
ATI M92-S2 CRT
C

800/1066 17,18
MHz CRT INPUTS OUTPUTS
7,8,9,10,11,12 BD
53,54,55,56 HDMI
X4 DMI 20 HDMI 5V_S5 DDR_VREF_S3
C-Link0
400MHz (1.2A)

CHARGER
23 LAN TXFM RJ45 MAX8731A 41
ICH9M SFF Giga LAN
Atheros AR8131
INT.SPKR 6 PCIe ports INPUTS OUTPUTS
1.5W PCI/PCI BRIDGE
Codec AZALIA ACPI 2.0 CHG_PWR
Int MIC Realtek DCBATOUT
4 SATA 18V 6.0A
ALC269Q 22 12 USB 2.0/1.1 ports
19 Mini 1 Card CPU DC/DC
ETHERNET (10/100/1000MbE)
MINI BD WLAN ADP3207A
B High Definition Audio PCIe x1 *3port 35 B

LPC I/F
Line Out USB 3 Port Mini 2 Card INPUTS OUTPUTS
Serial Peripheral I/F
Matrix Storage Technology(DO) 3G DCBATOUT
VCC_CORE
Active Managemnet Technology(DO)
25 0~1.3V
CRT 64A
MIC In
LPC BUS VGA
BD 13,14,15,16 ISL6263A
40
20
SATA INPUTS OUTPUTS
USB LPC
SATA CRT BD Camera KBC
Winbond DEBUG VCC_GFXCORE
HDD SATA 2 Port 20
17 WPCE773LA0DG SPI BIOS CONN. DCBATOUT
(7A)
28 (2MB)
29
A
SATA CARDREADER POWER BD MINI BD DIS
Digitally signed by dd A

ODD SATA BD 24
1 Port 26 3 Port 25
Touch INT. DN: cn=dd, o=dd,
Wistron ou=dd,
Corporation
CARDREADER BD
USB Blue Tooth Pad 30 KB 28 email=dddd@yahoo. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SATA
com, c=US
Title
24 MS/MS Pro/xD
SSD/HDD SATA 2 Port 24 /MMC/SD BLOCK DIAGRAM
Date: 2009.12.04
Size Document Number Rev
Custom
21 JM41_Discrete -1
Date: Tuesday, April 07, 2009 Sheet 1 of 48
5 4 3 2
19:23:30 +07'00' 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions page 92 Hub strapping configuration
ICH9 EDS 642879 Rev.1.5
and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down.

www.kythuatvitinh.com
GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller
Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister.
NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

1 DIS
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reference
Size Document Number Rev
A3
JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 2 of 48
A B C D E

1D05V_S0 3D3V_S0
3D3V_S0 R215
R220 R222
1 2 1D05V_CLK_S0

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1 2 3D3V_48MPW R_S0 C522 C516 C508 C512 C515 C532 3D3V_CLK_S0 1 2

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C525 C541 C517 C507 C526 C548 C549
0R0603-PAD

1
SC1U10V3KX-3GP

SC4D7U10V5ZY-3GP
C523 C524
0R0603-PAD 0R0603-PAD

SC4D7U6D3V3KX-GP

2
2

2
DY

4 4
3D3V_48MPW R_S0

C579
3D3V_CLK_S0 1D05V_CLK_S0
1 2
3D3V_S0
R210
R209 SC27P50V2JN-2-GP

2
U35

16

46
62
23

19
27
43
52
33
56
4

9
43 VGA_CLK_REQ# 1 2 CR#_G 1 2 X2
CL=20pF±0.2pF X-14D31818M-35GP

VDD48

VDDPLL3

VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDSRC
VDDCPU
VDDPCI
VDDREF
82.30005.891

1
1KR2J-1-GP 10KR2J-3-GP C542 82.30005.951
CPUT0 61 CLK_CPU_BCLK 4 CPU
3D3V_S0 1 2 60
CPUC0 CLK_CPU_BCLK# 4
GEN_XTAL_OUT 3 58
SC27P50V2JN-2-GP GEN_XTAL_IN 2
X1 CPUT1_F
57
CLK_MCH_BCLK 7 NB
X2 CPUC1_F CLK_MCH_BCLK# 7
4
3
2
1

www.kythuatvitinh.com
RN25 54
SRN10KJ-6-GP
R230 CPUT2_ITP/SRCT8
53
CLK_PCIE_ICH 14 SB DMI
CPUC2_ITP/SRCC8 CLK_PCIE_ICH# 14
14 CLK48_ICH 2 1 CLK_48 17 USB_48MHZ/FSLA
RN24 33R2F-3-GP 51
5
6
7
8

CR#_D R227 2 SRCT7/CR#_F


8 CLK_MCH_OE# 1 8 4,8 CPU_SEL0 1 2K2R2J-2-GP SRCC7/CR#_E 50 CR#_E
14 SATACLKREQ# 2 7 CR#_C 14 PM_STPPCI# 45
CR#_H PCI_STOP#
25 LAN_CLKREQ# 3 6 14 PM_STPCPU# 44 CPU_STOP# SRCT6 48 CLK_PCIE_MINI1 25 Wireless
25 W LAN_CLKREQ# 4 5 CR#_E 47 CLK_PCIE_MINI1# 25
SRCC6
3 SRN470J-3-GP G81 41 CLK_PCIE_LAN 25
3
SRCT10
16,17,18 SMBC_ICH 1GAP-CLOSE
2 SMBC_CKG 7 SCLK SRCC10 42 CLK_PCIE_LAN# 25 LAN
1 2 SMBD_CKG 6
16,17,18 SMBD_ICH SDATA
GAP-CLOSE 40 CR#_H
RN31 G80 SRCT11/CR#_H
63 39 CR#_G
3D3V_S0 PCLKCLK5 CK_PWRGD/PD# SRCC11/CR#_G
1 8
2 7 PCLKCLK4 37
3 6 PCLKCLK2
14 CLK_PW RGD SRCT9
38
CLK_PCIE_VGA 42 VGA
SRCC9 CLK_PCIE_VGA# 42
4 5 CPU_SEL2_R 8 PCI0/CR#_A
10 PCI1/CR#_B SRCT4 34 CLK_MCH_3GPLL 8 NB CLK
PCLKCLK2 11 35 CLK_MCH_3GPLL# 8
SRN10KJ-6-GP PCI2/TME SRCC4
4,8 CPU_SEL2 12 PCI3
PCLKCLK4 13 31 CR#_C
PCLKCLK5 PCI4/27_SELECT SRCT3/CR#_C CR#_D
14 PCI_F5/ITP_EN SRCC3/CR#_D 32

RN32 28
1 8 CPU_SEL2_R SRCT2/SATAT
29
CLK_PCIE_SATA 13 SB SATA
14 CLK_ICH14 SRCC2/SATAC CLK_PCIE_SATA# 13
29 PCLK_FW H 2 7 PCLKCLK2 4,8 CPU_SEL1 64
PCLKCLK4 CPU_SEL2_R FSLB/TEST_MODE
28 PCLK_KBC 3 6 5 REF0/FSLC/TEST_SEL
14 PCLK_ICH 4 5 PCLKCLK5 24 DREFSSCLK 8
27MHZ_NONSS/SRCT1/SE1
55 NC#55 27MHZ_SS/SRCC1/SE2 25 DREFSSCLK# 8 NB CLK
SRN33J-7-GP DY
CLK_ICH14 1 2 20 NB CLK

GNDSRC
GNDSRC
GNDSRC
GNDCPU
DREFCLK 8

GNDREF
SRCT0/DOTT_96

GNDPCI
DY EC48 SC22P50V2JN-4GP 21

GND48
SRCC0/DOTC_96 DREFCLK# 8
PCLK_ICH 1 2 (96 MHz)

GND

GND

GND
PCLK_KBC
DY EC45 SC22P50V2JN-4GP
1 2
DY EC46 SC22P50V2JN-4GP ICS9LPRS365BKLFT-GP-U

18
15
1

22
30
36
49
59
26

65
2 CLK48_ICH 2
1
EC44
2
SC22P50V2JN-4GP
71.09365.A03
2nd = 71.08513.003
EMI capacitor for Antenna team suggestion 3RD = 71.00875.C03
ICS9LPRS365YGLFT setting table
PIN NAME DESCRIPTION
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair SEL2 SEL1 SEL0
PCI0/CR#_A Byte 5, bit 6 CPU FSB
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
FSC FSB FSA
Byte 5, bit 5 PIN NAME DESCRIPTION 1 0 1 100M X
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 1 0 0 1 133M 533M
PCI1/CR#_B Byte 5, bit 4 0 = SRC3 enabled (default)
166M 667M
0 = CR#_B controls SRC1 pair (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair 0 1 1
1= CR#_B controls SRC4 pair SRCC3/CR#_D Byte 5, bit 0
200M 800M
0 = CR#_D controls SRC1 pair (default) 0 1 0
0 = Overclocking of CPU and SRC Allowed 1= CR#_D controls SRC4 pair
PCI2/TME 1 = Overclocking of CPU and SRC NOT allowed 0 0 0 266M 1067M
Byte 6, bit 7
0 = SRC7# enabled (default)
1
PCI3 SRCC7/CR#_E 1= CR#_F controls SRC6
DIS 1

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# Byte 6, bit 6
PCI4/27M_SEL 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# 0 = SRC7 enabled (default)
SRCT7/CR#_F 1= CR#_F controls SRC8 Wistron Corporation
0 =SRC8/SRC8# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PCI_F5/ITP_EN 1 = ITP/ITP# Byte 6, bit 5 Taipei Hsien 221, Taiwan, R.O.C.
0 = SRC11# enabled (default)
Byte 5, bit 3 SRCC11/CR#_G 1= CR#_G controls SRC9 Title
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 6, bit 4 Clock Generator
SRCT3/CR#_C Byte 5, bit 2 0 = SRC11 enabled (default) Size Document Number Rev
0 = CR#_C controls SRC0 pair (default), SRCT11/CR#_H 1= CR#_H controls SRC10
JM41_Discrete -1
1= CR#_C controls SRC2 pair
Date: Monday, April 06, 2009 Sheet 3 of 48
A B C D E
A B C D E

H_A#[35..3]
7 H_A#[35..3]
H_DINV#[3..0]
H_DINV#[3..0] 7
1 H_DSTBN#[3..0]
H_DSTBN#[3..0] 7
CPU1A 1 OF 6 TP4 TPAD14-GP
H_A#3 P2 M4 1D05V_S0 H_DSTBP#[3..0]
A3# ADS# H_ADS# 7 H_DSTBP#[3..0] 7
H_A#4 V4 J5 H_BNR# 7
H_A#5 A4# BNR# Place testpoint on H_D#[63..0]
4 W1 A5# BPRI# L5 H_BPRI# 7 H_D#[63..0] 7 4
H_A#6 T4 H_IERR# with a GND
A6#

1
ADDR GROUP 0
H_A#7 AA1 N5 0.1" away
A7# DEFER# H_DEFER# 7
H_A#8 AB4 F38 H_DRDY# 7
H_A#9 A8# DRDY# R178
T2 A9# DBSY# J1 H_DBSY# 7
H_A#10 AC5 56R2F-1-GP
A10#

CONTROL
H_A#11 AD2 M2 H_BREQ#0 7

2
H_A#12 A11# BR0#
AD4 A12#
H_A#13 AA5 B40 H_IERR#
H_A#14 A13# IERR#
AE5 A14# INIT# D8 H_INIT# 13
H_A#15 AB2
H_A#16 A15#
AC1 A16# LOCK# N1 H_LOCK# 7
7 H_ADSTB#0 Y4 ADSTB0# H_CPURST# 7
G5 CPU1B 2 OF 6
7 H_REQ#[4..0] RESET# H_RS#[2..0] 7
H_REQ#0 R1 K2 H_RS#0 H_D#0 F40 AP44 H_D#32
H_REQ#1 R5 REQ0# RS0# H_RS#1 H_D#1 D0# D32# H_D#33
REQ1# RS1# H4 G43 D1# D33# AR43
H_REQ#2 U1 K4 H_RS#2 H_D#2 E43 AH40 H_D#34
H_REQ#3 P4 REQ2# RS2# H_D#3 D2# D34# H_D#35
REQ3# TRDY# L1 H_TRDY# 7 J43 D3# D35# AF40

www.kythuatvitinh.com

DATA GROUP 0
H_REQ#4 W5 H_D#4 H40 AJ43 H_D#36
REQ4# H_THERMDA H_D#5 D4# D36# H_D#37
HIT# H2 H_HIT# 7 H44 D5# D37# AG41
H_A#17 AN1 F2 H_HITM# 7 H_D#6 G39 AF44 H_D#38
A17# HITM# D6# D38#

1
H_A#18 AK4 H_D#7 E41 AH44 H_D#39
A18# D7# D39#

DATA GROUP 2
H_A#19 AG1 AY8 C417 H_D#8 L41 AM44 H_D#40
H_A#20 A19# BPM0# SC2200P50V2KX-2GP H_D#9 D8# D40# H_D#41
ADDR GROUP 1

AT4 BA7 K44 AN43

2
H_A#21 A20# BPM1# H_THERMDC H_D#10 D9# D41# H_D#42
AK2 A21# BPM2# BA5 DY N41 D10# D42# AM40
H_A#22 AT2 AY2 H_D#11 T40 AK40 H_D#43
H_A#23 A22# BPM3# H_D#12 D11# D43# H_D#44
AH2 AV10 M40 AG43
Close to NB
XDP/ITP SIGNALS

H_A#24 A23# PRDY# XDP_BPM#5 H_D#13 D12# D44# H_D#45


AF4 A24# PREQ# AV2 G41 D13# D45# AP40
H_A#25 AJ5 AV4 XDP_TCK H_D#14 M44 AN41 H_D#46
3 H_A#26 A25# TCK XDP_TDI 1D05V_S0 H_D#15 D14# D46# H_D#47 3
AH4 A26# TDI AW7 L43 D15# D47# AL41
H_A#27 AM4 AU1 XDP_TDO K40 AK44 H_DSTBN#2 7
A27# TDO 7 H_DSTBN#0 DSTBN0# DSTBN2#
H_A#28 AP4 AW5 XDP_TMS J41 AL43 H_DSTBP#2 7
A28# TMS 7 H_DSTBP#0 DSTBP0# DSTBP2#
H_A#29 AR5 AV8 XDP_TRST# P40 AJ41 H_DINV#2 7
A29# TRST# 7 H_DINV#0 DINV0# DINV2#

1
H_A#30 AJ1 J7 XDP_DBRESET#
H_A#31 A30# DBR#
AL1 A31#
H_A#32 AM2 R182 H_D#16 P44 AV38 H_D#48
H_A#33 A32# 56R2F-1-GP H_D#17 D16# D48# H_D#49
AU5 A33# THERMAL V40 D17# D49# AT44
H_A#34 AP2 H_D#18 V44 AV40 H_D#50

2
H_A#35 A34# CPU_PROCHOT#_1 H_D#19 D18# D50# H_D#51
AR1 A35# PROCHOT# D38 AB44 D19# D51# AU41
AN5 BB34 H_THERMDA 27 H_D#20 R41 AW41 H_D#52
7 H_ADSTB#1 ADSTB1# THRMDA D20# D52#

DATA GROUP 1
BD34 H_THERMDC 27 H_D#21 W41 AR41 H_D#53
THRMDC H_D#22 D21# D53# H_D#54
13 H_A20M# C7 A20M# N43 D22# D54# BA37
13 H_FERR# D4 B10 PM_THRMTRIP-A# 8,13,32 H_D#23 U41 BB38 H_D#55
FERR# THERMTRIP# D23# D55#
ICH

DATA GROUP 3
13 H_IGNNE# F10 H_D#24 AA41 AY36 H_D#56
IGNNE# PM_THRMTRIP# should connect to H_D#25 D24# D56# H_D#57
AB40 D25# D57# AT40
F8 ICH9 and MCH without T-ing H_D#26 AD40 BC35 H_D#58
13 H_STPCLK# STPCLK# D26# D58#
C9 H CLK PH @ page48 H_D#27 AC41 BC39 H_D#59
13 H_INTR LINT0 D27# D59#
13 H_NMI C5 A35 CLK_CPU_BCLK 3 H_D#28 AA43 BA41 H_D#60
LINT1 BCLK0 1D05V_S0 H_D#29 D28# D60# H_D#61
13 H_SMI# E5 SMI# BCLK1 C35 CLK_CPU_BCLK# 3 Y40 D29# D61# BB40
H_D#30 Y44 BA35 H_D#62
H_D#31 D30# D62# H_D#63
V2 RSVD#V2 T44 D31# D63# AU43

2
RESERVED

Y2 RSVD#Y2 7 H_DSTBN#1 U43 DSTBN1# DSTBN3# AY40 H_DSTBN#3 7


AG5 RSVD#AG5 7 H_DSTBP#1 W43 DSTBP1# DSTBP3# AY38 H_DSTBP#3 7
AL5 Layout Note: 1KR2F-3-GP R43 BC37
RSVD#AL5 7 H_DINV#1 DINV1# DINV3# H_DINV#3 7
J9 "CPU_GTLREF0" R152
RSVD#J9 0.5" max length. CPU_GTLREF0
F4 AW43 AE43 COMP0 R1581 2 27D4R2F-L1-GP

1 1
RSVD#F4 C422 TEST1 GTLREF COMP0
H8 RSVD#H8 E37 TEST1 MISC COMP1 AD44 COMP1 R1601 2 54D9R2F-L1-GP

1
DY TPAD14-GP TEST2 D40 AE1 COMP2 R1621 2 27D4R2F-L1-GP

SC1KP50V2KX-1GP
2 R153 TP63 RSVD_CPU_12 TEST2 COMP2 2
1 C43 TEST3 COMP3 AF2 COMP3 R1611 2 54D9R2F-L1-GP
2KR2F-3-GP TEST4 AE41

2
TPAD14-GP TP2 TEST4
1RSVD_CPU_13AY10 TEST5 DPRSTP# G7 H_DPRSTP# 8,13,34
TPAD14-GP TP50 1RSVD_CPU_14
AC43 B8 H_DPSLP# 13

2
TEST6 DPSLP#
DPWR# C41 H_DPW R# 7
PENRYN-SFF-GP-U1-NF 3,8 CPU_SEL0 A37 E7 H_PW RGD 13,32
BSEL0 PWRGOOD
3,8 CPU_SEL1 C37 BSEL1 SLP# D10 H_CPUSLP# 7
3,8 CPU_SEL2 B38 BD10 PSI# 1
BSEL2 PSI# TP3 TPAD14-GP

1
PENRYN-SFF-GP-U1-NF C117

SC100P50V2JN-3GP
DY

2
Layout Note:
1D05V_S0 1 DY 2 TEST1 Comp0, 2 connect with Zo=27.4 ohm, make
R185 1KR2J-1-GP trace length shorter than 0.5" .
Net "TEST4" as short as possible, Comp1, 3 connect with Zo=55 ohm, make
H_FERR# 1 2 1 DY 2 TEST2 trace length shorter than 0.5" .
H_STPCLK# C442 1DY 2 SC100P50V2JN-3GP XDP_TMS R140 1 2 51R2F-2-GP R173 1KR2J-1-GP make sure "TEST4" routing is
C425
H_IGNNE# C97 1DY 2 SC100P50V2JN-3GP reference to GND and away other
H_INTR C436 1DY 2 SC100P50V2JN-3GP XDP_TDI R141 1 2 51R2F-2-GP 2DY 1 TEST4
H_DPSLP# C439 1DY 2 SC100P50V2JN-3GP SCD1U10V2KX-4GP
noisy signals
H_PW RGD C437 1DY 2 SC100P50V2JN-3GP XDP_BPM#5 R143 1 2 51R2F-2-GP
H_A20M# C429 1DY 2 SC100P50V2JN-3GP
H_SMI# C435 1DY 2 SC100P50V2JN-3GP XDP_TDO R142 1 2 51R2F-2-GP
H_NMI C430 1DY 2 SC100P50V2JN-3GP DY
H_INIT# C431 1DY 2 SC100P50V2JN-3GP
C428 DY SC100P50V2JN-3GP
3D3V_S0 H_DPRSTP# 1 TP10 TPAD14-GP
1 DIS 1
H_DPSLP# 1 TP69 TPAD14-GP
H_DPW R# 1 TP62 TPAD14-GP
XDP_DBRESET# R37 2 1KR2J-1-GP H_PW RGD TP12 TPAD14-GP
1
H_CPUSLP#
1
1 TP68 TPAD14-GP Wistron Corporation
H_INIT# 1 TP13 TPAD14-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY H_CPURST# 1 TP9 TPAD14-GP Taipei Hsien 221, Taiwan, R.O.C.
XDP_TCK R145 1 2 51R2F-2-GP
Place these TP on button-side, Title
XDP_TRST# R144 1 2 51R2F-2-GP
easy to measure. CPU (1 of 3)
All place within 2" to CPU Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 4 of 48
A B C D E
A B C D E

VCC_CORE

VCC_CORE CPU1D 4 OF 6
4 B42 VSS VSS AU35 4
F44 VSS VSS AV34
CPU1C 3 OF 6 D42 AW35
VSS VSS
F32 VCC VCC AB28 F42 VSS VSS AW33
G33 VCC VCC AD30 H42 VSS VSS AY34
H32 VCC VCC AD28 K42 VSS VSS AT36
J33 VCC VCC Y26 M42 VSS VSS AV36
K32 VCC VCC AB26 P42 VSS VSS BA33
L33 VCC VCC AD26 T42 VSS VSS BC33
M32 VCC VCC AF30 V42 VSS VSS BB36
N33 VCC VCC AF28 Y42 VSS VSS BD36
P32 VCC VCC AH30 AB42 VSS VSS C27
R33 VCC VCC AH28 AD42 VSS VSS C29
T32 VCC VCC AF26 AF42 VSS VSS C31
U33 VCC VCC AH26 AH42 VSS VSS E29
V32 VCC VCC AK30 AK42 VSS VSS E27
W33 VCC VCC AK28 AM42 VSS VSS G29
Y32 VCC VCC AM30 AP42 VSS VSS G27

www.kythuatvitinh.com
AA33 VCC VCC AM28 AV44 VSS VSS E31
AB32 VCC VCC AP30 AT42 VSS VSS G31
AC33 VCC VCC AP28 AV42 VSS VSS J29
AD32 VCC VCC AK26 AY42 VSS VSS J27
AE33 VCC VCC AM26 BA43 VSS VSS L29
AF32 VCC VCC AP26 BB42 VSS VSS L27
AG33 VCC VCC AT30 C39 VSS VSS N29
AH32 VCC VCC AT28 E39 VSS VSS N27
AJ33 VCC VCC AV30 G37 VSS VSS J31
AK32 VCC VCC AV28 H38 VSS VSS L31
AL33 VCC VCC AY30 J39 VSS VSS N31
3 AM32 AY28 L39 R29 3
VCC VCC VSS VSS
AN33 VCC VCC AT26 M38 VSS VSS R27
AP32 VCC VCC AV26 N39 VSS VSS U29
AR33 VCC VCC AY26 R39 VSS VSS U27
AT34 VCC VCC BB30 T38 VSS VSS R31
AT32 VCC VCC BB28 U39 VSS VSS U31
AU33 BD30 1D05V_S0 W39 W29
VCC VCC VSS VSS
AV32 VCC Y38 VSS VSS W27
AY32 VCC VCCP J11 AA39 VSS VSS W31
BB32 VCC VCCP E11 layout note: "1D5V_VCCA_S0" AC39 VSS VSS AA29
BD32 VCC VCCP G11 as short as possible AD38 VSS VSS AA27
B28 VCC VCCP J37 AE39 VSS VSS AC29
B30 VCC VCCP K38 AG39 VSS VSS AC27
1

B26 L37 C36 C47 AH38 AA31


VCC VCCP VSS VSS
1

1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

D28 N37 TC7 AJ39 AC31


VCC VCCP SE330U2D5VM-GP VSS VSS
D30 P38 AL39 AE29
2

VCC VCCP P_77.C3371.10L VSS VSS


F30 R37 AM38 AE27
2

VCC VCCP VSS VSS


F28 VCC VCCP U37 DY AN39 VSS VSS AG29
H30 VCC VCCP V38 AR39 VSS VSS AG27
H28 VCC VCCP W37 AR37 VSS VSS AJ29
D26 VCC VCCP AA37 AT38 VSS VSS AJ27
F26 VCC VCCP AB38 AU39 VSS VSS AE31
H26 AC37 1D5V_S0 AU37 AG31
VCC VCCP 1D5V_VCCA_S0 VSS VSS
K30 VCC VCCP AE37 R186 AW39 VSS VSS AJ31
K28 VCC AW37 VSS VSS AL29
M30 VCC VCCA B34 1 2 BA39 VSS VSS AL27
M28 VCC VCCA D34 BC41 VSS VSS AN29
1

K26 H_VID[6..0] 34 C453 C455 BD38 AN27


VCC H_VID0 0R0603-PAD VSS VSS
M26 BD8 B36 AL31
SC10U6D3V5MX-3GP
SCD01U16V2KX-3GP

2 VCC VID0 H_VID1 VSS VSS 2


P30 BC7 H34 AN31
2

VCC VID1 H_VID2 VSS VSS


P28 VCC VID2 BB10 D36 VSS VSS AR29
T30 BB8 H_VID3 K34 AR27
VCC VID3 H_VID4 VSS VSS
T28 VCC VID4 BC5 M34 VSS VSS AR31
V30 BB4 H_VID5 M36 AU29
VCC VID5 H_VID6 VSS VSS
V28 VCC VID6 AY4 P34 VSS VSS AU27
P26 VCC T34 VSS VSS AW29
T26 VCC V34 VSS VSS AW27
V26 VCC VCCSENSE BD12 VCORE_VCCSENSE 34 T36 VSS VSS AU31
Y30 VCC Y34 VSS VSS AW31
Y28 VCC AB34 VSS VSS BA29
AB30 VCC VSSSENSE BC13 VCORE_VSSSENSE 34 AD34 VSS VSS BA27
Y36 VSS VSS BC29
PENRYN-SFF-GP-U1-NF Layout Note: AD36 BC27
RN13 VSS VSS
AF34 VSS VSS BA31
2 3 VCCSENSE and VSSSENSE lines AH34 BC31
VCC_CORE VSS VSS
1 4 should be of equal length. AH36 C21
VSS VSS
AK34 VSS VSS C23
SRN100J-3-GP AM34 C25
Layout Note: VSS VSS
AM36 VSS VSS E25
Provide a test point (with AP34 E23
no stub) to connect a VSS VSS
AR35 VSS VSS E21
differential probe
between VCCSENSE and
VSSSENSE at the location PENRYN-SFF-GP-U1-NF
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (2 of 3)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 5 of 48
A B C D E
5 4 3 2 1

VCC_CORE 1D05V_S0
CPU1E 5 OF 6 6 OF 6
Place these inside socket CPU1F
cavity on L8(North side Secondary) G25 AD10 BD28 AL37
VSS VSS VCC VCCP
G23 AH12 BB26 AN37
VSS VSS VCC VCCP
G21 AE15 BD26 AP38
VCC_CORE VCC_CORE VSS VSS VCC VCCP
J25 AG15 B22 B32
VSS VSS VCC VCCP
J23 AJ15 B24 C33
VSS VSS VCC VCCP
J21 AH10 D22 D32
VSS VSS VCC VCCP
D L25 AM12 D24 E35 D
VSS VSS VCC VCCP
L23 AL15 F24 E33
1

1
C410 C1S C5S C8S C409 C7S C25 C6S C19 C412 C32 C38 C46 C37 C29 C51 VSS VSS VCC VCCP
L21 AN15 F22 F34
VSS VSS VCC VCCP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
N25 AR15 H24 G35
C10U6D3V3MX-GP

C10U6D3V3MX-GP

C10U6D3V3MX-GP

C10U6D3V3MX-GP

C10U6D3V3MX-GP
VSS VSS VCC VCCP
N23 AM10 H22 F36
2

2
VSS VSS VCC VCCP
N21 AT12 K24 H36
VSS VSS VCC VCCP
R25 AV12 K22 J35
VSS VSS VCC VCCP
R23 AW13 M24 L35
VSS VSS VCC VCCP
R21 AW11 M22 N35
VSS VSS VCC VCCP
U25 AY12 P24 K36
VSS VSS VCC VCCP
U23 AU15 P22 R35
VSS VSS VCC VCCP
U21 AW15 T24 U35
VSS VSS VCC VCCP
W25 AT10 T22 P36
VSS VSS VCC VCCP
W23 BA13 V24 V36
VSS VSS VCC VCCP
W21 BA11 V22 W35
VSS VSS VCC VCCP
AA25 BB12 Y24 AA35
VCC_CORE VCC_CORE VSS VSS VCC VCCP
AA23 BC11 Y22 AC35
VSS VSS VCC VCCP
AA21 BA15 AB24 AB36
VSS VSS VCC VCCP
AC25 BC15 AB22 AE35
VSS VSS VCC VCCP
AC23 B6 AD24 AG35
VSS VSS VCC VCCP
AC21 D6 AD22 AJ35
1

1
C59 C53 C42 C4 C27 C23 C24 C66 C43 C48 C3 C34 C413 C411 C40 C2 VSS VSS VCC VCCP
AE25 E9 AF24 AF36
VSS VSS VCC VCCP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
AE23 F6 AF22 AL35
VSS VSS VCC VCCP
AE21 G9 AH24 AN35
2

2
VSS VSS VCC VCCP
AG25 H6 AH22 AK36
VSS VSS VCC VCCP
AG23 K8 AK24 AP36
VSS VSS VCC VCCP

www.kythuatvitinh.com
AG21 K6 AK22 B12
VSS VSS VCC VCCP
AJ25 M8 AM24 B14
VSS VSS VCC VCCP
AJ23 M6 AM22 C13
VSS VSS VCC VCCP
AJ21 P8 AP24 D12
VSS VSS VCC VCCP
AL25 P6 AP22 D14
VSS VSS VCC VCCP
AL23 T8 AT24 E13
VSS VSS VCC VCCP
AL21 T6 AT22 F14
VCC_CORE VCC_CORE VSS VSS VCC VCCP
AN25 V8 AV24 F12
VSS VSS VCC VCCP
AN23 V6 AV22 G13
VSS VSS VCC VCCP
AN21 U5 AY24 H14
VSS VSS VCC VCCP
AR25 Y8 AY22 H12
VSS VSS VCC VCCP
AR23 Y6 BB24 J13
1

1
C77 C91 C84 C102 C104 C112 C101 C83 C64 C58 C54 C45 C41 C100 C103 C107 VSS VSS VCC VCCP
AR21 AB8 BB22 K14
VSS VSS VCC VCCP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AU25 AB6 BD24 K12
VSS VSS VCC VCCP
AU23 AD8 BD22 L13
2

2
VSS VSS VCC VCCP
C AU21 AD6 B16 L11 C
VSS VSS VCC VCCP
AW25 AF8 B18 M14
VSS VSS VCC VCCP
AW23 AF6 B20 N13
VSS VSS VCC VCCP
AW21 AH8 D16 N11
VSS VSS VCC VCCP
BA25 AH6 D18 K10
VSS VSS VCC VCCP
BA23 AK8 F18 P14
VSS VSS VCC VCCP
BA21 AK6 F16 P12
VSS VSS VCC VCCP
BC25 AM8 H18 R13
VSS VSS VCC VCCP
BC23 AM6 H16 R11
VCC_CORE VCC_CORE VSS VSS VCC VCCP
BC21 AP8 D20 T14
VSS VSS VCC VCCP
C17 AP6 F20 U13
VSS VSS VCC VCCP
C19 AT8 H20 U11
VSS VSS VCC VCCP
E19 AT6 K18 V14
VSS VSS VCC VCCP
E17 AU9 K16 V12
1

1
C80 C72 C67 C60 C74 C79 C71 C85 C76 C69 C115 C56 C52 C33 C114 C99 VSS VSS VCC VCCP
G19 AV6 M18 W13
VSS VSS VCC VCCP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP G17
VSS VSS
AU7 M16
VCC VCCP
W11
J19 AW9 K20 P10
2

VSS VSS VCC VCCP


J17 AY6 M20 V10
VSS VSS VCC VCCP
L19 BA9 P18 Y14
VSS VSS VCC VCCP
L17 BB6 P16 AA13
VSS VSS VCC VCCP
N19 BC9 T18 AA11
VSS VSS VCC VCCP
N17 BD6 T16 AB14
VSS VSS VCC VCCP
R19 B4 V18 AB12
VSS VSS VCC VCCP
R17 C3 V16 AC13
VSS VSS VCC VCCP
U19 E3 P20 AC11
VSS VSS VCC VCCP
U17 G3 T20 AD14
VSS VSS VCC VCCP
Place these inside socket W19
VSS VSS
J3 V20
VCC VCCP
AB10
cavity on L8(North side Secondary) W17 L3 Y18 AE13
VSS VSS VCC VCCP
AA19 N3 Y16 AE11
VSS VSS VCC VCCP
AA17 R3 AB18 AF14
VSS VSS VCC VCCP
AC19 U3 AB16 AF12
1D05V_S0 VSS VSS VCC VCCP
AC17 W3 AD18 AG13
VSS VSS VCC VCCP
AE19 AA3 AD16 AG11
VSS VSS VCC VCCP
AE17 AC3 Y20 AH14
VSS VSS VCC VCCP
AG19 AE3 AB20 AJ13
VSS VSS VCC VCCP
AG17 AG3 AD20 AJ11
VSS VSS VCC VCCP
AJ19 AJ3 AF18 AF10
1

C82 C63 C113 C81 C50 C57 VSS VSS VCC VCCP
AJ17 AL3 AF16 AK14
VSS VSS VCC VCCP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

AL19 AN3 AH18 AK12


VSS VSS VCC VCCP
AL17 AR3 AH16 AL13
2

VSS VSS VCC VCCP


AN19 AU3 AF20 AL11
B VSS VSS VCC VCCP B
AN17 AW3 AH20 AN13
VSS VSS VCC VCCP
AR19 BA3 AK18 AN11
VSS VSS VCC VCCP
AR17 BC3 AK16 AP12
VSS VSS VCC VCCP
AU19 D2 AM18 AR13
VSS VSS VCC VCCP
AU17 G1 AM16 AR11
VSS VSS VCC VCCP
AW19 AW1 AP18 AK10
VSS VSS VCC VCCP
AW17 BB2 AP16 AP10
VSS VSS VCC VCCP
BA19 A39 AK20 AU13
VSS VSS VCC VCCP
BA17 A29 AM20 AU11
VSS VSS VCC VCCP
BC19 A27 AP20 L9
VSS VSS VCC VCCP
BC17 A31 AT18 L7
VSS VSS VCC VCCP
C11 A25 AT16 N9
VSS VSS VCC VCCP
C15 A23 AV18 N7
VSS VSS VCC VCCP
E15 A21 AV16 R9
VSS VSS VCC VCCP
G15 A19 AY18 R7
VSS VSS VCC VCCP
H10 A17 AY16 U9
VSS VSS VCC VCCP
M12 A11 AT20 U7
VSS VSS VCC VCCP
J15 A15 AV20 W9
VSS VSS VCC VCCP
L15 A7 AY20 W7
VSS VSS VCC VCCP
N15 A9 BB18 AA9
VSS VSS VCC VCCP
M10 BB16 AA7
VSS VCC VCCP
T12 BD18 AC9
VSS NCTF_VSS#A5 TP71 TPAD14-GP VCC VCCP
R15 A5 1 BD16 AC7
VSS NCTF_VSS#A5 VCC VCCP
U15 A41 NCTF_VSS#A41 1 TP61 TPAD14-GP BB20 AE9
VSS NCTF_VSS#A41 VCC VCCP
W15 AY44 NCTF_VSS#AY44 1 TP49 TPAD14-GP BD20 AE7
VSS NCTF_VSS#AY44 VCC VCCP
T10 BA1 NCTF_VSS#BA1 1 TP47 TPAD14-GP AM14 AG9
VSS NCTF_VSS#BA1 VCC VCCP
Y10 BD4 NCTF_VSS#BD4 1 TP46 TPAD14-GP AP14 AG7

A5,A41,AY44,BA1,BD4,BD40,D44,E1
VSS NCTF_VSS#BD4 VCC VCCP
Y12 BD40 NCTF_VSS#BD40 1 TP48 TPAD14-GP AT14 AJ9
VSS NCTF_VSS#BD40 VCC VCCP
AA15 D44 NCTF_VSS#D44 1 TP55 TPAD14-GP AV14 AJ7
VSS NCTF_VSS#D44 NCTF_VSS#E1 TP51 TPAD14-GP VCC VCCP
AC15 E1 1 AY14 AL9
VSS NCTF_VSS#E1 VCC VCCP
AD12 BB14 AL7
VSS VCC VCCP
BD14 AN9
1D05V_S0 VCC VCCP
AN7
PENRYN-SFF-GP-U1-NF VCCP
AF38 AR9
VCCP VCCP
AG37 AR7

NCTF TEST PIN:


VCCP VCCP
AJ37 A33
VCCP VCCP
AK38 A13
VCCP VCCP

PENRYN-SFF-GP-U1-NF
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (3 of 3)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 6 of 48
5 4 3 2 1
5 4 3 2 1

NB1A 1 OF 10 H_A#[35..3]
H_A#[35..3] 4
H_D#[63..0] L15 H_A#3
4 H_D#[63..0] H_A#_3
H_D#0 J7 B14 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
H6 H_D#_1 H_A#_5 C15
H_D#2 L11 D12 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
J3 H_D#_3 H_A#_7 F14
1D05V_S0 H_D#4 H4 G17 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
D H_SWING routing Trace width and G3 H_D#_5 H_A#_9 B12 D
H_D#6 K10 J15 H_A#10
Spacing use 10 / 20 mil H_D#_6 H_A#_10

1
H_D#7 K12 D16 H_A#11
R196 H_D#8 H_D#_7 H_A#_11 H_A#12
L1 H_D#_8 H_A#_12 C17
221R2F-2-GP H_D#9 M10 D14 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
H_SWING Resistors and M6 H_D#_10 H_A#_14 K16
H_D#11 N11 F16 H_A#15
Capacitors close MCH

2
H_D#12 H_D#_11 H_A#_15 H_A#16
L7 H_D#_12 H_A#_16 B16
500 mil ( MAX ) H_SW ING H_D#13 K6 H_D#_13 H_A#_17 C21 H_A#17
H_D#14 M4 D18 H_A#18
H_D#_14 H_A#_18

1
H_D#15 K4 J19 H_A#19

SCD1U10V2KX-4GP
H_D#_15 H_A#_19
1

C499
R194 H_D#16 P6 J21 H_A#20
100R2F-L1-GP-U H_D#17 H_D#_16 H_A#_20 H_A#21
W9 H_D#_17 H_A#_21 B18
H_D#18 V6 D22 H_A#22
2

H_D#19 H_D#_18 H_A#_22 H_A#23


V2 G19

2
H_D#20 H_D#_19 H_A#_23 H_A#24
P10 H_D#_20 H_A#_24 J17
H_D#21 W7 L21 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
N9 H_D#_22 H_A#_26 L19

www.kythuatvitinh.com
H_D#23 P4 G21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
U9 H_D#_24 H_A#_28 D20
H_D#25 V4 K22 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
U1 H_D#_26 H_A#_30 F18
H_D#27 W3 K20 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
V10 H_D#_28 H_A#_32 F20
H_D#29 U7 F22 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
W11 H_D#_30 H_A#_34 B20
H_D#31 U11 A19 H_A#35
H_D#32 H_D#_31 H_A#_35
AC11 H_D#_32
H_D#33 AC9 F10 H_ADS# 4
C H_D#34 H_D#_33 H_ADS# C
Y4 A15

HOST
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4
H_D#35 Y10 C19 H_ADSTB#1 4
H_D#36 H_D#_35 H_ADSTB#_1
AB6 H_D#_36 H_BNR# C9 H_BNR# 4
H_D#37 AA9 B8 H_BPRI# 4
H_D#38 H_D#_37 H_BPRI#
AB10 H_D#_38 H_BREQ# C11 H_BREQ#0 4
H_D#39 AA1 E5 H_DEFER# 4
H_D#40 H_D#_39 H_DEFER#
AC3 H_D#_40 H_DBSY# D6 H_DBSY# 4
H_D#41 AC7 AH10 CLK_MCH_BCLK 3
H_D#42 H_D#_41 HPLL_CLK
AD12 H_D#_42 HPLL_CLK# AJ11 CLK_MCH_BCLK# 3
H_D#43 AB4 G11 H_DPW R# 4
H_D#44 H_D#_43 H_DPWR#
Y6 H_D#_44 H_DRDY# H2 H_DRDY# 4
H_RCOMP routing Trace width and H_D#45 AD10 C7 H_HIT# 4
H_D#46 H_D#_45 H_HIT#
AA11 F8 H_HITM# 4
Spacing use 10 / 20 mil H_D#47 AB2
H_D#_46 H_HITM#
A11
H_D#_47 H_LOCK# H_LOCK# 4
H_D#48 AD4 D8 H_TRDY# 4
H_D#49 H_D#_48 H_TRDY#
AE7 H_D#_49
1 2 H_RCOMP H_D#50 AD2 H_D#_50
R190 24D9R2F-L-GP H_D#51 AD6
H_D#52 H_D#_51 H_DINV#[3..0]
AE3 H_D#_52 H_DINV#[3..0] 4
H_D#53 AG9 L9 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AG7 H_D#_54 H_DINV#_1 N7
H_D#55 AE11 AA7 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
Place them near to the chip ( < 0.5") H_D#57
AK6
AF6
H_D#_56 H_DINV#_3 AG3
H_DSTBN#[3..0]
H_D#_57 H_DSTBN#[3..0] 4
H_D#58 AJ9 K2 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN_0 H_DSTBN#1
AH6 H_D#_59 H_DSTBN_1 N3
H_D#60 AF12 AA3 H_DSTBN#2
H_D#61 H_D#_60 H_DSTBN_2 H_DSTBN#3
AH4 H_D#_61 H_DSTBN_3 AF4
H_D#62 AJ7 H_DSTBP#[3..0]
B H_D#_62 H_DSTBP#[3..0] 4 B
H_D#63 AE9 L3 H_DSTBP#0
H_D#_63 H_DSTBP_0 H_DSTBP#1
H_DSTBP_1 M2
Y2 H_DSTBP#2
H_SW ING H_DSTBP_2 H_DSTBP#3
B6 H_SWING H_DSTBP_3 AF2
H_RCOMP D4 H_REQ#[4..0] 4
H_RCOMP H_REQ#0
H_REQ#_0 J13
1D05V_S0 L13 H_REQ#1
H_REQ#_1 H_REQ#2
H_REQ#_2 C13
G13 H_REQ#3
H_REQ#_3
2

4 H_CPURST# J11 G15 H_REQ#4


R48 H_CPURST# H_REQ#_4
4 H_CPUSLP# G9 H_CPUSLP# H_RS#[2..0] 4
1KR2F-3-GP F4 H_RS#0
H_RS#_0 H_RS#1
H_RS#_1 F2
G7 H_RS#2
1

H_AVREF H_RS#_2
L17 H_AVREF
K18 H_DVREF
CANTIGA-GS-GP-NF
1

1
SC1KP50V2KX-1GP

R49 C169
2KR2F-3-GP
2
2

A DIS A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (1 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 7 of 48
5 4 3 2 1
5 4 3 2 1

NB1C 3 OF 10
NB1B 2 OF 10
1D05V_S0
J43
RSVD#J43
L43 BB32 D38
J41
RSVD#L43
RSVD#J41
SA_CK_0
SA_CK_1
BA25
M_CLK_DDR0
M_CLK_DDR1
18
18
19 GMCH_L_BKLTCTL
19 GMCH_BL_ON C37
L_BKLT_CTRL
L_BKLT_EN PEG_COMPI
U45 PEG_CMP 2 1
Close to GMCH as 500 mils.
L41 BA33 LCTLA_CLK K38 T44 R53 49D9R2F-GP
RSVD#L41 SB_CK_0 M_CLK_DDR2 17 L_CTRL_CLK PEG_COMPO

DDR CLK/ CONTROL/COMPENSATION


AN11 BA23 M_CLK_DDR3 17
RSVD#AN11 SB_CK_1 LCTLB_DATA
AM10 L37
RSVD#AM10 L_CTRL_DATA
AK10 BA31 M_CLK_DDR#0 18 41 GMCH_CLK_DDC_EDID J37 D52 PEG_RXN0 42
RSVD#AK10 SA_CK#_0 L_DDC_CLK PEG_RX#_0
AL11 BC25 M_CLK_DDR#1 18 41 GMCH_DAT_DDC_EDID L35 G49 PEG_RXN1 42
RSVD#AL11 SA_CK#_1 L_DDC_DATA PEG_RX#_1
F12 BC33 M_CLK_DDR#2 17 K54 PEG_RXN2 42
RSVD#F12 SB_CK#_0 PEG_RX#_2

RSVD
1D5V_S3 AN45 BB24 H50
RSVD#AN45 SB_CK#_1 M_CLK_DDR#3 17 PEG_RX#_3 PEG_RXN3 42
R218 1KR2F-3-GP AP44 19 GMCH_LCDVDD_ON GMCH_LCDVDD_ON B36 M52 PEG_RXN4 42
RSVD#AP44 LIBG L_VDD_EN PEG_RX#_4
2 1 AT44 BC35 M_CKE0 18 F50 N49 PEG_RXN5 42
RSVD#AT44 SA_CKE_0 LVDS_IBG PEG_RX#_5
AN47 BE33 M_CKE1 18 TPAD14-GP TP26 1 L_LVBG H46 P54 PEG_RXN6 42
SM_RCOMP_VOH RSVD#AN47 SA_CKE_1 LVDS_VBG PEG_RX#_6
C27 BE37 M_CKE2 17 P44 V46 PEG_RXN7 42
RSVD#C27 SB_CKE_0 LVDS_VREFH PEG_RX#_7

LVDS
D D30 BC37 M_CKE3 17 K46 Y50 PEG_RXN8 42 D
1

1
C513 C514 RSVD#D30 SB_CKE_1 LVDS_VREFL PEG_RX#_8
41 GMCH_TXACLK- D46 V52 PEG_RXN9 42
R216 LVDSA_CLK# PEG_RX#_9
J9 BK18 M_CS0# 18 41 GMCH_TXACLK+ B46 W49 PEG_RXN10 42
3K01R2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP RSVD#J9 SA_CS#_0 LVDSA_CLK PEG_RX#_10
BK16 M_CS1# 18 D44 AB54 PEG_RXN11 42

2
SA_CS#_1 LVDSB_CLK# PEG_RX#_11
BE23 M_CS2# 17 B44 AD46 PEG_RXN12 42
SB_CS#_0 LVDSB_CLK PEG_RX#_12
AW42 BC19 M_CS3# 17 AC55 PEG_RXN13 42
2

SM_RCOMP_VOL RSVD#AW42 SB_CS#_1 PEG_RX#_13


41 GMCH_TXAOUT0- G45 AE49 PEG_RXN14 42
LVDSA_DATA#_0 PEG_RX#_14
BJ17 M_ODT0 18 41 GMCH_TXAOUT1- F46 AF54 PEG_RXN15 42
2

1
SA_ODT_0 LVDSA_DATA#_1 PEG_RX#_15

GRAPHICS
C511 C510 BJ19 M_ODT1 18 41 GMCH_TXAOUT2- G41
R214 SA_ODT_1 LVDSA_DATA#_2
BB20 BC17 M_ODT2 17 C45 E51 PEG_RXP0 42
1KR2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP RSVD#BB20 SB_ODT_0 LVDSA_DATA#_3 PEG_RX_0
BE19 BE17 M_ODT3 17 F48 PEG_RXP1 42
2

2
RSVD#BE19 SB_ODT_1 PEG_RX_1
BF20 41 GMCH_TXAOUT0+ F44 J55 PEG_RXP2 42
RSVD#BF20 M_RCOMPP LVDSA_DATA_0 PEG_RX_2
BF18 BL25 41 GMCH_TXAOUT1+ G47 J49 PEG_RXP3 42
1

RSVD#BF18 SM_RCOMP M_RCOMPN LVDSA_DATA_1 PEG_RX_3


BK26 SM_PWROK 32 41 GMCH_TXAOUT2+ F40 M54 PEG_RXP4 42
SM_RCOMP# LVDSA_DATA_2 PEG_RX_4
A45 M50 PEG_RXP5 42
SM_RCOMP_VOH LVDSA_DATA_3 PEG_RX_5
BK32 P52 PEG_RXP6 42
SM_RCOMP_VOH SM_RCOMP_VOL DDR_VREF_S3_1 PEG_RX_6
BL31 B40 U47 PEG_RXP7 42
SM_RCOMP_VOL LVDSB_DATA#_0 PEG_RX_7
layout take note 0.75V A41
LVDSB_DATA#_1 PEG_RX_8
AA49 PEG_RXP8 42
BC51 F42 V54 PEG_RXP9 42
SM_VREF DDR2 : connect to GND LVDSB_DATA#_2 PEG_RX_9
AY37 D48 V50 PEG_RXP10 42
SM_PWROK SM_REXT R2041 499R2F-2-GP LVDSB_DATA#_3 PEG_RX_10
BH20 2 AB52 PEG_RXP11 42

1
SM_REXT C238 RN8 PEG_RX_11
BA37 DDR3_DRAMRST# 17,18 D40 AC47 PEG_RXP12 42
SM_DRAMRST# LVDSB_DATA_0 PEG_RX_12

SCD1U10V2KX-4GP
DREFCLK 4 5 C41 AC53

PCI-EXPRESS
LVDSB_DATA_1 PEG_RX_13 PEG_RXP13 42
B42 DREFCLK# 3 6 G43 AD50 PEG_RXP14 42

2
DPLL_REF_CLK DREFCLK 3 DREFSSCLK LVDSB_DATA_2 PEG_RX_14
D42 2 7 B48 AF52 PEG_RXP15 42
DPLL_REF_CLK# DREFCLK# 3 DREFSSCLK# LVDSB_DATA_3 PEG_RX_15
B50 1 8
DPLL_REF_SSCLK DREFSSCLK 3

www.kythuatvitinh.com
D50 L47 M_TXN0 C535 1 2 SCD1U6D3V1KX-GP PEG_TXN0 42
DPLL_REF_SSCLK# DREFSSCLK# 3 PEG_TX#_0
SRN0J-7-GP F52 M_TXN1 C539 1 2 SCD1U6D3V1KX-GP PEG_TXN1 42
TV_DACA PEG_TX#_1
R49 CLK_MCH_3GPLL 3 DY J27 P46 M_TXN2 C550 1 2 SCD1U6D3V1KX-GP PEG_TXN2 42
PEG_CLK TV_DACB TVA_DAC PEG_TX#_2
P50 CLK_MCH_3GPLL# 3 E27 H54 M_TXN3 C589 1 2 SCD1U6D3V1KX-GP PEG_TXN3 42
PEG_CLK# TVB_DAC PEG_TX#_3

TV
TV_DACC G27 L55 M_TXN4 C577 1 2 SCD1U6D3V1KX-GP
SB TVC_DAC PEG_TX#_4
PEG_TX#_5
T46 M_TXN5 C575 1 2 SCD1U6D3V1KX-GP
PEG_TXN4 42
PEG_TXN5 42
R53 M_TXN6 C573

CLK
F26 1 2 SCD1U6D3V1KX-GP PEG_TXN6 42
TVA_RTN PEG_TX#_6
AG55 U49 M_TXN7 C571 1 2 SCD1U6D3V1KX-GP PEG_TXN7 42
DMI_RXN_0 DMI_TXN0 14 PEG_TX#_7
AL49 T54 M_TXN8 C569 1 2 SCD1U6D3V1KX-GP PEG_TXN8 42
DMI_RXN_1 DMI_TXN1 14 PEG_TX#_8
AH54 Y46 M_TXN9 C567 1 2 SCD1U6D3V1KX-GP PEG_TXN9 42
DMI_RXN_2 DMI_TXN2 14 PEG_TX#_9
AL47 B34 AB46 M_TXN10C565 1 2 SCD1U6D3V1KX-GP PEG_TXN10 42
DMI_RXN_3 DMI_TXN3 14 TV_DCONSEL_0 PEG_TX#_10
D34 W53 M_TXN11C563 1 2 SCD1U6D3V1KX-GP PEG_TXN11 42
TV_DCONSEL_1 PEG_TX#_11
AG53 Y54 M_TXN12C561 1 2 SCD1U6D3V1KX-GP PEG_TXN12 42
DMI_RXP_0 DMI_TXP0 14 PEG_TX#_12
3,4 CPU_SEL0 K26 AK50 AC49 M_TXN13C559 1 2 SCD1U6D3V1KX-GP PEG_TXN13 42
CFG_0 DMI_RXP_1 DMI_TXP1 14 PEG_TX#_13
3,4 CPU_SEL1 G23 AH52 AF46 M_TXN14C557 1 2 SCD1U6D3V1KX-GP PEG_TXN14 42
CFG_1 DMI_RXP_2 DMI_TXP2 14 PEG_TX#_14
C
3,4 CPU_SEL2 G25 AL45 AD54 M_TXN15C555 1 2 SCD1U6D3V1KX-GP PEG_TXN15 42 C
CFG_2 DMI_RXP_3 DMI_TXP3 14 PEG_TX#_15
J25
CFG_3 GMCH_BLUE
3D3V_S0 L25 AG49 41 GMCH_BLUE J29 J47 M_TXP0 C530 1 2 SCD1U6D3V1KX-GP PEG_TXP0 42
CFG_4 DMI_TXN_0 DMI_RXN0 14 CRT_BLUE PEG_TX_0
L27 AJ49 F54 M_TXP1 C536 1 2 SCD1U6D3V1KX-GP PEG_TXP1 42
CFG_5 DMI_TXN_1 DMI_RXN1 14 GMCH_GREEN PEG_TX_1
F24 AJ47 41 GMCH_GREEN G29 N47 M_TXP2 C543 1 2 SCD1U6D3V1KX-GP PEG_TXP2 42
CFG_6 DMI_TXN_2 DMI_RXN2 14 CRT_GREEN PEG_TX_2
D24 AG47 H52 M_TXP3 C584 1 2 SCD1U6D3V1KX-GP PEG_TXP3 42
CFG_7 DMI_TXN_3 DMI_RXN3 14 PEG_TX_3

VGA
D26 GMCH_RED F30 L53 M_TXP4 C578 1 2 SCD1U6D3V1KX-GP
CFG_8 41 GMCH_RED CRT_RED PEG_TX_4 PEG_TXP4 42

CFG
CFG9 J23 AF50 R47 M_TXP5 C576 1 2 SCD1U6D3V1KX-GP
CFG_9 DMI_TXP_0 DMI_RXP0 14 PEG_TX_5 PEG_TXP5 42
R51 1 DY 2 4K02R2F-GP CFG20 B26 AH50 E29 R55 M_TXP6 C574 1 2 SCD1U6D3V1KX-GP PEG_TXP6 42
CFG_10 DMI_TXP_1 DMI_RXP1 14 CRT_IRTN PEG_TX_6
A23 AJ45 T50 M_TXP7 C572 1 2 SCD1U6D3V1KX-GP PEG_TXP7 42
CFG_11 DMI_TXP_2 DMI_RXP2 14 PEG_TX_7

GRAPHICS VID DMI


C23 AG45 GMCH_DDCCLK D36 T52 M_TXP8 C570 1 2 SCD1U6D3V1KX-GP
CFG_12 DMI_TXP_3 DMI_RXP3 14 20 GMCH_DDCCLK CRT_DDC_CLK PEG_TX_8 PEG_TXP8 42
B24 GMCH_DDCDATA C35 W47 M_TXP9 C568 1 2 SCD1U6D3V1KX-GP
CFG_13 20 GMCH_DDCDATA CRT_DDC_DATA PEG_TX_9 PEG_TXP9 42
R50 1 DY 2 2K21R2F-GP CFG9 B22 J33 AA47 M_TXP10C566 1 2 SCD1U6D3V1KX-GP
CFG_14 CRT_HSYNC PEG_TX_10 PEG_TXP10 42
K24 20 GMCH_HSYNC D32 W55 M_TXP11C564 1 2 SCD1U6D3V1KX-GP PEG_TXP11 42
CFG_15 CRT_TVO_IREF PEG_TX_11
TPAD14-GP TP77 1 CFG16 C25 20 GMCH_VSYNC G31 Y52 M_TXP12C562 1 2 SCD1U6D3V1KX-GP PEG_TXP12 42
CFG_16 CRT_VSYNC PEG_TX_12
L23 AB50 M_TXP13C560 1 2 SCD1U6D3V1KX-GP PEG_TXP13 42
CFG_17 PEG_TX_13
L33 AE47 M_TXP14C558 1 2 SCD1U6D3V1KX-GP PEG_TXP14 42
CFG_18 PEG_TX_14
K32 AD52 M_TXP15C556 1 2 SCD1U6D3V1KX-GP PEG_TXP15 42
CFG20 CFG_19 GFX_VID0 PEG_TX_15
K34 G33
1D5V_S3 CFG_20 GFX_VID_0 GFX_VID1 CRT_IREF
G37 1 2
GFX_VID_1 GFX_VID2 R211 976R2F-3-GP CANTIGA-GS-GP-NF
GFX_VID_2
F38
GFX_VID3
0201 CAPs
F36
GFX_VID_3 GFX_VID4
14 PM_SYNC# J35 G35 GFX_VID[4..0] 38
1

PM_SYNC# GFX_VID_4
4,13,34 H_DPRSTP# F6
PM_EXTTS#0 PM_DPRSTP#
R206 17,18 PM_EXTTS#0 J39 FOR Cantiga: 1.02k_1% ohm
PM_EXT_TS#_0
PM

80D6R2F-L-GP PM_EXTTS#1 L39 Teenah: 1.3k ohm


PM_EXT_TS#_1 GFXVR_EN
14,32 PWROK AY39 G39
PLT_RST1#_Cantiga PWROK GFX_VR_EN GFXVR_EN 38 1D05V_S0
BB18 CRT_IREF routing Trace
2

M_RCOMPP PM_THRMTRIP-A#_R RSTIN#


K28
width use 20 mil

2
THERMTRIP#
14,22,24,25,28,29,42 PLT_RST1# 2 1R47 K36
100R2J-2-GP DPRSLPVR R243
M_RCOMPN AK52 1KR2F-3-GP
CL_CLK0 14
1

C164 CL_CLK
AK54 CL_DATA0 14
1

SC100P50V2JN-3GP CL_DATA
A7 AW40 PWROK 14,32

1
NC#A7 CL_PWROK
ME

R207 DY A49 AL53


2

NC#A49 CL_RST# MCH_CLVREF CL_RST#0 14


80D6R2F-L-GP A52 AL55
NC#A52 CL_VREF SRN100KJ-6-GP
R208 A54

1
NC#A54 GMCH_BL_ON
B54 2 3
2

1
NC#B54 C583 R244 GMCH_LCDVDD_ON
4,13,32 PM_THRMTRIP-A# 1 2 D55 1 4
NC#D55 511R2F-2-GP
G55 F34

SCD1U10V2KX-4GP
NC#G55 DDPC_CTRLCLK RN26
NC

14,34 PM_DPRSLPVR 0R0402-PAD BE55 F32

2
B NC#BE55 DDPC_CTRLDATA SDVO_CLK B
BH55 B38

2
NC#BH55 SDVO_CTRLCLK SDVO_DAT
BK55 A37
MISC

NC#BK55 SDVO_CTRLDATA
BK54 C31 CLK_MCH_OE# 3
NC#BK54 CLKREQ#
BL54 K42 MCH_ICH_SYNC# 14
NC#BL54 ICH_SYNC# LIBG
BL52 FOR Cantiga:500 ohm 1 2
NC#BL52 R221 2K4R2F-GP
BL49 Teenah: 392 ohm
NC#BL49 MCH_TSATN#
BL7 D10
NC#BL7 TSATN#
BL4 SRN150F-1-GP
NC#BL4 RN27
BL2
NC#BL2 GMCH_BLUE
BK2 1 8
NC#BK2 GMCH_GREEN
BK1
BH1
NC#BK1 for debug only 3D3V_S0 -1 GMCH_RED
2
3
7
6
NC#BH1
BE1 4 5
NC#BE1
G1 C29
NC#G1 HDA_BCLK RN46
B30
HDA_RST# SDVO_CLK
D28 3 2
HDA_SDI SDVO_DAT
A27 4 1
HDA_SDO SRN0J-10-GP-U
B28
HDA_SYNC
HDA

DY

CANTIGA-GS-GP-NF

1D05V_S0
RN23
1

3D3V_S0 1 8 TV_DACC
R198 2 7 TV_DACB
SRN10KJ-5-GP 56R2F-1-GP 3 6 TV_DACA
PM_EXTTS#0 3 2 4 5
PM_EXTTS#1 4 1
2

MCH_TSATN#
RN28 SRN75J-1-GP

3D3V_S0

SRN10KJ-5-GP
A LCTLA_CLK A
3 2
LCTLB_DATA 4 1
RN6

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (2 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 8 of 48
5 4 3 2 1
5 4 3 2 1

M_A_DQ[63..0] NB1D 4 OF 10 M_B_DQ[63..0] NB1E 5 OF 10


18 M_A_DQ[63..0] 17 M_B_DQ[63..0]
M_A_DQ0 AP46 BC21 M_A_BS#0 18 M_B_DQ0 AP54 BJ13 M_B_BS#0 17
M_A_DQ1 SA_DQ_0 SA_BS_0 M_B_DQ1 SB_DQ_0 SB_BS_0
AU47 SA_DQ_1 SA_BS_1 BJ21 M_A_BS#1 18 AM52 SB_DQ_1 SB_BS_1 BK12 M_B_BS#1 17
M_A_DQ2 AT46 BJ41 M_A_BS#2 18 M_B_DQ2 AR55 BK38 M_B_BS#2 17
M_A_DQ3 SA_DQ_2 SA_BS_2 M_B_DQ3 SB_DQ_2 SB_BS_2
AU49 SA_DQ_3 AV54 SB_DQ_3
M_A_DQ4 AR45 BH22 M_A_RAS# 18 M_B_DQ4 AM54
M_A_DQ5 SA_DQ_4 SA_RAS# M_B_DQ5 SB_DQ_4
AN49 SA_DQ_5 SA_CAS# BK20 M_A_CAS# 18 AN53 SB_DQ_5 SB_RAS# BE21 M_B_RAS# 17
M_A_DQ6 AV50 BL15 M_A_W E# 18 M_B_DQ6 AT52 BH14 M_B_CAS# 17
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ7 SB_DQ_6 SB_CAS#
AP50 SA_DQ_7 AU53 SB_DQ_7 SB_WE# BK14 M_B_W E# 17
D M_A_DQ8 AW47 M_B_DQ8 AW53 D
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
BD50 SA_DQ_9 AY52 SB_DQ_9
M_A_DQ10 AW49 M_A_DM[7..0] M_B_DQ10 BB52
SA_DQ_10 M_A_DM[7..0] 18 SB_DQ_10
M_A_DQ11 BA49 AT50 M_A_DM0 M_B_DQ11 BC53 M_B_DM[7..0]
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7..0] 17
M_A_DQ12 BC49 BB50 M_A_DM1 M_B_DQ12 AV52 AP52 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AV46 SA_DQ_13 SA_DM_2 BB46 AW55 SB_DQ_13 SB_DM_1 AY54
M_A_DQ14 BA47 BE39 M_A_DM3 M_B_DQ14 BD52 BJ49 M_B_DM2
M_A_DQ15 SA_DQ_14 SA_DM_3 M_A_DM4 M_B_DQ15 SB_DQ_14 SB_DM_2 M_B_DM3
AY50 SA_DQ_15 SA_DM_4 BB12 BC55 SB_DQ_15 SB_DM_3 BJ43

A
M_A_DQ16 BF46 BE7 M_A_DM5 M_B_DQ16 BF54 BH12 M_B_DM4
M_A_DQ17 SA_DQ_16 SA_DM_5 M_A_DM6 M_B_DQ17 SB_DQ_16 SB_DM_4 M_B_DM5
BC47 SA_DQ_17 SA_DM_6 AV10 BE51 SB_DQ_17 SB_DM_5 BD2
M_A_DQ18 BF50 AR9 M_A_DM7 M_B_DQ18 BH48 AY2 M_B_DM6

B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_A_DQS[7..0] M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BF48 SA_DQ_19 M_A_DQS[7..0] 18 BK48 SB_DQ_19 SB_DM_7 AJ3
M_A_DQ20 BC43 AR47 M_A_DQS0 M_B_DQ20 BE53 M_B_DQS[7..0]
M_B_DQS[7..0] 17

MEMORY
M_A_DQ21 SA_DQ_20 SA_DQS_0 M_A_DQS1 M_B_DQ21 SB_DQ_20 M_B_DQS0
BE49 SA_DQ_21 SA_DQS_1 BA45 BH52 SB_DQ_21 SB_DQS_0 AR53
M_A_DQ22 BA43 BE45 M_A_DQS2 M_B_DQ22 BK46 BA53 M_B_DQS1
M_A_DQ23 SA_DQ_22 SA_DQS_2 M_A_DQS3 M_B_DQ23 SB_DQ_22 SB_DQS_1 M_B_DQS2

MEMORY
BE47 SA_DQ_23 SA_DQS_3 BC41 BJ47 SB_DQ_23 SB_DQS_2 BH50
M_A_DQ24 BF42 BC13 M_A_DQS4 M_B_DQ24 BL45 BK42 M_B_DQS3
M_A_DQ25 SA_DQ_24 SA_DQS_4 M_A_DQS5 M_B_DQ25 SB_DQ_24 SB_DQS_3 M_B_DQS4
BC39 SA_DQ_25 SA_DQS_5 BB10 BJ45 SB_DQ_25 SB_DQS_4 BH8

www.kythuatvitinh.com
M_A_DQ26 BF44 BA7 M_A_DQS6 M_B_DQ26 BL41 BB2 M_B_DQS5
M_A_DQ27 SA_DQ_26 SA_DQS_6 M_A_DQS7 M_B_DQ27 SB_DQ_26 SB_DQS_5 M_B_DQS6
BF40 SA_DQ_27 SA_DQS_7 AN7 BH44 SB_DQ_27 SB_DQS_6 AV2
M_A_DQ28 BB40 M_A_DQS#[7..0] M_B_DQ28 BH46 AM2 M_B_DQS7
SA_DQ_28 M_A_DQS#[7..0] 18 SB_DQ_28 SB_DQS_7
M_A_DQ29 BE43 AR49 M_A_DQS#0 M_B_DQ29 BK44 M_B_DQS#[7..0]
SA_DQ_29 SA_DQS#_0 SB_DQ_29 M_B_DQS#[7..0] 17
M_A_DQ30 BF38 AW45 M_A_DQS#1 M_B_DQ30 BK40 AT54 M_B_DQS#0
M_A_DQ31 SA_DQ_30 SA_DQS#_1 M_A_DQS#2 M_B_DQ31 SB_DQ_30 SB_DQS#_0 M_B_DQS#1
BE41 SA_DQ_31 SA_DQS#_2 BC45 BJ39 SB_DQ_31 SB_DQS#_1 BB54
M_A_DQ32 BA15 BA41 M_A_DQS#3 M_B_DQ32 BK10 BJ51 M_B_DQS#2
M_A_DQ33 SA_DQ_32 SA_DQS#_3 M_A_DQS#4 M_B_DQ33 SB_DQ_32 SB_DQS#_2 M_B_DQS#3
BE11 SA_DQ_33 SYSTEM SA_DQS#_4 BA13 BH10 SB_DQ_33 SB_DQS#_3 BH42
M_A_DQ34 BE15 BA11 M_A_DQS#5 M_B_DQ34 BK6 BK8 M_B_DQS#4
M_A_DQ35 SA_DQ_34 SA_DQS#_5 M_A_DQS#6 M_B_DQ35 SB_DQ_34 SB_DQS#_4 M_B_DQS#5
BF14 SA_DQ_35 SA_DQS#_6 BA9 BH6 SB_DQ_35 SB_DQS#_5 BC3
M_A_DQ36 M_A_DQS#7 M_B_DQ36 M_B_DQS#6

SYSTEM
BB14 SA_DQ_36 SA_DQS#_7 AN9 BJ9 SB_DQ_36 SB_DQS#_6 AW3
C M_A_DQ37 BC15 M_A_A[14..0] M_B_DQ37 BL11 AN3 M_B_DQS#7 C
SA_DQ_37 M_A_A[14..0] 18 SB_DQ_37 SB_DQS#_7
M_A_DQ38 BE13 BC23 M_A_A0 M_B_DQ38 BG5 M_B_A[14..0]
SA_DQ_38 SA_MA_0 SB_DQ_38 M_B_A[14..0] 17
M_A_DQ39 BF16 BF22 M_A_A1 M_B_DQ39 BJ5 BJ15 M_B_A0
M_A_DQ40 SA_DQ_39 SA_MA_1 M_A_A2 M_B_DQ40 SB_DQ_39 SB_MA_0 M_B_A1
BF10 SA_DQ_40 SA_MA_2 BE31 BG3 SB_DQ_40 SB_MA_1 BJ33
M_A_DQ41 BC11 BC31 M_A_A3 M_B_DQ41 BF4 BH24 M_B_A2
M_A_DQ42 SA_DQ_41 SA_MA_3 M_A_A4 M_B_DQ42 SB_DQ_41 SB_MA_2 M_B_A3
BF8 SA_DQ_42 SA_MA_4 BH26 BD4 SB_DQ_42 SB_MA_3 BA17
M_A_DQ43 BG7 BJ35 M_A_A5 M_B_DQ43 BA3 BF36 M_B_A4
M_A_DQ44 SA_DQ_43 SA_MA_5 M_A_A6 M_B_DQ44 SB_DQ_43 SB_MA_4 M_B_A5
BC7 SA_DQ_44 SA_MA_6 BB34 BE5 SB_DQ_44 SB_MA_5 BH36
M_A_DQ45 BC9 BH32 M_A_A7 M_B_DQ45 BF2 BF34 M_B_A6
M_A_DQ46 SA_DQ_45 SA_MA_7 M_A_A8 M_B_DQ46 SB_DQ_45 SB_MA_6 M_B_A7
DDR

BD6 SA_DQ_46 SA_MA_8 BB26 BB4 SB_DQ_46 SB_MA_7 BK34


M_A_DQ47 BF12 BF32 M_A_A9 M_B_DQ47 AY4 BJ37 M_B_A8
M_A_DQ48 SA_DQ_47 SA_MA_9 M_A_A10 M_B_DQ48 SB_DQ_47 SB_MA_8 M_B_A9
AV6 SA_DQ_48 SA_MA_10 BA21 BA1 SB_DQ_48 SB_MA_9 BH40

DDR
M_A_DQ49 BB6 BG25 M_A_A11 M_B_DQ49 AP2 BH16 M_B_A10
M_A_DQ50 SA_DQ_49 SA_MA_11 M_A_A12 M_B_DQ50 SB_DQ_49 SB_MA_10 M_B_A11
AW7 SA_DQ_50 SA_MA_12 BH34 AU1 SB_DQ_50 SB_MA_11 BK36
M_A_DQ51 AY6 BH18 M_A_A13 M_B_DQ51 AT2 BH38 M_B_A12
M_A_DQ52 SA_DQ_51 SA_MA_13 M_A_A14 M_B_DQ52 SB_DQ_51 SB_MA_12 M_B_A13
AT10 SA_DQ_52 SA_MA_14 BE25 AT4 SB_DQ_52 SB_MA_13 BJ11
M_A_DQ53 AW11 M_B_DQ53 AV4 BL37 M_B_A14
M_A_DQ54 SA_DQ_53 M_B_DQ54 SB_DQ_53 SB_MA_14
AU11 SA_DQ_54 AU3 SB_DQ_54
M_A_DQ55 AW9 M_B_DQ55 AR3
M_A_DQ56 SA_DQ_55 M_B_DQ56 SB_DQ_55
AR11 SA_DQ_56 AN1 SB_DQ_56
M_A_DQ57 AT6 M_B_DQ57 AP4
M_A_DQ58 SA_DQ_57 M_B_DQ58 SB_DQ_57
AP6 SA_DQ_58 AL3 SB_DQ_58
M_A_DQ59 AL7 M_B_DQ59 AJ1
M_A_DQ60 SA_DQ_59 M_B_DQ60 SB_DQ_59
AR7 SA_DQ_60 AK4 SB_DQ_60
M_A_DQ61 AT12 M_B_DQ61 AM4
M_A_DQ62 SA_DQ_61 M_B_DQ62 SB_DQ_61
AM6 SA_DQ_62 AH2 SB_DQ_62
M_A_DQ63 AU7 M_B_DQ63 AK2
SA_DQ_63 SB_DQ_63
CANTIGA-GS-GP-NF CANTIGA-GS-GP-NF
B B

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (3 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 9 of 48
5 4 3 2 1
5 4 3 2 1
NB1G 7 OF 10

VCC_GFXCORE
1D5V_S3

NB1F 6 OF 10
T32
VCC_AXG_NCTF
BB36 U31
VCC_SM VCC_AXG_NCTF
BE35 T31
VCC_SM VCC_AXG_NCTF 1D05V_S0
AW34 R31 FOR VCC CORE
VCC_SM VCC_AXG_NCTF
AW32 U29
VCC_SM VCC_AXG_NCTF
BK30 T29
VCC_SM VCC_AXG_NCTF
BH30 R29 AT41
VCC_SM VCC_AXG_NCTF VCC
BF30 U28 AR41
VCC_SM VCC_AXG_NCTF VCC
BD30 U27 AN41
VCC_SM VCC_AXG_NCTF C213 C221 C236 C204 C206 C212 C198 VCC
BB30 T27 AJ41

1
VCC_SM VCC_AXG_NCTF VCC

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AW30 R27 AH41
VCC_SM VCC_AXG_NCTF VCC
BL29 U25 AD41
VCC_SM VCC_AXG_NCTF VCC
BJ29 T25 AC41

2
VCC_SM VCC_AXG_NCTF VCC
BG29 R25 Y41
VCC_SM VCC_AXG_NCTF VCC
D BE29 U24 W41 D
VCC_SM VCC_AXG_NCTF VCC
BC29 U22 AT40
VCC_SM VCC_AXG_NCTF VCC

POWER
BA29 T22 AM40
VCC_SM VCC_AXG_NCTF VCC
AY29 R22 AL40
VCC_SM VCC_AXG_NCTF VCC
BK28 U21
VCC_SM VCC_AXG_NCTF Coupling CAP 370 mils from the Edge
BH28 T21 AJ40
VCC_SM VCC_AXG_NCTF VCC

VCC CORE
BF28 R21 AH40
VCC_SM VCC_AXG_NCTF VCC
BD28 AM19 AG40
VCC_SM VCC_AXG_NCTF VCC
BB28 AL19 AE40
VCC_SM VCC_AXG_NCTF VCC
BL27 AH19 AD40
VCC_SM VCC_AXG_NCTF VCC
BJ27 AG19 AC40
VCC_SM VCC_AXG_NCTF VCC
BG27 AE19 AA40
VCC_SM VCC_AXG_NCTF VCC

VCC SM
BE27 AD19 Y40
VCC_SM VCC_AXG_NCTF VCC_GFXCORE VCC
BC27 AC19 AN35

VCC GFX NCTF


VCC_SM VCC_AXG_NCTF VCC
BA27 W19 AM35

1
VCC_SM VCC_AXG_NCTF C218 C205 VCC
AY27 U19 AJ35
VCC_SM VCC_AXG_NCTF VCC
AW26 AM18 AH35
VCC_SM VCC_AXG_NCTF SCD1U10V2KX-4GP VCC
BF24 AL18 AD35

2
1

1
VCC_SM VCC_AXG_NCTF C174 C192 C163 C165 C178 C170 C184 C159 C162 BC1 C171 C172 VCC
BL19 AJ18 AC35

1
VCC_SM VCC_AXG_NCTF SC10U6D3V5MX-3GP VCC
BB16 AH18 W35

SC1U10V3KX-3GP
SC10U10V5KX-2GP

SC10U10V5KX-2GP
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
VCC_SM VCC_AXG_NCTF VCC
AG18 AM34

2
VCC_GFXCORE VCC_AXG_NCTF VCC
AE18 AL34

2
VCC_AXG_NCTF VCC
AD18 AJ34
VCC_AXG_NCTF VCC
AC18 AH34
VCC_AXG_NCTF VCC
W32
VCC_AXG VCC_AXG_NCTF
AA18 Coupling CAP AG34
VCC
AG31 Y18 AE34 1D05V_S0
VCC_AXG VCC_AXG_NCTF VCC

www.kythuatvitinh.com

POWER
AE31 W18 AD34
VCC_AXG VCC_AXG_NCTF VCC
AD31 U18 AT38
VCC_AXG VCC_AXG_NCTF Coupling CAP VCC_NCTF
AC31 T18 AC34 AR38
VCC_AXG VCC_AXG_NCTF VCC VCC_NCTF
AA31 R18 DY DY AA34 AN38
VCC_AXG VCC_AXG_NCTF DY DY DY VCC VCC_NCTF
Y31 AM38
VCC_AXG VCC_NCTF
W31 Place on the Edge Y34 AL38
VCC_AXG VCC_GFXCORE VCC VCC_NCTF
AH29 W34 AG38
VCC_AXG VCC VCC_NCTF
AG29 AM32 AE38
VCC_AXG VCC VCC_NCTF
AE29 AL32 AA38
VCC_AXG VCC VCC_NCTF
AD29 AJ16 AJ32 Y38
VCC_AXG VCC_AXG VCC VCC_NCTF
AC29 AH16 AH32 W38
VCC_AXG VCC_AXG VCC VCC_NCTF
AA29 AD16 AE32 U38
VCC_AXG VCC_AXG VCC VCC_NCTF
Y29 AC16 AD32 T38
VCC_AXG VCC_AXG VCC VCC_NCTF
W29 AA16 AA32 R38
VCC_AXG VCC_AXG VCC VCC_NCTF
AH28 U16 AM31 AT37
VCC_AXG VCC_AXG VCC VCC_NCTF
C AG28 T16 AL31 AR37 C
VCC_AXG VCC_AXG VCC VCC_NCTF
VCC GFX

AE28 R16 AJ31 AN37


VCC_AXG VCC_AXG VCC VCC_NCTF
AA28 AM15 AH31 AM37
VCC_AXG VCC_AXG VCC VCC_NCTF
AH27 AL15 AM29 AL37
VCC_AXG VCC_AXG VCC VCC_NCTF
AG27
VCC_AXG VCC_AXG
AJ15 Place CAP where AL29
VCC VCC_NCTF
AJ37
AE27 AH15 LVDS and DDR3 taps AM28 AH37
VCC_AXG VCC_AXG VCC VCC_NCTF
AD27 AG15 AL28 AG37
VCC_AXG VCC_AXG VCC VCC_NCTF
AC27 AE15 AJ28 AE37
VCC_AXG VCC_AXG VCC VCC_NCTF
AA27 AA15 AM27 AD37
VCC_AXG VCC_AXG VCC VCC_NCTF
Y27 Y15 FOR VCC SM AL27 AC37
VCC_AXG VCC_AXG VCC VCC_NCTF

VCC NCTF
W27 W15 AM25 AA37
VCC_AXG VCC_AXG 1D5V_S3 VCC VCC_NCTF
AH25 U15 AL25 Y37
VCC_AXG VCC_AXG VCC VCC_NCTF
AD25 T15 AJ25 W37
VCC_AXG VCC_AXG VCC VCC_NCTF
AC25 AM24 U37
VCC_AXG C191 C187 R52 VCC_GMCH_35 N36 VCC VCC_NCTF
W25 1 2 T37

1
VCC_AXG VCC VCC_NCTF

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
AJ24 C217 C216 C166 DY TC10 0R0402-PAD R37

1
VCC_AXG VCC_NCTF

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

ST330U2D5VBM-GP
AH24 AT35
VCC_AXG SCD1U10V2KX-4GP VCC_NCTF
AG24 AR35
2

2
VCC_AXG VCC_NCTF
AE24 U35

2
VCC_AXG VCC_NCTF
AD24 AT34
VCC_AXG VCC_NCTF
AC24 AR34
VCC_AXG VCC_NCTF
AA24 U34
VCC_AXG VCC_NCTF
Y24 T34
VCC_AXG VCC_NCTF
W24 R34
VCC_AXG VCC_NCTF
AM22
VCC_AXG
AL22
VCC_AXG
AJ22
VCC_AXG
Place on the Edge
VCC GFX

AH22
VCC_AXG
AG22
VCC_AXG
AE22
VCC_AXG
AD22
VCC_AXG
AC22
VCC_AXG
AA22 AU45 SM_LF1_GMCH
VCC_AXG VCC_SM_LF
VCC SM LF

AM21 BF52 SM_LF2_GMCH


VCC_AXG VCC_SM_LF
AL21 BB38 SM_LF3_GMCH
VCC_AXG VCC_SM_LF
AJ21 BA19 SM_LF4_GMCH
VCC_AXG VCC_SM_LF
AH21 BE9 SM_LF5_GMCH
VCC_AXG VCC_SM_LF
AD21 AU9 SM_LF6_GMCH
SCD47U10V3KX-3GP

VCC_AXG VCC_SM_LF
AC21 AL9 SM_LF7_GMCH CANTIGA-GS-GP-NF
VCC_AXG VCC_SM_LF
C211

C237

C229

AA21
SC1U10V3KX-3GP

SC1U10V3KX-3GP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP
1

VCC_AXG
C146

C142

Y21 C147 C175


B VCC_AXG B
W21
VCC_AXG
AM16
2

VCC_AXG
AL16
VCC_AXG

VCC_AXG_SENSE AG13
38 VCC_AXG_SENSE VCC_AXG_SENSE
38 VSS_AXG_SENSE VSS_AXG_SENSE AE13
VSS_AXG_SENSE

place near Cantiga


U60(ISL6263ACRZ-T-GP) place near Cantiga
CANTIGA-GS-GP-NF

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (4 of 6)
Size Document Number Rev

JM41_Discrete -1
Date: Monday, April 06, 2009 Sheet 10 of 48
5 4 3 2 1
5 4 3 2 1

5V_S0 Imax = 300 mA 3D3V_S0_DAC 1D05V_S0


3D3V_S0_DAC 852mA
U30 80mA NB1H 8 OF 10

SC2D2U6D3V3MX-1-GP
SCD01U16V2KX-3GP

SCD1U10V2KX-4GP
C209 C210

ST220U2D5VDM-13GP
SCD47U6D3V2KX-GP

SC4D7U6D3V3KX-GP

SCD47U6D3V2KX-GP
1

1
1 1 TC8

C228

C220

C179

C193
1 VIN VOUT 5 VTT R13
2 GND VTT T12

1
3 4 J31 R11 2 2

2
EN NC#4 C509 VCCA_CRT_DAC VTT
VTT T10 DY
SC10U6D3V5MX-3GP R9

2
VTT
1

1
SC1U10V3KX-3GP

BC3 RT9198-33PBR-GP T8
BC2 VTT
74.09198.G7F L31 R7

CRT
3D3V_S0_DAC VCCA_DAC_BG VTT

SC1U10V3KX-3GP
74.09091.J3F M33 T6
2

2
VSSA_DAC_BG VTT
R5
D
10mA VTT
VTT T4
D

SCD01U16V2KX-3GP

SCD1U10V2KX-4GP
C202 C201 R3
VTT

1
M_VCCA_DPLLA J45 T2 3D3V_S0_DAC
1D05V_S0 VCCA_DPLLA VTT
R1

VTT
M_VCCA_DPLLB VTT
L49

2
VCCA_DPLLB
65mA

PLL

1
M_VCCA_DPLLA M_VCCA_HPLL AF10 180ohm 100MHz
VCCA_HPLL C197
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

C520 C519 C518 M_VCCA_MPLL AE1 K30

2
VCCA_MPLL VCCA_TV_DAC SCD1U10V2KX-4GP

TV
1D8V_NB_S0
2

A PEG A LVDS
1
U43
C225 13.2mA U41
VCCA_LVDS
A31 SB

D TV/CRT HDA
SC1KP50V2KX-1GP VCCA_LVDS VCC_HDA
DY DY

2
V44
65mA M_VCCA_DPLLB 1D5V_S0 VSSA_LVDS

www.kythuatvitinh.com
N34 1D5VRUN_TVDAC
VCCD_QDAC
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

C528 C527 C529 AJ43 VCCA_PEG_BG 1D5VRUN_QDAC


VCCD_TVDAC N32

1
C227
50mA
2

SCD1U10V2KX-4GP I=300mA NB:180mA


1D05V_S0 1D05V_RUN_PEGPLL AG43

2
VCCA_PEG_PLL
3D3V_S0 U10
DY DY

2
AW24 VCCA_SM 1 VIN VOUT 5 1D8V_NB_S0
AU24 1D05V_S0 C222 2
VCCA_SM
POWER GND

2
SC1U10V2ZY-GP
C148 C160 C155 AW22 3 4
480mA 350mA

1
VCCA_SM EN/EN# NC#4

1
SC4D7U6D3V3KX-GP

SC1U10V3KX-3GP
C AU22 C234 C
VCCA_SM

SC10U6D3V5MX-3GP

SC1U10V2ZY-GP
AU21

1
1D05V_S0 VCCA_SM

SC10U6D3V5MX-3GP
AW20 RT9198-18PBR-GP

2
VCCA_SM

1
1D05V_SUS_MCH_PLL2

SC1U10V3KX-3GP

C231
AU19 C203 74.09198.C7F
VCCA_SM
AW18 74.09091.G3F

A SM
VCCA_SM
AU18 DY

2
VCCA_SM
AW16
FCM1608KF-1-GP 24mA AU16
VCCA_SM
VCCA_SM
1 2 M_VCCA_HPLL AT16 VCCA_SM
SC4D7U6D3V3KX-GP

L3 AR16 VCCA_SM
1

68.00217.161 C145 C153 AU15


SCD1U10V2KX-4GP