NOVEMBER 29 2010
Abstract—this paper is dealing with the single phase semi average. Using Parametric Sweep in the PSPICE, the values of
controlled full wave rectifiers operating at the fourth quadrant. It L and C could be found for the 10 percent ripple in the output
deals with finding the optimum value of series inductance to limit voltage of the rectifier. The values of L and C could also be
the peak-to-peak ripple at the output voltage to 10% of its found out using the Fourier series expansion of the average
average. It is shown next that a parallel capacitor can be added to
the load resistor to minimize the size of series inductance for
output voltage of the full wave rectifiers [4].The design of
maintain the output voltage ripple to 10% of its average. In both control circuit could be done like Pulse Width Modulation
of these cases, only the fundamental components of the ripple are (PWM). In this paper, the different approach of control circuit
considered. The next part of the paper consists of the control design is shown using 555 timer and OPAMPS.
circuit design for firing the thyristor at the specified angle.. The
delay angle alpha is calculated by varying the resistor(R) and IV. CONVETER OPERATION AND DESIGN
capacitor(C) values of 555 timer operated at the mono stable
mode and triggered by the pulse generated at the zero crossing of
the input voltage. The basic full wave rectifier circuit to be implemented is
shown in Fig 1.
Index Terms—rectifier, zero crossing detection, firing angle,
Total harmonic distortion, Power Factor.
I. INTRODUCTION
Design of inductive filter was made for α=0, C=0 and Since the average voltage across the inductor in the steady
R=10Ω .The value of series inductance is to be calculated for state is zero, the average output voltage for continuous
the peak to peak ripple to be 10% of the average output
inductor current from eqn (1.2) is,
voltage (v0).
2Vm
Vo
For the full wave rectifier, sinusoidal voltage across the load
can be expressed as a Fourier series consisting of a dc term
Average inductor current must equal the average resistor
and the even harmonics [6].
current because the average capacitor current is zero.
Vo 2Vm
IL IR
vo t Vo V
n 2,4..
n cos(not ) (1.1) R R
(1.4)
Fig 3: Circuit diagrams for the positive edge zero crossing detection of the
Fig 2: Block diagram of the control circuit input voltage waveform.
The transformer input voltage is the supply voltage which is crossing of input wave( which is already determined ).
170 volt peak to peak at 60 Hz. The transformer inductances Negative edge detection is used for firing the second
L1 and L2 are chosen as 260 and 2 henry respectively in thyristor(T2) since it gets forward biased only in the negative
order to get 17 volt peak to peak at the secondary. half cycle of the input wave. The negative edge zero crossing
For the simulation of transformer, XFRM_LINEAR of the circuit is shown in fig(8) and the corresponding waveform is
Analog Library, in pspice is used. The coupling factor K is shown in fig(10).
chosen to be 1 .Since the secondary circuit needs a DC
connection to ground, it is done by adding a large resistor of
100MΩ.
The ua741OPAMP is used as a comparator. The output
voltage of the transformer is directly fed to the Opamp ua741
which is biased to +5volt at +Vcc and and 0Volt to –Vcc,
produces the output pulses as shown in Fig 4.
Fig 6: Negative edge zero crossing detection of the input voltage waveform.
Fig 4: Positive edge, zero crossing detection of the input voltage waveform There are two separate phase control circuits for the two
(out1) thyristors. It consists of 555 timers and MOSFET as a switch.
As shown in Fig 4, the pulse generated by the opamp starts at The MOFET used is the IRF540. The 555 timer is operated in
the positive edge zero crossing point of the input voltage monostable mode. In the monostable mode of the 555 timer,
wave. These pulses are later used for the firing of first the output pulse of duration equivalent to 1.1RC second is
Thyrisotr(T1), which becomes forward biased during the produced at the output pin 2 when a negative edge transition
positive half cycle of the input voltage wave. occurs at the trigger pin 2
ii. Negative edge zero crossing detection of the i. Operation of phase control circuit
input voltage waveform
In the monostable mode of operation, pins 6(threshold) and
For the zero crossing detection of the input voltage wave 7(discharge) are shorted and connected to the Vcc(+12V) via a
while going from negative value to positive value (i.e for the resistor(R) and connected to the ground via a capacitor(C2) as
negative edge zero crossing detection), the signal from the shown in Fig 7.These values of R and C determines the period
transformer is inverted using the an opamp as an inverter of the output pulse given by 1.1RC sec. Pin 5(control) is
whose gain is adjusted to 1 by keeping the values of R1 and Rf grounded via a capacitor(C1). Pin 4(reset output) is connected
equal.This inverted signal is sent to the another opamp as a to the Vcc. Pin2(trigger) input to the 555 timer is connected to
comparator as shown in Fig 5 to generate the pulse at the the source terminal of the MOSFET(M2) which his connected
negative zero crossing edge. to the source via a resistor.
Fig 10: Output of the 555 timer for firing the Q2 thyristor
The gate drive circuit uses pulse transformers for the isolation
of control signal from input voltage signal. It is shown in Fig
11. The gate drive circuit is designed for the thryristor 2N3899
Fig 7: Phase control circuit for the firing Thyristor (Q1) which requires 4 to 5.2mA triggering current at its gate for
firing. The MOSFETS at the first stage of the gate drive
circuit (M11 and M14) invert the pulse obtained from the
respective 555 timer. These inverted pulses are used as
controls for the second stage MOSFETS(M8 and M12). The
corresponding second stage voltage waveforms at terminal n1
and n2 of MOSFETS (M8 and M12) are shown in Fig 12 and
Fig 13 respectively. When input to the second stage MOSFET
is low( corresponding to the high voltage at 555 timer output),
the primary side of the transformer would not be grounded and
thus no current flows at the primary loop. Now when input to
the second stage MOSFET is high( corresponding to the high
voltage at 555 timer output), the MOSFET behaves as a short
Fig 8: Output of the 1st 555 timer for firing the thyristor Q1 circuit connecting the primary of the transformer to the +12V
supply. The diode across the primary is needed to circulate the
magnetizing current of the transformer[7].By this method, the
primary is connected to the +12V supply during period when
the value of output pulse of 555 timer goes low. In the
secondary side of the transformer, one end is connected to the
gate of the thryster via a diode and a resistor while the other
side is connected to the common ground of the bridge rectifier.
As soon as the primary of the pulse transformer gets
connected to the +12V supply, an impulse of short duration at
the secondary terminal would be produced as shown in Fig
14and Fig 15. The diode in the secondary would allow the
unidirectional flow of impulse current to the gate. The resistor
values are chosen such that the impulse current would be
sufficient to fire the thyristors as shown in Fig 16and Fig 17.
Fig 12: voltage pulse found at n1 Fig 14: Voltage pulse found at m1
Fig 13: Voltage pulse found at n2 Fig 15: Voltage pulse found at m2
Case II: 0 and inductive filter (L=180mH)
Vs
Vsrms 120.2V
2
From Fig(28) and Fig(29),
I srms 2.37 A
I orms 2.38 A
P I orms
2
R 56.56watt
Again,
3.2
I1rms 2.26 A
2
P watt 56.56
pf 0.198
S Vs ,rms I s ,rms 120.2 2.37
Fig 30: waveform for (Vs) and load voltage(Vo)
From eqn(3.3),
2
I srms I1,2srms
THD 0.31
I1,2srms
2
I srms I1,2srms
THD 0.619
I1,2srms
Fig(35) shows that average current across capacitor is 0.
Fig 32: waveform of source current ( Is) Fig 35: waveform for the capacitor current
VII. CONCLUTION
[1] http://www.scribd.com/doc/18667041/Controlled-Rectifiers-Sharifah-
Azma-Syed-Mustaffa
[2] Power Electronics,Circuits ,devices and application,second
edition,Muhammad H. Rashid pg 323,345
[3] http://www.services.eng.uts.edu.au/~venkat/pe_html/ch06s1/ch06s1p1.h
tm
[4] Power Electronics, Daniel W.Hart, McGRAW HILLpg, 135,136
[5] http://www.seas.upenn.edu/~jan/spice/PSpicePrimer.pdf
[6] Power Electronics, Daniel W.Hart pg 120
[7] http:// www.engr.siu.edu/staff1/hatz/EE483/LABS/Exp3.html