MEALY 101 SEQUENCE DETECTOR (WITH OVERLAPPING )

library ieee;
use ieee.std_logic_1164.all;

entity miley is
port(x,clk,reset: in bit; z: out bit);
end miley;

architecture bev of miley is

Type state_type is (s0, s1, s2);

signal state: state_type;

begin
process(state,reset)
begin
if reset = '1' then
state <= s0;
else if (clk' event and clk = '1') then

case state is

when s0 => if x='0' then z<='0';

state <=s0;

elsif x='1' then z<='0';

state<=s1; end if;

when s1 => if x='0' then z<='0';

state <=s2;

elsif x='1' then z<='0';

state <= s1; end if;

when s2 => if x='0' then z<='0';

state <=s0;

elsif x='1' then z<='1';

state <=s1; end if;

when others => null;

end case;
end if;
end if;
end process;
end bev;
RTL VIEW :

state Selector0

clk clk

reset reset s2 z~reg0

SEL[1..0]
x x PRE
OUT D Q z
DATA[1..0]
ENA

CLR
0
0 SELECTOR
0 1
0 1
z~0
z~1

0
0
1 1
0 1
z~2
z~3

STATE VIEW :

s0 s1 s2
reset
MEALY 101 SEQUENCE DETECTOR (WITHOUT OVERLAPPING )

entity miley is
port(x,clk,reset: in bit; z: out bit);
end miley;

architecture bev of miley is

Type state_type is (s0, s1, s2);

signal state: state_type;

begin
process(state,reset)
begin
if reset = '1' then
state <= s0;
else if (clk' event and clk = '1') then

case state is

when s0 => if x='0' then z<='0';

state <=s0;

elsif x='1' then z<='0';

state<=s1; end if;

when s1 => if x='0' then z<='0';

state <=s2;

elsif x='1' then z<='0';

state <= s1; end if;

when s2 => if x='0' then z<='0';

state <=s0;

elsif x='1' then z<='1';

state <=s0; end if;

when others => null;

end case;
end if;
end if;
end process;
end bev;
RTL VIEW :

state Selector0

clk clk

reset reset s2 z~reg0

SEL[1..0]
x x PRE
OUT D Q z
DATA[1..0]
ENA

CLR
0
0 SELECTOR
0 1
0 1
z~0
z~1

0
0
1 1
0 1
z~2
z~3

STATE VIEW :

s0 s1 s2
reset
MOORE 101 SEQUENCE DETECTOR (WITHOUT OVERLAPPING ) :

entity moorey is
port(x,clk,reset: in bit; z: out bit);
end moorey;

architecture bev of moorey is

Type state_type is (s0, s1, s2,s3);

signal state: state_type;

begin
process(state,reset)
begin
if reset = '1' then
state <= s0;
else if (clk' event and clk = '1') then

case state is
when s0 => if x='0' then z<='0';
state <=s0;
elsif x='1' then z<='0';
state<=s1; end if;

when s1 => if x='0' then z<='0';

state <=s2;
elsif x='1' then z<='0';
state <= s1; end if;

when s2 => if x='0' then z<='0';

state <=s0;
elsif x='1' then z<='0';
state <=s3; end if;

when s3 => if x='0' then z<='1';

state <=s0;
elsif x='1' then z<='1';
state <=s1; end if;

when others => null;

end case;
end if;
end if;
end process;
end bev;
RTL VIEW :
state Selector0

clk clk

reset reset s3 z~reg0

SEL[1..0]
x x PRE
OUT D Q z
DATA[1..0]
ENA

CLR
0
0 SELECTOR
0 1
0 1
z~0
z~1

0
0
1 1
1 1
z~2
z~3

STATE VIEW :

s0 s1 s2 s3
reset
MOORE 101 SEQUENCE DETECTOR (WITH OVERLAPPING ) :

entity moorey is
port(x,clk,reset: in bit; z: out bit);
end moorey;

architecture bev of moorey is

Type state_type is (s0, s1, s2,s3);

signal state: state_type;

begin
process(state,reset)
begin
if reset = '1' then
state <= s0;
else if (clk' event and clk = '1') then

case state is
when s0 => if x='0' then z<='0';
state <=s0;
elsif x='1' then z<='0';
state<=s1; end if;

when s1 => if x='0' then z<='0';

state <=s2;
elsif x='1' then z<='0';
state <= s1; end if;

when s2 => if x='0' then z<='0';

state <=s0;
elsif x='1' then z<='0';
state <=s3; end if;

when s3 => if x='0' then z<='1';

state <=s2;
elsif x='1' then z<='1';
state <=s1; end if;

when others => null;

end case;
end if;
end if;
end process;
end bev;
RTL VIEW :
state Selector0

clk clk

reset reset s3 z~reg0

SEL[1..0]
x x PRE
OUT D Q z
DATA[1..0]
ENA

CLR
0
0 SELECTOR
0 1
0 1
z~0
z~1

0
0
1 1
1 1
z~2
z~3

STATE VIEW :

s0 s1 s2 s3
reset