INTERGRATED CIRCUIT
DESIGN
Department of Electrical
Engineering
Mr. Azman Bin Mat Hussin
Mrs. Hazanal Suzima
REKABENTUK LITAR
n+ n+
p bulk Si
nMOS Transistor (N-type) structure
pMOS Transistor (P-type)
p+ p+
n bulk Si
pMOS Transistor (P-type) structure
CMOS Inverter
A Y VDD
0
1
A Y
A Y
GND
CMOS Inverter
A Y VDD
0
1 0
OFF
A=1 Y=0
ON
A Y GND
CMOS Inverter
A Y VDD
0 1
ON
1 0
A=0 Y=1
OFF
A Y
GND
CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B
CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF
CMOS NAND Gate
A B Y
0 0 1 ON
OFF
0 1 1 Y=1
1 0 A=0
OFF
1 1
B=1
ON
CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF
CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON
CMOS NOR Gate (Uji Kefahaman)
A B P1 N1 P2 N2 Y
0 0 ON OFF ON OFF 1 A P1
0 1 ON OFF OFF ON 0
1 0 OFF ON ON OFF 0 B P2
1 1 OFF ON OFF ON 0 Y
A
N1 N2
Y
B
CMOS Gate Design
INVERTER GATE
Truth Table
A output
Symbol Logic
CMOS Gate Design
INVERTER GATE
V DD
S
G D
A output Out
D
S In
vss
CMOS TRANSISTOR LEVEL STICK DIAGRAM
CMOS Gate Design
NAND GATE
Truth Table
A
A B F
F
0 0 1
B
0 1 1
Symbol Logic
‘+’ selari
Output 1 0 1
_ _
F = A . B (PMOS) ‘x’ sesiri
_ _ _ 1 1 0
F= A.B
_
F= A+B
CMOS Gate Design
NAND GATE
VDD V
DD
B
A
F(o/p)
Out
VSS A B
GND
0 1 0
Symbol Logic
1 0 0
F=A+B
____ 1 1 0
F=A+B
_ _
F=A•B
CMOS Gate Design
NOR GATE
VDD
B
B
F(o/p)
A
?
B A
VSS
_ _ _
X = C + (A • B) A B
CMOS Gate Design
IQ TEST
X = (A+B)•(C+D) A C
A B D
B
C
D
X = (A+B)•(C+D)
Logic Circuit
C D
A B
CMOS Gate Design
IQ TEST
CMOS LOGIC GATE
X = (AB)+(AC)
? CMOS TRANSISTOR
LEVEL
CMOS STICK
DIAGRAM