Ramakrishna Velaga
S/o Veeranjaneyulu babu, ramucec120@gmail.com
Devarapalli (PO),
Parchur (MD), +919989283293
Prakasam (DT),
Andhra Pradesh.
Career Objective:
To be associated with an organization that gives me a challenging position where I can apply
my skills towards the growth of organization.
Educational Qualifications:
Skills:
Strengths:
Achievements:
Participated in paper presentation in national level on biochip.
Organizer in my college function.
Participated in National Conference on ‘Design of Symbol Deinterleaver for DVB by using
Multibank MemoryBased VLSI Architecture’.
Title : A BIST TPG for low power dissipation and high fault coverage.
Duration : 2 months
Description : Automatic test pattern generator (TPG) for scanbased builtin selftests (BIST) that
can reduce switching activity in circuits under test (CUT s) during BIST and also achieve very high
fault coverage.
Title : Design of Symbol Deinterleaver for DVB by using Multibank
MemoryBased VLSI Architecture
Duration : 8 Months.
Description : The aim of the project is to design of an efficient of symbol-deinterleaver architecture
compliant with the digital-video-broadcasting (DVB) standard is proposed for the at
receiver.
Personal Profile:
Declaration:
I hereby declare that the information furnished above is true to the best of my knowledge.
Place:
Date: (V. Ramakrishna)