end Behavioral;
Verilog code
module basic_gates (a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
assign c= ~a;
assign d=a&b;
assign e=a|b;
assign f=~(a&b);
assign g=~(a|b);
assign h=a^b;
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALF_ADDER is
port( a,b: in bit;
sum, carry: out bit);
end HALF_ADDER;
begin
sum<= a xor b;
carry<= a and b;
end Behavioral;
Verilog code
module half_adder (a,b,sum,carry);
input a,b;
output sum, carry;
assign sum=a^b;
assign carry =a&b;
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Full_adder is
port(a,b,c: in bit;
sum, carry: out bit);
end Full_adder;
begin
sum<= a xor b xor c;
carry<= ( a and b) or (b and c) or (c and a);
end Behavioral;
Verilog code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_beh1 is
Port ( a,b,c : in std_logic;
sum,carry : out std_logic);
end full_beh1;
architecture Behavioral of full_beh1 is
begin
process(a,b,c)
begin
sum<= a xor b xor c;
carry<= (a and b) or (b and c) or (c and a);
end process;
end Behavioral;
Verilog code
module full_adder (a,b,c,sum,carry);
input a,b,c;
output sum, carry;
reg sum,carry;
always@ (a,b,c)
begin
sum=a^b^c;
carry = (a&b)|(b&c) | (c &a );
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_add_struct is
port( x,y,z: in bit;
sum, carry: out bit);
end full_add_struct;
component BASIC_GATES
port( a,b: in bit;
e: out bit);
end component;
signal p,q,r: bit;
begin
Verilog code
module full_struc_14(x,y,z,sum,carry);
input x,y,z;
output sum,carry;
HA (x,y,s0,c0);
HA(z,s0,sum,c1);
Or (carry,c0,c1);
endmodule
Module HA(x,y,s,c);
Input x,y;
Output s,c;
xor (s,x,y);
and (c,x,y,);
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_8_1 is
Port ( I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
y : out std_logic);
end Mux_8_1;
architecture Behavioral of Mux_8_1 is
begin
with S select
Y<= I(0) when "000",
I(1) when "001",
I(2) when "010",
I(3) when "011",
I(4) when "100",
I(5) when "101",
I(6) when "110",
I(7) when "111",
'Z' when others;
end Behavioral;
Verilog code
module mux_8_1(s,i,y);
input [2:0]s;
input [7:0]i;
output y;
reg y;
always@ (i,s);
begin
case (s)
3’d 0 :y = i[0];
3’d 1 :y = i[1];
3’d 2 :y = i[2];
3’d 3 :y = i[3];
3’d 4 :y = i[4];
3’d 5 :y = i[5];
3’d 6 :y = i[6];
3’d 7 :y = i[7];
default:y= ”z”;
end case
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Decoder2to4 is
Port ( r : out std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0));
end Decoder2to4;
Verilog code
module decoder (s,r);
input [1:0]s;
output [3:0]r;
reg [3:0]r;
always@ ( s)
begin
case (s)
2’b 00:r=4’d1;
2’b 01:r=4’d2;
2’b 10:r=4’d3;
2’b 11:r=4’d4;
default:r=”z”;
end case
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Demux is
Port ( I : in std_logic;
sel : in std_logic_vector(2 downto 0);
Y : out std_logic_vector(7 downto 0));
end Demux;
begin
process(sel,I)
begin
if(sel="000") then Y(0) <= I;
else Y(0) <= 'Z';
end if;
end process;
end Behavioral;
Verilog code
y[5]=i;
else
y[5]=”z”;
if (sel==3’d6)
y[6]=i;
else
y[6]=”z”;
if (sel==3’d7)
y[7]=i;
else
y[7]=”z”;
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Encoder_wihtoutpriority is
Port ( a : in std_logic_vector(0 to 7);
b : out std_logic_vector(2 downto 0));
end Encoder_wihtoutpriority;
begin
process(a)
begin
case a is
when "00000001" => b<= "111";
when "00000010" => b<= "110";
when "00000100" => b<= "101";
when "00001000" => b<= "100";
when "00010000" => b<= "011";
when "00100000" => b<= "010";
when "01000000" => b<= "001";
when "10000000" => b<= "000";
when others => b<= "ZZZ";
end case;
end process;
end Behavioral;
Verilog code
module enc_wop(a,b);
input [7:0]a;
output [2:0]b;
reg [2:0]b;
always@ (a);
begin
case (a)
8’b 00000001: b=3’d7;
8’b 00000010: b=3’d6;
8’b 00000100: b=3’d5;
8’b 00001000: b=3’d4;
8’b 00010000: b=3’d3;
8’b 00100000: b=3’d2;
8’b 01000000: b=3’d1;
8’b 10000000: b=3’d0;
default : b=”zzz”;
end case
end
end module
entity encodr_with is
Port ( a : in std_logic_vector(0 to 7);
b : out std_logic_vector(2 downto 0));
end encodr_with;
Verilog code
module encdr(a,b);
input [7:0]a;
output [2:0]b;
reg [2:0]b;
always@ (a);
begin
case (a)
8’b xxxxxxx1: b=3’d7;
8’b xxxxxx10: b=3’d6;
8’b xxxxx100: b=3’d5;
8’b xxxx1000: b=3’d4;
8’b xxx10000: b=3’d3;
8’b xx100000: b=3’d2;
8’b x1000000: b=3’d1;
8’b 10000000: b=3’d0;
default : b=”zzz”;
end case
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Port ( a,b : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(2 downto 0);
agb,alb,aeb, anb : out std_logic);
end comparator;
Verilog code
module copm_2(x,y,z,a,b);
input [1:0] a,b;
Output x,y,z;
assign x = (~(a[1]^b[1])) & (~( a[0]^b[0]));
assign y=(a[1]& (~b[1])) |(a[1]&a[0]&(~b[0])) |
(a[0] & (~b[1]) & (~b[0]));
assign z=( v[1]& (~a[1])) | (b[1]&b[0]&(~a[0]))|
((~a[1]) &~a[0]) &b[0]);
endmodule
12)VHDL code to implement BINARY TO GRAY code conversion
Department of Electronics & Communication Engg. 13 Dr. TTIT, KGF
IV SEMESTER HDL Lab
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Bin_gray is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end Bin_gray;
Verilog code
module bin_gray(b,g);
input [3:0]b;
output [3:0]g;
reg [3:0]g;
always@ ( b)
begin
g[0]=b[0]^b[1];
g[1]=b[1]^b[2];
g[2]=b[2]^b[3];
g[3]=b[3];
end
endmodule
13) VHDL code to implement SR- FLIP-FLOP.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRFF is
Port (reset, s : in bit;
r : in bit;
clk : in bit;
q : inout bit;
qn : out bit:='1');
end SRFF;
architecture Behavioral of SRFF is
begin
process(clk,reset)
begin
if(reset=’1’) then q<= ‘0’;
elsif(clk'event and clk='1')then
q <= s or((not r) and q);
end if;
end process;
qn<=not q;
end Behavioral;
Verilog code
module SR_FF(s,r,clk,q,qn);
input s,r,clk;
output q,qn;
reg q,qn;
always@ (posedge (clk))
begin
q=(s|((~r)&q));
qn=~q;
end
endmodule
14) VHDL code to implement D-FLIP FLOP.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( clk,d,set,reset : in bit;
q : inout bit;
qn : out bit:='1');
end dff;
begin
process( clk, set,reset)
begin
if ( reset='1') then q<='0';
elsif(set = '1')then q<='1';
elsif( clk'event and clk='1')then
q<= d;
end if;
qn<= not q;
end process;
end Behavioral;
Verilog code
q=0;
else if(set==1)
q=1;
else
q=d ;
qn= ~q ;
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( clk,t,set,reset : in bit;
q : inout bit;
qn : out bit:='1');
end tff;
begin
process( clk, set,reset)
begin
if ( reset='0') then q<='0';
elsif(set = '0')then q<='1';
elsif( clk'event and clk='1')then
q<= q xor t;
end if;
qn<= not q;
end process;
end Behavioral;
Verilog code
module t_ff(t,clk,set,reset,q,qn);
input t, clk, set, reset;
output q,qn;
reg q,qn;
always@ (posedge (clk))
begin
if(reset==0)
q=0;
else if(set==0)
q=1;
else
q=q^t ;
qn= ~q ;
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk is
Port ( clk,j,k : in bit;
set,reset : in bit;
q : inout bit;
qn : out bit:=’1’);
end jk;
architecture Behavioral of jk is
begin
process(clk,set, reset)
variable t: bit_vector (1 downto 0);
begin
if ( reset='0') then
q<='0';
elsif(set = '0')then
q<='1';
elsif( clk'event and clk='1')then
t :=j & k;
case t is
when "00" => q<=q;
when "01" => q<='0';
Verilog code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( a,b : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(3 downto 0);
enable: in bit;
res1 : out std_logic_vector(31 downto 0));
end ALU;
Verilog code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary_asyn is
Port ( clk,reset,load,p : in std_logic;
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end binary_asyn;
process(clk)
begin
if(rising_edge(clk))then
sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;
end if;
end if;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Bin_synreset is
Port ( clk,reset,load,p,t : in std_logic;
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end Bin_synreset;
process(clk)
begin
if(rising_edge(clk)) then
sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;
end if;
end if; end if; end if;
end process;
end Behavioral;
VERILOG CODE
reg [3:0] q;
entity bcd_synreset is
Port ( clk,reset,load,p,t : in std_logic;
d : in std_logic_vector(3 downto 0);
q : inout std_logic_vector(3 downto 0));
end bcd_synreset;
process(clk)
begin
if(rising_edge(clk)) then
sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;
VERILOG CODE
reg [3:0] q;
if(reset == 1)
q<= 0000;
else if( load == 1)
q <=d;
else if(p==1)
q <= q + 1;
if(q == 1001)
q<= 0000;
end
endmodule
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd_asynreset is
Port ( clk,reset,load,p,t : in std_logic;
d : in std_logic_vector(3 downto 0);
process(clk)
begin
if(rising_edge(clk)) then
sclkdiv<=sclkdiv+1;
end if;
sclk<=sclkdiv(12);
end process;
q <= d;
else
if(p='1') then
q <= q + 1;
end if;
end if; end if; end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K: in std_logic
);
end TKBELE;
begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyflr <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyflr <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyflr <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyflr <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
then skeyflr <= 4;
elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyflr <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyflr <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyflr <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyflr <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")
begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;
end if;
end if;
end if;
end process;
process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000
111",
"1111111
","1101111","1110111","1111100","1011000","1011110","1111001","1110001");
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
end process;
end behavioral;
23. VHDL code for accepting hexakey pad input data and to display the value on
the given seven segment display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBHKY is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pledind : out std_logic_vector (7 downto 0);
pclk100K : in std_logic
);
end TKBHKY;
begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;
-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyval <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyval <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyval <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyval <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
begin
pdspseg <= segval(skeyval);
pdspmux <= "1110";
end process;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tkblcd is
Port (
plcddat : out std_logic_vector (7 downto 0);
plcdrs,plcdrw,plcden : out std_logic;
pclk100K : in std_logic
);
end tkblcd;
begin
-- clkdivider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
-- display
process(sdspclk)
variable vdspseq : integer range 0 to 15;
variable vdspnum : integer range 0 to 15;
variable i1 : integer;
begin
if(falling_edge(sdspclk) ) then
vdspseq := vdspseq+1;
end if;
if(falling_edge(sdspclk) ) then
if(vdspseq > 3) then
vdspnum := vdspnum+1;
end if;
end if;
end process;
end behavioral;
25. VHDL code to control the SPEED AND DIRECTION OF STEPPER MOTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBSTP is
Port ( pkeycol : in std_logic_vector (3 downto 0);
pkeyrow : out std_logic_vector (3 downto 0);
pstpsig : out std_logic_vector(3 downto 0);
pspdcntrl : in std_logic_vector (1 downto 0);
pclk100K : in std_logic );
end TKBSTP;
begin
-- clkdivider
process(pclk100k,pspdcntrl)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
if ( pspdcntrl = "00") then
sstpclk <= sclkdiv(14);
elsif ( pspdcntrl = "01") then
sstpclk <= sclkdiv(16);
-- key process
-- out key row = 0 check key col
pkeyrow <= "0000";
process(pkeycol)
begin
if(pkeycol(0) = '0' or
pkeycol(1) = '0' or
pkeycol(2) = '0' or
pkeycol(3) = '0' ) then skeyhit <= '0';
else skeyhit <= '1';
end if;
end process;
-- 4 step counter
process(sstpclk)
begin
if(rising_edge(sstpclk)) then
if(skeysts(0) = '0') then
sstpcnt <= sstpcnt+1;
elsif(skeysts(1) = '0') then
sstpcnt <= sstpcnt-1;
end if;
end if;
end process;
end behavioral;
26. DAC
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBDAC is
Port ( pdigout : out std_logic_vector(7 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pledind : out std_logic_vector (7 downto 0);
pclk100K : in std_logic;
pcwave : in std_logic;
psqrwave : out std_logic
);
end TKBDAC;
begin
-- process clk divider
--
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
process(sfclk)
begin
if( rising_edge(sfclk)) then
if(scount = "11111111") then
scmode <= '1';
end if;
if(scount = "00000000") then
scmode <= '0';
end if;
end if;
psqrwave <= scmode;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBADC1 is
Port ( pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
padcclk,padccs : out std_logic;
padcdat : in std_logic;
pclk100K : in std_logic);
end TKBADC1;
begin
-- process clk divider
process(pclk100k)
begin
if( pclk100k = '1' and pclk100k'event) then
sclkdiv <= sclkdiv+1;
end if;
end process;
end process;
if(rising_edge(sadccs))
then sadcregbuf <= sadcreg;
end if;
end process;
-- tst counter
-- process(stmpclk)
-- begin
-- if(rising_edge(stmpclk)) then
-- sadcreg <= sadcreg+1;
-- end if;
-- end process;
-- process pdspmux
process(sdspseq)
begin
if(sdspseq = "000") then sdspmux <= "1110";
elsif(sdspseq = "010") then sdspmux <= "1101";
elsif(sdspseq = "100") then sdspmux <= "1011";
elsif(sdspseq = "110") then sdspmux <= "0111";
else sdspmux <= "1111";
end if;
pdspmux <= sdspmux;
end process;
end case;
end process;
-- process muxdisp
-- process(sdspmux)
-- begin
-- if(sdspmux = "0111") then
-- process muxdisp
process(sdspmux)
begin
if(sdspmux = "0111") then
sledval <=
(sadcregbuf(3),sadcregbuf(2),sadcregbuf(1),sadcregbuf(0));
elsif(sdspmux = "1011") then
sledval <=
(sadcregbuf(7),sadcregbuf(6),sadcregbuf(5),sadcregbuf(4));
elsif(sdspmux = "1101") then
sledval <=
(sadcregbuf(11),sadcregbuf(10),sadcregbuf(9),sadcregbuf(8));
else sledval <= "0000";
end if;
end process;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBDCM is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
p100k : in std_logic
);
end TKBDCM;
begin
process(p100k)
begin
if( rising_edge(p100k)) then
sclkdiv <= sclkdiv+1;
end if;
process(psw,sclkdiv)
variable vdcm : bit;
begin
if(sclkdiv = "000000000000") then
vdcm := '1';
end if;
-- 1f4,320,44c,578,6a4,7d0,8fc,9c4
if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';
elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0';
elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0';
elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0';
elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0';
elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0';
end process;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
begin
process(a)
begin
if (a='1') then
b<= '1';
else
b<= '0';
end if;
end process;
end Behavioral;