Date: March 30, 2011 FA.

vhd Project: FA
1 -- ******************************************************************
2 -- * FILENAME: fa.vhd *
3 -- * AUTHOR: Casey Stark *
4 -- * DATE: 23 March 2011 *
5 -- * PROVIDES: *
6 -- * *
7 -- * - a VHDL with-select dataflow architecture for a full add *
8 -- * component *
9 -- ******************************************************************
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13
14 -- ******************************************************************
15 -- * ENTITY DECLERATION *
16 -- * *
17 -- * X: input bit representing the column input for n-bit number X *
18 -- * Y: input bit representing the column input for n-bit number Y *
19 -- * C: input bit representing the carry-in to the column *
20 -- * CO: output bit representing the carry-out to the next column *
21 -- * S: output bit representing the column sum *
22 -- ******************************************************************
23 entity FA is port (
24 X, Y, C: in std_logic;
25 CO, S: out std_logic
26 );
27 end entity FA;
28
29 -- ******************************************************************
30 -- * ENTITY ARCHITECTURE DESCRIPTION *
31 -- * *
32 -- * - dataflow description using with-select *
33 -- ******************************************************************
34
35 architecture DATAFLOW of FA is
36
37 signal SIG_INPUTS: std_logic_vector(2 downto 0);
38
39 begin
40 -- Combining all inputs onto one std_logic_vector signal
41 SIG_INPUTS <= X&Y&C;
42 with SIG_INPUTS select
43 S <= '1' when B"001",
44 '1' when B"010",
45 '1' when B"100",
46 '1' when B"111",
47 '0' when others;
48
49 with SIG_INPUTS select
50 CO <= '1' when B"011",
51 '1' when B"101",
52 '1' when B"110",
53 '1' when B"111",
54 '0' when others;
55 end architecture DATAFLOW;

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