Design and Simulation of 8 Bit Arithmetic Logic Unit

DESIGN AND SIMULATION OF 8 BIT
ARITHMETIC LOGIC UNIT USING VHDL
A MINOR PROJECT REPORT
Submitted by:
1. SHIVANTH KUMAR(0282092807)
2. BHUVNESH KUMAR(0282092807)
3. MOHAMMAD IHTESHAM(0752092807)
In partial fulfillment for the award of the degree
of the degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
AT
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
G B PANT ENGINEERING COLLEGE
NEW DELHI
DECEMBER 2010
DECLARATION
We hereby declare that the project entitled

“Design and Simulation of 8 Bit Arithmetic Logic Unit”
submitted for the Bachelor of Technology degree is our original work
and the project has not formed for the basis for the award of any degree,
associate ship, fellowship for any other similar titles.
Name Signature
Mohammad Ihtesham
Shivnath Kumar
Bhuvnesh Kumar
PLACE: New Delhi

DATE:
CERTIFICATE
This is to certify that the project entitled “Design and Simulation of 8 Bit
Arithmetic Logic Unit” is the bona fide work carried out by:
• Mohammad Ihtesham (0752092807)
• Shivnath Kumar (0292092807)
• Bhuvnesh Kumar (0282092807)
Students of B.Tech ‘G.B. PANT ENGINEERING COLLEGE’,DELHI

during the year 2010, in partial fulfillment of the requirements for the award of the
degree of BACHELOR IN ELECTRONICS AND COMMUNICATION
ENGINEERING and that the project has not formed the basis for the award
previously of any degree, diploma, associate ship, fellowship or any other similar
title.
SIGNATURE OF THE MENTOR:
Mr. Arun Prakash
(Lecturer)
E.C.E.
PLACE:
DATE: (SEAL OF THE
COLLEGE)
ACKNOWLEDGEMENT
First and foremost, we would like to express our sincere gratitude to our project
mentor Mr. ARUN PRAKASH. We were privileged to experience a sustained
enthusiastic and involved interest from her side. This fueled our enthusiasm even
further and encouraged us to boldly step into what was a totally dark and
unexplored expanse before us.
We would also like to thank our Friends who were ready with positive comments
all the time, whether it was an off-hand comment to encourage us or a constructive
piece of criticism and a special thanks to Mrs. Mamta Jain (HOD ECE) who
arranged the needed requirements for all of us.
Last but not least, we would like to thank the G.B Pant staff members and
Mr.Dhnanjay Kimothi, in particular, for extending a helping hand at every
juncture of need.
Date: 10th December Mr. Mohammad Ihtesham
Place: New Delhi Mr. Shivnath Kumar

Mr. Bhuvnesh Kumar
ABSTRACT
This project includes the designing of 8 –Bit Arithmetic Logic Unit and simulating
its components using VHSIC HDL. The implementation strategies have been
borrowed from most popular Xilinx ISE software. The method applied in this
project is to design and test all the wat through starting with discrete component
design and later VHDL based design on the FPGA.
An arithmetic logic unit (ALU) is the part of a computer processor (CPU) that
carries out arithmetic and logic operations on the operands in computer instruction
words. ALU performs operations such as addition, subtraction and multiplication
of integers and bitwise AND, OR, NOT, XOR and other Boolean operations. The
CPU's instruction decode logic determines which particular operation the ALU
should perform, the source of the operands and the destination of the result.
VHDL is a hardware description language for delineating digital electronic

systems. It arose out of the US government’s Very High Speed Integrated Circuits
(VHSIC) program.
We have presented our work in the use of the VHDL environment. The work
included the development of a number of VHDL models and sequences of input
stimuli and the gathering of performance data from their execution. The instruction
set adopted here is extremely simple that gives an insight into the kind of
hardware, which should be able to execute the set of instructions properly. For
synthesis purpose the targeted FPGA device used is SPARTAN-3. The device can
accept two numbers of 8 bit binary data and can perform logical/arithmetic
operation depending on the 4 bit Operation code given.
8 BIT ALU DESIGN
CONTENTS
CHAPTER 1: INTRODUCTION TO VHDL
 Overview of VHDL……………………………………………4
 History of VHDL………………………………………………5
 VHDL Application Field………………………………………7
 ASIC Development ……………………………………………8
 Concept of VHDL ……………………………………………9
 Abstraction Levels in VHDL………………………………….10
 Description of Abstraction Levels ……………………………11
 Modularity and Hierarchy……………………………………..12
 VHDL Language and Syntax………………………………….13
 VHDL Structural Elements……………………………………14
 Process…………………………………………………………20
 Process Communication Model……………………………….22
CHAPTER 2 : INTRODUCTION TO SYNTHESIS
 What is Logic Synthesis?.............................................................23
 Impact Of HDL & Logic Synthesis…………………………….24
 Design Entry & Synthesis………………………………………24
 Hierarchical Design……………………………………………..24
 Area Optimization………………………………………………25
8 BIT ALU DESIGN
 Speed Optimization……………………………………………..26
 Technology Mapping…………………………………………….26
 Placement…………………………………………………….......27
 Routing……………………………………………………….......27
CHAPTER 3 : PROGRAMMABLE LOGIC DESIGN
 History of Programmable Logic Design…………………………28
 Complex Programmable Logic Device (CPLD)…………………31
 Field Programmable Logic Gate Array (FPGA)…………………32
 Basic Design Process……………………………………………..33
CHAPTER 4 : DESIGN OFARITHMETIC LOGIC UNIT
 Introduction to Arithmetic Logic Unit……………………………35
 Design Overview………………………………………………….36
 Logical Unit……………………………………………………….40
 Arithmetic Unit……………………………………………………44
 Instruction Set…………………………………….……………….45
 Design Implementation……………………………………………46
 VHDL Code……………………………………………………….49
CHAPTER 5 : SYNTHESIS
 Synthesis Report………………………………………………......52
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 Bitgen Report……………………………………………………...68
 RTL Schematic…………………………………………………….73
 Simulation Waveforms…………………………………………….76
 Floorplan…………………………………………………………..78
CHAPTER 6 : EPILOGUE
 Conclusion………………………………………………………….79
 Bibliography………………………………………………………..80
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8 BIT ALU DESIGN
CHAPTER 1
INTRODUCTION TO VHDL
1.1 OVERVIEW OF VHDL
VHDL is an acronym which stands for VHSIC Hardware Description Language.

VHSIC is another acronym which stands for Very High Speed Integrated Circuits.
Hardware description languages can be used in several ways; they can be an

alternative way of representing a circuit diagram for a digital circuit or a higher
level algorithmic ‘program’ that solves a particular problem. Such structural or
behavioral representations are two ways of describing a model of a digital system.
VHDL can be used for documentation, verification, and synthesis of large digital
designs. This is actually one of the key features of VHDL, since the same VHDL
code can achieve all three of these goals, thus saving a lot of effort and reducing
the introduction of errors between translating a specification into an
implementation.
In addition to being used for each of these purposes, VHDL can be used to take
three different approaches to describing hardware. These three different
approaches are the structural, data flow, and behavioral methods of hardware
description. Most of the times a mixture of the three methods are employed and a
complete design will have different sections expressed in different ways. The terms
algorithmic and RTL (Register Transfer Language) are sometimes used for
behavioral and dataflow.
A language capable of such diverse applications has a lot of keywords and a

typical user only uses a small subset of the full language. It also means that there is
often more than one way of doing something in VHDL; proper software tools that
compile and run (i.e simulate) the VHDL model will work with the entire language
as defined in the official Language Reference Manual (LRM) but there will be
some specialist tools that require certain subsets or a particular methodology to be
adhered to. This is most often seen in synthesis tools that try to automate the
conversion of behavioral to structural. Implementation tools that are targeted to a
particular type of hardware such as PLDs may well have restrictions and some of
the less expensive VHDL tools may not completely cover the language. The
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8 BIT ALU DESIGN
Alliance toolset for instance is a free VHDL compiler, simulator and synthesis tool
that runs on PCs; it has several restrictions. In practice such tools will still allow
useful work to be done, within their target environment so the restrictions are
rarely too severe.
VHDL is a standard (VHDL-1076) developed by the IEEE. The language has been
through a couple of revisions, the most widely used version is the 1987 (Std 1076-
1987) version, sometimes referred to as VHDL’87, but also just VHDL. However,
there is a newer revision of the language referred to as VHDL’93. VHDL’93
(adopted in 1994 of course) is fairly new and is still in the process of replacing
VHDL’87. The appendix at the end of this document lists further reading for these
standards and the library has some videotapes that describe the differences; they
are unlikely to be of concern to the neophyte VHDL programmer/designer.
1.2 VHDL HISTORY

1.2.1 THE REQUIREMENT
The development of VHDL was initiated in 1981 by the United States Department
of Defence to address the hardware life cycle crisis. The cost of reprocuring
electronic hardware as technologies became obsolete was reaching crisis point,
because the function of the parts was not adequately documented, and the various
components making up a system were individually verified using a wide range of
different and incompatible simulation languages and tools. The requirement was
for a language with a wide range of descriptive capability that would work the
same on any simulator and was independent of technology or design methodology.
1.2.2 STANDARDIZATION
The standardization process for VHDL was unique in that the participation and
feedback from industry was sought at an early stage. A baseline language (version
7.2) was published 2 years before the standard so that tool development could
begin in earnest in advance of the standard. All rights to the language definition
were given away by the DoD to the IEEE in order to encourage industry
acceptance and investment.
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8 BIT ALU DESIGN
1.2.3 ASIC MANDATE
DoD Mil Std 454 mandates the supply of a comprehensive VHDL description with
every ASIC delivered to the DoD. The best way to provide the required level of
description is to use VHDL throughout the design process.
1.2.4 VHDL 1993
As an IEEE standard, VHDL must undergo a review process every 5 years (or
sooner) to ensure its ongoing relevance to the industry. The first such revision was
completed in September 1993, and this is still the most widely supported version of
VHDL.
1.2.5 VHDL 2000 AND VHDL 2002
One of the features that was introduced in VHDL-1993 was shared variables.
Unfortunately, it wasn’t possible to use these in any meaningful way. A working
group eventually resolved this by proposing the addition of protected types to
VHDL. VHDL 2000 Edition is simply VHDL-1993 with protected types.
VHDL-2002 is a minor revision of VHDL 2000 Edition. There is one significant

change, though: the rules on using buffer ports are relaxed, which makes these
much more useful than hitherto.
1.2.6 VHPI
In 2007, an amendment to VHDL 2002 was created. This introduces the VHDL
Procedural Interface (VHPI) and also makes a few minor changes to the text of
VHDL 2002. Apart from the VHPI itself, no new features were added to VHDL.
The VHPI allows tools programmable access to a VHDL model before and during
simulation. In other words, you can write programs in a language such as C that
interact with a VHDL simulator.
1.2.7 VHDL-2008
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8 BIT ALU DESIGN
Since the publication of the first IEEE standard in 1987 several revised versions
have appeared. The first, in 1993, had the most extensive changes. VHDL 2000
Edition introduced protected types and VHDL-2002 contains mainly minor
changes. VHDL-2008 is the name of the new version of VHDL. As with the earlier
revisions, this doesn’t radically alter the language, but it does provide a wider set
of modifications than previously.
A draft of the proposed revision (version 4.0) was delivered by Accellera to the
IEEE in 2008. The standard is now available from the IEEE and is known as IEEE
Std. 1076-2008.
1.3 VHDL APPLICATION FIELD

VHDL is used mainly for the development of Application Specific Integrated
Cicuits (ASICs). Tools for the automatic transformation of VHDL code into a gate-
level netlist were developed already at an early point of time. This transformation
is called synthesis and is an integral part of current design flows.
For the use with Field Programmable Gate Arrays (FPGAs) several problems exist.
In the first step, 7ehavio equations are derived from the VHDL description, no
matter, whether an ASIC or a FPGA is the target technology. But now, this
7ehavio code has to be partitioned into the configurable logic blocks (CLB) of the
FPGA. This is more difficult than the mapping onto an ASIC library. Another big
problem is the routing of the CLBs as the available resources for interconnections
are the bottleneck of current FPGAs.
While synthesis tools cope pretty well with complex designs, they obtain usually
only suboptimal results. Therefore, VHDL is hardly used for the design of low
complexity Programmable Logic Devices (PLDs).
VHDL can be applied to model system 7ehavior independently from the target
technology. This is either useful to provide standard solutions, e.g. for micro
controllers, error correction (de-)coders, etc, or behavioural models of
microprocessors and RAM devices are used to simulate a new device in its target
environment.
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8 BIT ALU DESIGN
An ongoing field of research is the hardware/software co design. The most

interesting question is which part of the system should be implemented in software
and which part in hardware. The decisive constraints are the costs and the resulting
performance.
1.4 ASIC DEVELOPMENT

The development of VHDL models starts with their specification which covers
functional aspects and the timing behavior. Sometimes a behavioral VHDL model
is derived from there, yet synthesizable code is frequently requested right from the
beginning. VHDL code can be simulated and checked for the proper functionality.
If the model shows the desired behavior, the VHDL description will be
synthesized. A synthesis tool selects the appropriate gates and flip-flops from the
specified ASIC library in order to reproduce the functional description. It is
essential for the synthesis procedure that the sum of the resulting gate delays along
the longest paths (from the output to the input of every Flip Flop) is less than the
clock period.
As soon as a model built of ASIC library elements is available, a simulation on

gate level can be performed. Now gate and propagation delays have to be taken
into account. Delay values can be included in each VHDL model description, i.e.
the designer receives the first clues about maximum clock frequency and critical
paths after synthesis, already.
The propagation delay along the signal wires have to be estimated first because the
real values are available after the layout is finished. The process of feeding these
values back into the VHDL model is called back annotation. Once again it must be
checked, whether the circuit fulfills the specified timing constraints.
1.5 CONCEPTS OF VHDL
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8 BIT ALU DESIGN
EXECUTION OF STATEMENTS:
SEQUENTIAL
CONCURRENT
METHODOLOGIES
ABSTRACTION
MODULARITY
HIERARCHY
VHDL distinguishes itself from other languages by the way assignments are
executed because two basic types of statements are known:
Sequential statements are executed one after another, like in software

programming languages. Subsequent statements can override the effects of
previous statements this way. The order of the assignment must be considered
when sequential statements are used.
Concurrent statements are active continuously. So the order of the statements is

not relevant. Concurrent statements are especially suited model the parallelism of
hardware.
VHDL features also three important modeling techniques:
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Abstraction allows for the description of different parts of a system with different
amount of detail. Modules which are needed only for the simulation do not have to
be described as detailed as modules that might be synthesized.
Modularity enables the designer(s) to split big functional blocks and to write a
model for each part.
Hierarchy lets the designer build a design out of sub modules which may consist
of several sub modules, themselves. Each level of hierarchy may contain modules
of different abstraction levels. The sub modules of these models are present in the
next lower hierarchical level.
1.6 ABSTRACTION LEVELS AND VHDL
VHDL is applicable to the upper three abstraction levels. It is not suitable to

describe a layout. The design entry in behavioral and RT level is usually done by
text editors. Graphical tools are also available but experienced users often find it
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easier to write the code by hand. On the gate level, a schematic is modified as
VHDL netlist descriptions tend to become too complex pretty soon.
The transition from an upper abstraction level to a lower one is supported more or
less efficiently by software.
Behavioral synthesis is still a dream of many researchers as only very simple

behavior models are synthesizable. A common application is the design of RAM
cells for the target technology, where only the generic parameters (width, depth,
number of ports, (a) synchronous ...) need to be specified.
Logic synthesis, however, has been perfected in recent years. As long as the
designer confines himself to certain simple VHDL constructs that are sufficient for
RT level descriptions, the synthesis tools will be able to reproduce the behavior in
the logic level.
As a result of the ongoing research in efficient place and route algorithms the step
from the logic level to the final layout has been widely automated for digital
standard cell designs.
1.7 DESCRIPTION OF ABSTRACTION LEVELS

In the behavior level, complete systems can be modeled. Bus systems or complex
algorithms are described without considering synthesizability. The stimuli for
simulation of RTL models are described in the behavior level, for example. Stimuli
are signal values of the input ports of the model and are described in the test bench,
sometimes called validation bench.
The designer has to take great care to find a consistent set of input stimuli that do
not contradict the specification. The responses of the model have to be compared
with the expected values which, in the simplest case, can be done with the help of a
waveform diagram that shows the simulated signal values.
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On the RT level, the system is described in terms of registers and logic that
calculates the next value of the storage elements. It is possible to split the code into
two blocks (cf. process statement) that contain either purely combinational logic or
registers. The registers are connected to the clock signal and provide for
synchronous behavior. In practice, the strict separation of Flip Flops from
combinational logic is often annulated and clocked processes describe the registers
and the corresponding update functions.
The gate netlist is generated from the RT description with the help of a synthesis
tool. For this task, a cell library for the target technology which holds the
information about all available gates and their parameters (fan-in, fan-out, delay) is
needed.
Based upon this gate netlist the circuit layout is generated. The resulting wire
lengths can be converted into propagation delays which can be fed back into the
gate level model (back annotation). This allows for thorough timing simulations
without the need for additional simulator software.
1.8 MODULARITY AND HIERARCHY

Modularity allows the partitioning of big functional blocks into smaller units and
to group closely related parts in self-contained sub blocks, so called modules. This
way, a complex system can be divided into manageable subsystems. The
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guidelines for partitioning can differ from design to design. Most of the time
functional aspects are considered as partitioning constraint. The existence of well
defined subsystems allows several designers to work in parallel on the same
project as each designer will view his part as a new, complete system.
Hierarchy allows the building of a design out of modules which themselves may be
built out of (sub-) modules. One level of a hierarchical description contains one or
more modules; each module can even have different degrees of abstraction. These
modules can themselves contain sub modules which would be present the next
lower hierarchical level.
Modularity and hierarchy help to simplify and organize a design project.

Additional advantages are that different implementation alternatives can be
examined for the modules, e.g. in a simulation. Only the corresponding component
instantiation needs to be changed for this in the overall model. Also analogues
interfaces can be modeled in VHDL and added to the system model for simulation.
Sometimes, simulation models of the devices that will be connected to the new
design exist and can be used for a simulation of the design under test in its real
working environment.
1.9 VHDL LANGUAGE AND SYNTAX

VHDL is generally case insensitive which means that lower case and upper case
letters are not distinguished. This can be exploited to define own rules for
formatting the VHDL source code. VHDL keyword could for example be written
in lower case letters and self defined identifiers in upper case letters. This
convention is valid for the following slides.
Statements are terminated in VHDL with a semicolon. That means as many line
breaks or other constructs as wanted can be inserted or left out. Only the
semicolons are considered by the VHDL compiler.
List are normally separated by commas. Signal assignments are notated with the
composite assignment operator ‘<=’. Self defined identifier as defined by the
VHDL 87 standard may contain letters, numbers and underscores and must begin
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with a letter. Further no VHDL keywords may be used. The VHDL 93 standard
allows defining identifiers more flexible as the next slide will show.
-- Example VHDL Code — Case insensitive
signal mySignal: bit; -- an example Comments: ‘—‘ until end of line

signal
Statements are terminated by ‘;’
Mysignal <= ‘0’, -- start
(may span multiple lines)
with ‘0’
List delimiter: ‘,’
‘1’ AFTER 10 ns, -- and
toggle after Signal assignment: ‘<=’
‘0’ after 10 ns, -- User defined names:

every 10 ns
letters, numbers, underscores start with
‘1’ after 10 ns; a letter
1.10 VHDL Structural Elements

1.10.1 ENTITY DECLARATION:
The interface between a module and its environment is described within the entity
declaration which is initiated by the keyword ' entity '. It is followed by a user-
defined, (hopefully) descriptive name, in this case: HALFADDER. The interface
description is placed between the keyword ' is ' and the termination of the entity
statement which consists of the keyword ' end ' and the name of the entity. In the
new VHDL'93 standard the keyword ' entity ' may be repeated after the keyword '
end ' for consistency reasons.
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The input and output signal names and their data types are defined in the port
statement which is initiated by the keyword ' port '. The list of ports is enclosed in a
'(' ')' pair. For each list element the port name(s) is given first, followed by a ':', the
port mode and the data type. Within the list, the ';' symbol is used to separate
elements, not to terminate a statement. Consequently, the last list element is not
followed by a ';'!
entity HALFADDER is Interface description
port( No behavioral definition
A, B: in bit;
SUM, CARRY: out bit);
end HALFADDER;
-- VHDL'93: end entity HALFADDER ;

entity ADDER is Linking via port signals
port( data types
A, B: in integer range 0 signal width

to 3;
signal direction
SUM: out integer range 0
to 3;
CARRY: out bit );
end ADDER;
Several ports with the same mode and data type can be declared by a single port
statement when the port names are separated by ','. The port mode defines the data
flow (in: input, i.e. the signal influences the module behavior; out: output, i.e. the
signal value is generated by the module) while the data type determines the value
range for the signals during simulation.
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Entity declaration specifies the following:
 The name of the entity.
 A set of generic declarations specifying instance-specific parameters.
 A set of port declarations defining inputs and outputs of the hardware

design.
1.10.2 ARCHITECTURE
The architecture contains the implementation for an entity which may be either a
behavioral description (behavioral level or, if synthesizable, RT level) or a
structural netlist or a mixture of those alternatives. An architecture is strictly linked
to a certain entity. An entity, however, may very well have several architectures
underneath, e.g. different implementations of the same algorithm or different
abstraction levels. Architectures of the same entity have to be named differently in
order to be distinguishable. The name is placed after the keyword ‘ architecture ‘
which initiates an architecture statement. ‘RTL’ was chosen in this case.
Entity HALFADDER is Implementation of the design
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port( A, B: in bit; Always connected with a specific entity
SUM, CARRY: out bit); one entity can have several

17rchitectures
end HALFADDER;
entity ports are available as signals
architecture RTL of HALFADDER is
within the architecture
begin
Contains concurrent statements
SUM <= A xor B;
CARRY <= A and B;
end RTL;
-- VHDL’93: end architecture RTL ;
It is followed by the keyword ‘ of ‘ and the name of entity that is used as interface
(‘HALFADDER’). The architecture header is terminated by the keyword ‘ is ‘, like
in entity statements. In this case, however, the keyword ‘ begin ‘ must be placed
somewhere before the statement is terminated. This is done the same way as in
entity statements: The keyword ‘ end ‘, followed by the architecture name. Once
again, the keyword ‘ architecture ‘ may be repeated after the keyword ‘ end ‘ in
VHDL’93. As the VHDL code is synthesizable, RTL was chosen as architecture
name. In case of this simple function, however, there is no difference to behavioral
(algorithmic) description. We will use ‘BEHAVE’, ‘RTL’, ‘GATE’, ‘STRUCT’
and ‘TEST’ to indicate the abstraction level and the implemented behavior,
respectively. The name ‘EXAMPLE’ will be used whenever the architecture shows
the application of new VHDL elements and is not associated with a specific entity.
1.10.3 ARCHITECTURE STRUCTURE

Each architecture is split into an optional declarative part and the definition part.
The declarative part is located between the keywords ' is ' and ' begin '. New
objects that are needed only within the architecture constants, data types, signals,
subprograms, etc. can be declared here. The definition part is initiated by the
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8 BIT ALU DESIGN
keyword ' begin ' and holds concurrent statements. These can be simple signal
assignments, process statements, which group together sequential statements, and
component instantiations. Concurrency means that the order in which they appear
in the VHDL code is not important. The signal SUM, for example, gets always the
result of (3 + 7), independently of the location of the two assignments to the
signals DIGIT_A and DIGIT_B.
architecture EXAMPLE of Declarative part:

STRUCTURE is
data types
subtype DIGIT is integer range 0 to 9; constants
constant BASE: integer := 10; additional signals
signal DIGIT_A, DIGIT_B: DIGIT; ("actual" signals)
signal CARRY: DIGIT; components
begin ...
DIGIT_A <= 3; Definition part (after 'begin'):

signal assignments
SUM <= DIGIT_A + DIGIT_B;
processes
DIGIT_B <= 7;
component instantiations
CARRY <= 0 when SUM < BASE else
1; concurrent statements:
order not important

end EXAMPLE
Signal assignments are carried out by the signal assignment operator ' <= '. The
symbol represents the data flow, i.e. the target signal whose value shall be updated
is placed on the left side of the operator. The right side holds an expression that
evaluates to the new signal value. The data types on the left and on the right side
have to be identical. Please remember that the signals that are used in this example
were defined implicitly by the port declaration of the entity.
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Multiple architectures can be created for a particular entity. For example, we might
wish to create several architectures for a particular entity with each architecture
optimized with respect to a design goal:
 Performance
 Area
 Power consumption
 Ease of simulation
1.11 PROCESS
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Behavioral descriptions are supported with the process statement. The process
statement can appear in the body of an architecture declaration just as the signal
assignment statement does. The contents of the process statement can include
sequential statements like those found in software programming languages. These
statements are used to compute the outputs of the process from its inputs.
Sequential statements are often more powerful, but sometimes have no direct
correspondence to a hardware implementation. The process statement can also
contain signal assignments in order to specify the outputs of the process.
entity AND_OR_XOR is Contains sequentially executed

statements
port (A,B : in
bit; Exist within an architecture, only
Z_OR, Z_AND, Z_XOR : out Several processes run concurrently

bit);
Execution is controlled either via
end AND_OR_XOR;
sensitivity list (contains trigger
architecture RTL of AND_OR_XOR signals), or
is
wait-statements
begin
The process label is optional
A_O_X: process (A, B)
Begin
Z_OR <= A or B;
Z_AND <= A and B;
Z_XOR <= A xor B;
end process A_O_X ;
end RTL;
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Because the statements within an architecture operate concurrently another VHDL

construct is necessary to achieve sequential behavior. A process, as a whole, is
treated concurrently like any other statement in an architecture and contains
statements that are executed one after another like in conventional programming
languages. In fact it is possible to use the process statement as the only concurrent
VHDL statement. The execution of a process is triggered by events. Either the
possible event sources are listed in the sensitivity list or explicit wait statements are
used to control the flow of execution. These two options are mutually exclusive,
i.e. no wait statements are allowed in a process with sensitivity list. While the
sensitivity list is usually ignored by synthesis tools, a VHDL simulator will invoke
the process code whenever the value of at least one of the listed signals changes.
Consequently, all signals that are read in a purely combinational process i.e. that
influence the behavior, have to be mentioned in the sensitivity list if the simulation
is to produce the same results as the synthesized hardware. Of course the same is
true for clocked processes, yet new register values are to be calculated with every
active clock edge, only. Therefore the sensitivity list contains the clock signal and
asynchronous control signals (e.g. reset).
A process statement starts with an optional label and a ':' symbol, followed by the
process keyword. The sensitivity list is also optional and is enclosed in a '(' ')' pair.
Similar to the architecture statement, a declarative part exists between the header
code and the keyword ' begin '. The sequential statements are enclosed between
“begin” and ' end process '. The keyword ' process ' has to be repeated! If a label
was chosen for the process, it has to be repeated in the end statement, as well.
Important notes regarding processes:
- Processes execute in zero time.

- Processes execute endlessly unless broken by:
- WAIT statement or
- Sensitivity list (Processes with a sensitivity list have an implied WAIT at the
end)
- An Architecture can have multiple processes.
- All processes execute concurrently.
- Variables are local to the process in which they are declared.
- Variables may only be declared within processes.
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8 BIT ALU DESIGN
1.12 PROCESS COMMUNICATION MODEL
Processes are concurrent

statements
Several processes
run parallel
linked by signals in the

sensitivity list
sequential execution of
statements
Link to processes of other

entity/architecture pairs via
entity interface
Process statements are concurrent statements while the instructions within each
process are executed sequentially, i.e. one after another. All processes of a VHDL
design run in parallel, no matter in which entity or hierarchy level they are located.
They communicate with each other via signals. These signals need to be ports of
the entities if processes from different architectures depend from another.
A group of processes will be executed concurrently since the process is a

concurrent statement, it usually contains sequential ststements. We can also group
a block of concurrent statements together and specify when they are to be
executed.
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8 BIT ALU DESIGN
CHAPTER 2
INTRODUCTION TO SYNTHESIS
2.1 WHAT IS LOGIC SYNTHESIS?
Logic synthesis is the process of converting a high-level description of design into
an optimized gate-level representation. Logic synthesis uses standard cell library
which have simple cells, such basic logic gates like and , or and nor, or macro
cells, such as adder, muxes, memory, and flip-flops. Standard cells put together is
called technology library. Normally technology library is known by the transistor
size (0.18u, 90mm). A circuit description is written in Hardware Description
Language (HDL) such as VHDL. The designer should first understand the
architectural description. Then he should consider design constraints such as
timing area, testability, and power.
The synthesis and simulation Design provides a general overview of designing

Field Programmable Gate Arrays (FPGA) devices with Hardware Description
Languages (HDLs).
Synthesis is a broad term often used to describe very different tools. Synthesis can
include silicon compilers and function generators used by ASIC vendors to
produce regular RAM and ROM type structures. Synthesis in the context of this
tutorial refers to generating random logic structures from VHDL descriptions. This
is best suited to gate arrays and programmable devices such as FPGAs. Sy nthesis
is not an easy task. It is vital to tackle High Level Design using VHDL with
realistic expectations of synthesis. Other tools which use VHDL, such as synthesis,
23
8 BIT ALU DESIGN
will make their own interpretation of the VHDL language. This is an IEEE
standard for VHDL synthesis (IEEE Std. 1364.1-2002) but no vendor adheres
strictly to it. It is not sufficient that the VHDL is functionally correct, it must be
written in such a way that it directs the synthesis tool to generate good hardware,
and moreover, the VHDL must be matched to the idiosyncrasies of the particular
synthesis tool being used. We shall tackle some of these idiosyncrasies in this
VHDL tutorial.
2.2 IMPACT OF HDL AND LOGIC SYNTHESIS

High-level design is less prone to human error because designs are described at a
higher level of abstraction. High-level design is done without significant concern
about design constraints. Conversion from high-level design to gates is done by
synthesis tools, while doing so it used various algorithms to optimize the design as
a whole. This removes the problem with varied designer styles for the different
blocks in the design and suboptimal designs. Logic synthesis tools allow
technology independent design. Design reuse is possible for the technology-
independent descriptions.
2.3 DESIGN ENTRY AND SYNTHESIS

You can enter a design with a schematic editor or a text-based tool. Design entry
begin with a design concept, expressed as a drawing or functional description.
From the original design, a netlist is created, then synthesized and translated into a
native generic object (NGO) file. This file is fed into Xilinx software program
called NGD build, which produces a logical native generic description (NGD) file.
The following figure shows the design entry and synthesis process
2.4 HIERARCHICAL DESIGN

Design hierarchy is important in both schematic and HDL entry for the following
reasons:
 Helps you conceptualize your design
 Adds structure to your design.
 Promotes easier design debugging.
24
8 BIT ALU DESIGN
 Makes it easier to combine different design entry methods (schematic, HDL,

or state directory.)
 Makes it easier to design incrementally, which consists of designing,

implementing, and verifying individual parts of a design in stages.
 Reduces optimization time.
 Facilitates concurrent design, which is the process of dividing a design

among a number of people who develop different parts of the design in
parallel.
2.5 AREA OPTIMIZATION

Area optimization is well studied field in digital electronics. Early technique
addressed simple matrix-based manipulation for the Boolean algebra. Later
25
8 BIT ALU DESIGN
developments incorporated optimizations based on do not care conditions. The

optimizations may be – a general purpose one or targeted at particular structures
(e.g. Programmable Logic Array). Also under lying technology strongly affects the
optimization.
Where area optimization is more difficult is where a particular device technology

is used. For example, the Xilinx FPGA operates a number of CLBs(). Each CLB
can compute upto five inputs Boolean expressions. If the expression involves six
inputs then a second CLB is needed. If four inputs are needed then the chip area is
wasted.
2.6 SPEED OPTIMIZATION

Some measure of speed optimization is usually, as the area optimization remove
redundant circuitry and can shorten the critical path of the circuit however, further,
speed optimization can be performed.
As common approach is to identify the critical path and to work on reducing that a
simple optimization might be replaced each component on the critical path with a
higher rated (i.e. faster but more power intensive equivalent) but functionally
equivalent component from the library. Other optimization techniques might be to
strip out string inverters from a design where, e.g. AND gates are slower than Ors
gates. To attempt to replace all ANDs with OR.
Speed optimization is usually applied after area optimization has taken place. It
improves the performance, but only to a certain extent. If after speed optimization
the circuit still does not meet the required specifications, then the designer must go
back and restructure behavioral specifications with a structural or data flow.
2.7 TECHNOLOGY MAPPING

After logic optimization has produced the optimized network, technology mapping
transform this network into the final circuit. This is done by selecting pieces of the
network that can be implemented by one of the available circuit elements, and
specifying how there are to be interconnected. The circuit is optimized to reduce a
cost function that typically incorporates measures of both area and delay.
Conventional approaches to technology mapping have focused on using circuit
element from a set of simple gates, such as a standard cell library. The complex
26
8 BIT ALU DESIGN
logic block used in FPGA presents difficulties for library-based approaches

because they can implement a large number of functions.
2.8 PLACEMENT
The next step after technology mapping is placement of logic blocks. A number of
efficient techniques has been developed, which can be easily adopted to use for
FPGAs.
2.9 ROUTING
Routing refers to the process of inter-connecting the various logic block of the
FPGA. Some of the terms used in the routing are:
 Pin- a logic block input or output.
 Connection- a pair of logic blocks pin that are electrically connected.
 Net- a set of logic pins that are to be electrically connected. A net can be
divided into one or more connection.
 Wire segment- a straight segment of wire that is used to from a part of a

connection.
 Routing switch- a programmable switch that is used to electrically connect

two wire segments.
 Track- a straight section of wire that spans the entire width or length of a
routing channel. A track can be composed of a number of wire segments of
various lengths.
 Routing channel- the rectangular area that lies between two rows or two
column of logic blocks. A routing channel contains a number of tracks.
27
8 BIT ALU DESIGN
CHAPTER 3
PROGRAMMABLE LOGIC DESIGN
3.1 HISTORY
By the late 1970s, standard logic devices were all the rage, and printed circuit
boards were loaded with them. Then someone asked, “What if we gave designers
the ability to implement different interconnections in a bigger device?” This would
allow designers to integrate many standard logic devices into one part.
To offer the ultimate in design flexibility, Ron Cline from Signetics (which was
later purchased by Philips and then eventually Xilinx) came up with the idea of
two programmable planes. These two planes provided any combination of “AND”
and “OR” gates, as well as sharing of AND terms across multiple ORs.
This architecture was very flexible, but at the time wafer geometries of 10 μm
made the input-to-output delay (or propagation delay) high, which made the
devices relatively slow. The features of the PLA were:
• Two programmable ground planes
• Any combination of ANDs/ORs
• Sharing of AND terms across multiple ORs
• Highest logic density available to user
• High fuse count; slower than PALs
• Programmable logic array
28
8 BIT ALU DESIGN
Figure: Programmable Logic Array
MMI (later purchased by AMD™) was enlisted as a second source for the PLA
array. After fabrication issues, it was modified to become the programmable array
logic (PAL) architecture by fixing one of the programmable planes.
This new architecture differed from that of the PLA in that one of the
programmable planes was fixed – the OR array. PAL architecture also had the
added benefit of faster tPD and less complex software, but without the flexibility of
the PLA structure. Other architectures followed, such as the PLD. This category of
devices is often called Simple PLD.
• One programmable plane: AND/Fixed OR
• Finite combination of ANDs/ORs
• Medium logic density available to user
• Lower fuse count; faster than PLAs (at the time, fabricated on a 10 μM process)
• Programmable array logic
29
8 BIT ALU DESIGN
Figure: Programmable Array Logic
The architecture had a mesh of horizontal and vertical interconnect tracks. At each
junction was a fuse. With the aid of software tools, designers could select which
junctions would not be connected by “blowing” all unwanted fuses. (This was done
by a device programmer, but more commonly these days is achieved with ISP).
Input pins were connected to the vertical interconnect. The horizontal tracks were
connected to AND-OR gates, also called “product terms”. These in turn connected
to dedicated flip-flops, whose outputs were connected to output pins.
PLDs provided as much as 50 times more gates in a single package than discrete
logic devices! This was a huge improvement, not to mention fewer devices needed
in inventory and a higher reliability over standard logic. PLD technology has
moved on from the early days with companies such as Xilinx producing ultra-low-
power CMOS devices based on flash memory technology.
30
8 BIT ALU DESIGN
3.2 COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLDS)

Complex programmable logic devices (CPLDs) extend the density of SPLDs. The
concept is to have a few PLD blocks or macro-cells on a single device with a
general-purpose interconnect in-between. Simple logic paths can be implemented
within a single block. More sophisticated logic requires multiple blocks and uses
the general-purpose interconnect in-between to make these connections. CPLDs
feature:
• Central global interconnect
• Simple, deterministic timing
• Easily routed
• PLD tools add only interconnect
• Wide, fast complex gating
Figure: CPLD Architecture
3.3 FIELD PROGRAMMABLE GATE ARRAYS (FPGA)

31
8 BIT ALU DESIGN
In 1985, Xilinx introduced a completely new idea: combine the user control and
time to market of PLDs with the densities and cost benefits of gate arrays.
Customers liked it, and the FPGA was born. Today Xilinx is the number one
FPGA vendor in the world. An FPGA is a regular structure of logic cells (or
modules) and interconnect, which is under your complete control. This means that
you can design, program, and make changes to your circuit whenever you wish.
With FPGAs now exceeding the 10 million gate limit (the Xilinx Virtex™-4 FPGA
is the current record holder), you can really dream big. FPGAs feature:
• Channel based routing
• Post layout timing
• Tools more complex than CPLDs
• Fine grained
• Fast register pipelining
Figure: FPGA Architecture
3.4 BASIC DESIGN FLOW
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8 BIT ALU DESIGN
Design entry or design specification can be in the form of schematic capture or

hardware description language ( HDL). In schematic form, after determining the
capture tool and the manufacturer’s library, designer can connect the gates from
library with wires and then generates netlist, which is the textual description of the
circuit. Schematic capture is not feasible for large designs because it is not
scalable, not reusable, strongly vendor dependent and hard to maintain. In HDL
design entry, the design is entered in high level description language emphasizing
design’s function or behavior and then synthesized by the vendor independent tool
and netlist is generated. The design is more maintainable, scalable and reusable
than schematic design entry.
In design implementation, the first step is translation of low level and generic
netlist file into device specific resources. After translation step, mapping step
checks the design according to device specific rules, add further logic or make
replications to meet the timing requirements using device resources. At last, in
place and route step, already allocated resources are distributed along FPGA taking
into account the physical constraints and routing resources. At this point physical
layout is determined and timing information for design entities and interconnects
(Back Annotation) is available. After routing, the device is ready to be
programmed. In device programming stage, the SRAM based FPGA’s
configuration, which is volatile after power on and also defining the logic and
interconnect, is programmed to a Programmable Read Only Memory (PROM)
device with part name xc18v02. Design specification is a parallel process to design
development. Design entry in either schematic or HDL form can be simulated
behaviorally, while it can be tested based on the code syntax. After synthesis
phase, generated netlist format can be simulated functionally by providing test
vectors and tested by checking the desired output vector. Timing simulation comes
after the place and route phase using back annotation.
33
8 BIT ALU DESIGN
CHAP
34
8 BIT ALU DESIGN
TER 4
DESIGN OF ARITHMETIC LOGIC UNIT
4.1 INTRODUCTION TO ALU:
An arithmetic logic unit (ALU) is the part of a computer processor (CPU) that
carries out arithmetic and logic operations on the operands in computer instruction
words. ALU performs operations such as addition, subtraction and multiplication
of integers and bitwise AND, OR, NOT, XOR and other Boolean operations. The
CPU's instruction decode logic determines which particular operation the ALU
should perform, the source of the operands and the destination of the result.
The width in bits of the words which the ALU handles is usually the same as that
quoted for the processor as a whole whereas its external buses may be narrower.
Floating point operations are usually done by a separate "floating point unit". Some
processors use the ALU for address calculations (e.g. incrementing the program
counter), others have separate logic for this.
In some processors, the ALU is divided into two units, an arithmetic unit (AU) and
a logic unit (LU). Some processors contain more than one AU for example, one for
fixed point operations and another for floating point operations. (In personal
computers floating point operations are sometimes done by a floating point unit on
a separate chip called a numeric coprocessor.)
Typically, the ALU has direct input and output access to the processor controller,
main memory (random access memory or RAM in a personal computer), and
35
8 BIT ALU DESIGN
input/output devices. Inputs and outputs flow along an electronic path that is called
a bus. The input consists of an instruction word (sometimes called a machine
instruction word) that contains an operation code (sometimes called an "op code"),
one or more operands, and sometimes a format code. The operation code tells the
ALU what operation to perform and the operands are used in the operation. (For
example, two operands might be added together or compared logically.) The
format may be combined with the op code and tells, for example, whether this is a
fixed point or a floating point instruction. The output consists of a result that is
placed in a storage register and settings that indicate whether the operation was
performed successfully. (If it isn't some sort of status will be stored in a permanent
place that is sometimes called the machine status word.)
In general, the ALU includes storage places for input operands, operands that are
being added, the accumulated result (stored in an accumulator), and shifted results.
The flow of bits and the operations performed on them in the subunits of the ALU
is controlled by gated circuits. The gates in these circuits are controlled by a
sequence logic unit that uses a particular algorithm or sequence for each operation
code. In the arithmetic unit, multiplication and division are done by a series of
adding or subtracting and shifting operations. There are several ways to represent
negative numbers. In the logic unit, one of 16 possible logic operations can be
performed such as comparing two operands and identifying where bits don't match.
The design of the ALU is obviously a critical part of the processor and new
approaches to speeding up instruction handling are continually being developed.
4.2 DESIGN OVERVIEW

4.2.1 INPUT SIGNALS
The Arithmetic and logic Unit has two eight-bit input signals Accumulator_in(7 -0)
and Data_in(7 -0) taken and controlled from trainer switches and loaded into
registers Accumulator and Data respectively.
4.2.2 INTERNALLY INITIATED SIGNALS
clk- Clock Input: This is a signal from the FPGA internal clock.
4.2.3 MODULES
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8 BIT ALU DESIGN
Figure shows the block diagram of the Arithmetic Logic Unit, which consists of
various modules interconnected by an 8-bit internal data bus. Each of these
modules along with its sub components is described in this section.
 REGISTER FILE
o Two 8 –bit input registers and one 8- bit output register.
o Input registers , Accumuulator_in(7-0) and Data_in(7-0)
 ARITMETIC LOGIC UNIT
o 8 –Bit ALU (logical operations like AND, XOR etc.. arithmetic

operations like increment, addition etc….)
4.2.4 REGISTER FILE
Arithmetic and Logical instructions require three source registers and one
destination register. Of the two source registers, three are used as input registers
and the other is used as an instruction register. A total of 4 bits would be required
for any ALU instruction. The actual implementation of any instruction is done with
the instruction register and two 3:8 decoders. These decoder outputs can be used to
drive the required output.
4.2.5 ARITHMETIC LOGIC UNIT
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8 BIT ALU DESIGN
Figure shows in detail the ALU, the 8-bit inputs A, B and the output Z. The ALU
takes two operands from the A and B registers. The result register Z is used to hold
the ALU output. The ALU has the capability to perform 9 operations as shown in
the figure. After every ALU instruction, the output register is updated.
The various units inside the ALU are described below:
 Adder/Subtractor: The 8-bit adder/subtractor in the ALU is a Reduced Full

Adder built by using universal gates. A ripple carry adder is used in which
the carry signal propagates from the LSB to the MSB and coming out as
Cout.
 Logical Unit: We provide all the possible logical operations (nand nor,
exor,not,and,or,xnor) in the ALU.
38
8 BIT ALU DESIGN
Figure: Arithmetic Logic Unit
39
8 BIT ALU DESIGN
4.3 LOGICAL UNITS:

4.3.1 AND GATE:
(1) Instruction Format: Oprand1 AND Oprand2

(2) Function: Oprand1 and Oprand2 are two register inputs. This operator performs
the bitwise AND operation, and put the result in Oprand1. The truth table defines
the behavior of each bit operation shown in figure 1(a).
The circuit symbol is shown in figure 1(b)
4.3.2 OR GATE:
(1) Instruction Format: OR Oprand1 Oprand2

the bitwise OR operation, and put the result in Oprand1. The truth table defines the
behavior of each bit operation shown in figure 2(a).
4.3.3. XOR GATE:

40
8 BIT ALU DESIGN
(1)Instruction Format: Oprand1 XOR Oprand2.

(2)Function: Oprand1 and Oprand2 are two register inputs. This operator performs
the bitwise XOR operation, and put the result in Oprand1. The truth table defines
The circuit symbol is shown in figure 3(b).
4.3.4. NOT GATE:
(1) Instruction Format: NOT Oprand1

(2) Function: Oprand1 is a register input. This operator performs the bitwise NOT
operation on Oprand1. The truth table defines the behavior of each bit operation
shown in figure 4(a).
The circuit symbol is shown in figure 4(b).
4.3.5 NOR GATE:
41
8 BIT ALU DESIGN
(1) Instruction Format: Oprand1NOR Oprand2

the bitwise NOR operation, and put the result in Oprand1. The truth table defines
`
4.3.6 NAND GATE:
(1) Instruction Format: Oprand1NAND Oprand2

the bitwise NAND operation, and put the result in Oprand1. The truth table defines
4.3.7 EXCLUSIVE –NOR GATE:
42
8 BIT ALU DESIGN
(1) Instruction Format: Oprand1 XNOR Oprand2

the bitwise XNOR operation, and put the result in Oprand1. The truth table defines
4.4 Arithmetic Unit:
4.4.1 ADDER AND SUBTRACTOR CIRCUIT:
The addition and subtraction operations can be done using an Adder-Subtractor

circuit. The figure shows the logic diagram of a 8-bit Adder-Subtractor circuit. The
circuit has a mode control signal M which determines if the circuit is to operate as
an adder or a subtractor.
43
8 BIT ALU DESIGN
Each XOR gate receives input M and one of the inputs of B, i.e., Bi. To understand
the behavior of XOR gate consider its truth table given below. If one input of XOR
gate is zero then the output of XOR will be same as the second input. While if one
input of XOR gate is one then the output of XOR will be complement of the
second input.
So when M = 0, the output of XOR gate will be Bi ⊕ 0 = Bi. If the full adders
receive the value of B, and the input carry C0 is 0, the circuit performs A plus B.
When M = 1, the output of XOR gate will be Bi ⊕ 1 = Bi’. If the full adders receive
the value of B’, and the input carry C0 is 1, the circuit performs A plus 1’s
complement of B plus 1, which is equal to A minus B.
4.5 INSTRUCTION SET

44
8 BIT ALU DESIGN
The instructions that can be performed are shown in the table:
Opcode_in( Opcode_in( Opcode_in( Opcode_in(

Function
3) 2) 1) 0)
0 0 0 0 Pass Data_in
0 0 0 1 Pass Accumulator_in
0 0 1 0 ADDITION
0 0 1 1 SUBTRACTION
0 1 0 0 AND
0 1 0 1 OR
0 1 1 0 XOR
0 1 1 1 NOT Accumulator_in
1 0 0 0 NOT Data_in
INCREMENT
1 0 0 1
Accumulator_IN
DECREMENT
1 0 1 0
Accumulator_in
1 0 1 1 MULTIPLICATION
1 1 0 0 NAND
1 1 0 1 NOR
1 1 1 0 XNOR
1 1 1 1 -
4.6 DESIGN IMPLEMENTATION

45
8 BIT ALU DESIGN
Our basic goal was to implement the design on FPGA. We have used Xilinx
Spartan 3 XC3S400 FPGA board mounted on FPGA trainer. Xilinx Spartan-3
FPGAs are ideal for low-cost, high-volume applications and are targeted as
replacements for fixed-logic gate arrays and ASSP products such as bus interface
chip sets. The Spartan-3 (1.2V, 90 nm) FPGA is not only available for a very low
cost, but it integrates many architectural features associated with high-end
programmable logic. This combination of low cost and features makes it an ideal
replacement for ASICs (gate arrays) and many ASSP devices. In order to interface
it with the parallel port of PC we have to setup the parallel port unidirectional
settings (EEP) with IRQ 278 from the bios setup of PC. For that, we first
implemented the design using the Xilinx-ISE simulator. The error free code for this
has been given in coming sections.
This code was then synthesized in XILINX-PROJECT NAVIGATOR.
After synthesizing the code, we generated the bit stream file after assigning the
input and output ports for the FPGA XC3S400 board using XILINX PACE.
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8 BIT ALU DESIGN
47
8 BIT ALU DESIGN
Then, we loaded the ALU.bit file on the FPGA using Xilinx- iMPACT.
Followed by, we provided the inputs using trainer switches (via Toggle
Switches) and displayed the outputs using LEDS on the trainer.
Following picture shows the whole design implemented with inputs and outputs.
The Spartan 3 XC3S400 kit:
48
8 BIT ALU DESIGN
4.7 VHDL CODE ATIRHMETIC LOGIC UNIT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity minor_project is
Port ( Accumulator_in : in STD_LOGIC_VECTOR (7 downto 0);
Data_in : in STD_LOGIC_VECTOR (7 downto 0);
Opcode_in : in STD_LOGIC_VECTOR (3 downto 0);
Multiplier : in STD_LOGIC_VECTOR (3 downto 0);
Multiplicand : in STD_LOGIC_VECTOR (3 downto 0);
Result_out : out STD_LOGIC_VECTOR (7 downto 0));
end minor_project;
architecture Behavioral of minor_project is
begin
Main: process(Accumulator_in,Opcode_in, Data_in)
begin
case Opcode_in is
when "0000" => Result_out <= Data_in;
-- result = Data_in
when "0001"=> Result_out <= Accumulator_in;
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8 BIT ALU DESIGN
-- result = accumulator_in
when "0010"=> Result_out <= Accumulator_in + Data_in;
-- result = accumulator_in + Data_in
when "0011"=> Result_out <= Accumulator_in - Data_in;
-- result = accumulator_in - Data_in
when "0100"=> Result_out <= Accumulator_in and Data_in;
-- result = accumulator_in and Data_in
when "0101"=> Result_out <= Accumulator_in or Data_in;
-- result = accumulator_in or Data_in
when "0110"=> Result_out <= Accumulator_in xor Data_in;
-- result = accumulator_in xor Data_in
when "0111"=> Result_out <= not(accumulator_in);
-- result = not(accumulator_in)
when "1000"=> Result_out <= not(Data_in);
-- result = not(Data_in);
when "1001"=> Result_out <= Accumulator_in + 1;
-- result Increment Accumulator_in

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8 BIT ALU DESIGN
when "1010"=> Result_out <= Accumulator_in - 1;
-- result Decrement Accumulator_in
when "1011"=> Result_out <= Multiplier * Multiplicand;
-- result = 8 MSBs of ( Multiplier * Multiplicand)
when "1100"=> Result_out <= accumulator_in nand Data_in;
-- result = accumulator_in nand Data_in
when "1101"=> Result_out <= accumulator_in xnor Data_in;
--result=accumulator_in xnor Data_in
when "1110"=> Result_out <= accumulator_in nor Data_in;
-- result = accumulator_in nor Data_in
when "1111"=> Result_out <= "00000000";
--result=Accumulator_in
when others => Result_out <="XXXXXXXX";
end case;
end process Main;
end Behavioral;
CHAPTER 5
51
8 BIT ALU DESIGN
SYNTHESIS
5.1 SYNTHESIS REPORT
ARITHMETIC LOGIC UNIT
Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
--> Reading design: minor_project.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
52
8 BIT ALU DESIGN
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "minor_project.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "minor_project"
Output Format : NGC
Target Device : xc3s400-5-pq208
---- Source Options
Top Module Name : minor_project
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
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8 BIT ALU DESIGN
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) :8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto

54
8 BIT ALU DESIGN
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : minor_project.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5
===========================================================
* HDL Compilation *
===========================================================
Compiling vhdl file "C:/Xilinx92i/shivnath/minor_project.vhd" in Library work.

55
8 BIT ALU DESIGN
Architecture behavioral of Entity minor_project is up to date.
===========================================================
* HDL Analysis *
===========================================================
Analyzing Entity <minor_project> in library <work> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/Xilinx92i/shivnath/minor_project.vhd" line 91: Mux is

complete : default of case is discarded
WARNING:Xst:819 - "C:/Xilinx92i/shivnath/minor_project.vhd" line 42: The

following signals are missing in the process sensitivity list:
Multiplier, Multiplicand.
Entity <minor_project> analyzed. Unit <minor_project> generated.
===========================================================
* HDL Synthesis *
===========================================================
Performing bidirectional port resolution...
Synthesizing Unit <minor_project>.
Related source file is "C:/Xilinx92i/shivnath/minor_project.vhd".
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
Found 8-bit 16-to-1 multiplexer for signal <Result_out>.
Found 8-bit addsub for signal <Result_out$addsub0000>.
Found 4x4-bit multiplier for signal <Result_out$mult0000> created at line 78.
Found 8-bit xor2 for signal <Result_out$xor0000> created at line 63.
Summary:
56
8 BIT ALU DESIGN
inferred 1 Adder/Subtractor(s).
inferred 1 Multiplier(s).
inferred 8 Multiplexer(s).
Unit <minor_project> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some

arithmetic operations in this design can share the same physical resources for
reduced device utilization. For improved clock frequency you may try to disable
resource sharing.
HDL Synthesis Report
8-bit xor2 :1
Macro Statistics
8-bit addsub :1
8-bit 16-to-1 multiplexer :1
4x4-bit multiplier :1
# Xors :1
# Multipliers :1
# Multiplexers :1
# Adders/Subtractors :1
===========================================================
* Advanced HDL Synthesis *
===========================================================
57
8 BIT ALU DESIGN
Loading device for application Rf_Device from file '3s400.nph' in environment

C:\Xilinx92i.
===========================================================
Advanced HDL Synthesis Report
Macro Statistics
# Multipliers :1
4x4-bit multiplier :1
# Adders/Subtractors :1
8-bit addsub :1
# Multiplexers :1
8-bit 16-to-1 multiplexer :1
# Xors :1
8-bit xor2 :1
===========================================================
* Low Level Synthesis *
===========================================================
Optimizing unit <minor_project> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block minor_project, actual ratio is 2.
Final Macro Processing ...
===========================================================
* Final Report *
58
8 BIT ALU DESIGN
===========================================================
Final Results
RTL Top Level Output File Name : minor_project.ngr
Top Level Output File Name : minor_project
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 36
Cell Usage :
# BELS : 153
# GND :1
# LUT1 :8
# LUT3 : 64
# LUT4 :9
# MUXCY :7
# MUXF5 : 32
# MUXF6 : 16
# MUXF7 :8
# XORCY :8
# IO Buffers : 36
# IBUF : 28
# OBUF :8
59
8 BIT ALU DESIGN
# MULTs :1
# MULT18X18 :1
===========================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-5
Number of Slices: 41 out of 3584 1%
Number of 4 input LUTs: 81 out of 7168 1%
Number of IOs: 36
Number of bonded IOBs: 36 out of 141 25%
Number of MULT18X18s: 1 out of 16 6%
===========================================================
TIMING REPORT
--------------------------------------------------------------------------------
Release 9.2i Trace
C:\Xilinx92i\bin\nt\trce.exe -ise C:/Xilinx92i/shivnath/shivnath.ise -intstyle
ise -e 3 -s 5 -xml minor_project_preroute minor_project_map.ncd -o
minor_project_preroute.twr minor_project.pcf -ucf minor_project.ucf
Design file: minor_project_map.ncd
Physical constraint file: minor_project.pcf
Device,speed: xc3s400,-5 (PRODUCTION 1.39 2007-04-13)

60
8 BIT ALU DESIGN
Report level: error report
Environment Variable Effect
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Pad to Pad
-----------------+---------------+---------+-------------
Source Pad |Destination Pad| Delay |
-----------------+---------------+---------+------------
Accumulator_in<0>|Result_out<0> | 7.985|
61
8 BIT ALU DESIGN
62
8 BIT ALU DESIGN
Data_in<0> |Result_out<0> | 8.564|

63
8 BIT ALU DESIGN

64
8 BIT ALU DESIGN
Multiplicand<0> |Result_out<0> | 8.693|

65
8 BIT ALU DESIGN
Multiplier<0> |Result_out<0> | 8.693|

66
8 BIT ALU DESIGN
Opcode_in<0> |Result_out<0> | 8.945|

67
8 BIT ALU DESIGN
-----------------+---------------+---------+
Analysis completed Fri Dec 10 15:44:04 2010
Peak Memory Usage: 108 MB
5.2 BITGEN REPORT
68
8 BIT ALU DESIGN
Release 9.2i - Bitgen J.36

Loading device for application Rf_Device from file '3s400.nph' in environment
C:\Xilinx92i.
"minor_project" is an NCD, version 3.1, device xc3s400, package pq208, speed
-5
Opened constraints file minor_project.pcf.
Fri Dec 10 15:57:31 2010
Summary of Bitgen Options:

+----------------------+----------------------+
| Option Name | Current Setting |

+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 6** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DCMShutdown | Disable** |
69
8 BIT ALU DESIGN
+----------------------+----------------------+
| DCIUpdateMode | AsRequired** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| HswapenPin | Pullup* |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+

+----------------------+----------------------+
+----------------------+----------------------+
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
70
8 BIT ALU DESIGN
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| Match_cycle | Auto** |
+----------------------+----------------------+
+----------------------+----------------------+

+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
71
8 BIT ALU DESIGN
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
+----------------------+----------------------+
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
+----------------------+----------------------+

+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "minor_project.bit".Bitstream generation is complete.
72
8 BIT ALU DESIGN
5.3 RTL SCHEMATIC: ARITHMETIC LOGIC UNIT
73
8 BIT ALU DESIGN
74
8 BIT ALU DESIGN
5.3.1 DETAILED RTL SCHEMATIC: ARITHMETIC

LOGIC UNIT
75
8 BIT ALU DESIGN
76
8 BIT ALU DESIGN
77
8 BIT ALU DESIGN
5.3.2 TECHNOLOGY SCHEMATIC
5.4 SIMULATION WAVEFORMS

Inputs: Accumulator_in : 11001011
78
8 BIT ALU DESIGN
Data_in : 00101010
Operation: ADDITION
Output: Result_out = 11110101
Inputs: Accumulator_in : 11001011
Data_in : 00101010
79
8 BIT ALU DESIGN
Operation: AND
Output: Result_out = 00001010
5.5 FLOOR PLAN
80
8 BIT ALU DESIGN
81
8 BIT ALU DESIGN
CHAPTER 6
EPILOGUE
CONCLUSION
The VHDL is a versatile language, which has great flexibility of designing

components. It can be said that VHDL fuelled modern synthesis technology and
enabled the development of ASIC semiconductor companies. From the beginning
VHDL has been a powerful language with numerous language constructs that are
capable of describing very complex behavior, this leadership of VHDL community
has assured open and internationally accredited for the electronic design
Engineering community. The legacy of team work continues to benefit the design
community today as the benchmark by which one measures openness.
With the help of which we are able to successfully implement the Arithmetic Logic
Unit of a Microprocessor.
82
8 BIT ALU DESIGN
BIBLIOGRAPHY
 J.Bhaskar, A VHDL Primer, Pearson Education Asia, Third Edition 2006
 Volnei A. Pedroni, Circuit Design with VHDL, Prentice Hall India 2005
 Morris M Mano, Digital Design, Pearson Edition, 2000
 XILINX INC, XILINX Foundation Series User Reference Guide
 XILINX INC, XILINX Software Sampler Quick Start Guide
 Charles H Roth, Principles Of Digital System Design using VHDL,Clengage

Learning 2010
 Enoch O. Hwang, Digital Logic and Microprocessor Design with VHDL,

Thomson 2007
 www.xilinx.com
 www.ieee.org
83

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DESIGN AND SIMULATION OF 8 BIT

ARITHMETIC LOGIC UNIT USING VHDL

A MINOR PROJECT REPORT

In partial fulfillment for the award of the degree

ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

G B PANT ENGINEERING COLLEGE

We hereby declare that the project entitled

PLACE: New Delhi

• Shivnath Kumar (0292092807)

• Bhuvnesh Kumar (0282092807)

Students of B.Tech ‘G.B. PANT ENGINEERING COLLEGE’,DELHI

SIGNATURE OF THE MENTOR:

Mr. Arun Prakash

Date: 10th December Mr. Mohammad Ihtesham

Place: New Delhi Mr. Shivnath Kumar

VHDL is a hardware description language for delineating digital electronic

 VHDL Application Field………………………………………7

 ASIC Development ……………………………………………8

 Concept of VHDL ……………………………………………9

 Abstraction Levels in VHDL………………………………….10

 Description of Abstraction Levels ……………………………11

 Modularity and Hierarchy……………………………………..12

 VHDL Language and Syntax………………………………….13

 VHDL Structural Elements……………………………………14

 Process Communication Model……………………………….22

CHAPTER 2 : INTRODUCTION TO SYNTHESIS

 What is Logic Synthesis?.............................................................23

 Impact Of HDL & Logic Synthesis…………………………….24

 Design Entry & Synthesis………………………………………24

CHAPTER 3 : PROGRAMMABLE LOGIC DESIGN

 History of Programmable Logic Design…………………………28

 Complex Programmable Logic Device (CPLD)…………………31

 Field Programmable Logic Gate Array (FPGA)…………………32

 Basic Design Process……………………………………………..33

CHAPTER 4 : DESIGN OFARITHMETIC LOGIC UNIT

 Introduction to Arithmetic Logic Unit……………………………35

VHDL is an acronym which stands for VHSIC Hardware Description Language.

Hardware description languages can be used in several ways; they can be an

A language capable of such diverse applications has a lot of keywords and a

1.2 VHDL HISTORY

1.2.3 ASIC MANDATE

1.2.4 VHDL 1993

1.2.5 VHDL 2000 AND VHDL 2002

VHDL-2002 is a minor revision of VHDL 2000 Edition. There is one significant

1.3 VHDL APPLICATION FIELD

An ongoing field of research is the hardware/software co design. The most

1.4 ASIC DEVELOPMENT

As soon as a model built of ASIC library elements is available, a simulation on

1.5 CONCEPTS OF VHDL

Sequential statements are executed one after another, like in software

Concurrent statements are active continuously. So the order of the statements is

VHDL features also three important modeling techniques:

1.6 ABSTRACTION LEVELS AND VHDL

VHDL is applicable to the upper three abstraction levels. It is not suitable to

Behavioral synthesis is still a dream of many researchers as only very simple

1.7 DESCRIPTION OF ABSTRACTION LEVELS

1.8 MODULARITY AND HIERARCHY

Modularity and hierarchy help to simplify and organize a design project.

1.9 VHDL LANGUAGE AND SYNTAX

-- Example VHDL Code — Case insensitive

signal mySignal: bit; -- an example Comments: ‘—‘ until end of line

‘0’ after 10 ns, -- User defined names: