4. The ________ ensures that only one IC is active at a time to avoid a bus conflict caused
by two ICs writing different data to the same bus.
A. control bus
B. control instructions
C. address decoder
D. CPU
5. In an 8085 microprocessor, the instruction CMP B has been executed while the contents
of accumulator is less than that of register B. As a result carry flag and zero flag will be
respectively
(A) set, reset (B) reset, set (C) reset, reset (D) set, set
7. Registers, which are partially visible to users and used to hold conditional, are known as
a. PC
b. Memory address registers
c. General purpose register
d. Flags
11. The number of memory cycles required to execute the following 8085 instructions
(i) LDA 3000H
(ii) LXI D, FOF1H would be
(B) 2 for (i) and 2 for (ii)
(C) 4 for (i) and 2 for (ii)
(D) 3 for (i) and 3 for (ii)
(E) 3 for (i) and 4 for (ii)
12. The 8255 Programmable Peripheral Interface isused as described below.
(i) An A/D converter is interfaced to a microprocessor
through an 8255. The conversion is initiated by a signal
from the 8255 on Port C. A signal on Port C causes data
to be stobed into Port A.
(ii) Two computers exchange data using a pair of 8255s.
Port A works as a bidirectional data port supported by
appropriate handshaking signals. The appropriate
modes of operation of the 8255 for (i) and (ii) would be
(A) Mode 0 for (i) and Mode 1 for (ii)
(B) Mode 1 for (i) and Mode 2 for (ii)
(C) Mode 2 for (i) and Mode 0 for (ii)
(D) Mode 2 for (i) and Mode 1 for (ii)
13. The microprocessor 8085 has _____ basic instructions and _____ opcodes.
a) 80, 246 b) 70, 346 c) 80, 346 d) 70, 246
22. The contents of accumulator before CMA instruction is A5H. Its content after instruction
execution is
a) A5H b) 5AH c) AAH d) 55H
23. In an 8085 based system, the maximum number of input output devices can be connected
using I/0 mapped I/O method is
a) 64 b) 512 c) 256 d) 65536
25. What generation chip is the Pentium 4 for the Intel central processing units?
A. Seventh generation
B. Eighth generation
26. The first processor to include Virtual memory in the Intel microprocessor family
was:
a.) 80286
b.) 80386
c.) 80486
d.) Pentium
27. Intel Itanium processors are designed for
a. Servers and personal computers
b. Servers only
c. Personal computers only
d. Calculators
28. In 8086 microprocessor one of the following instructions is executed before an arithmetic
operation
a. AAM b) AAD c) DAS d) DAA
32. When the 8051 is reset and the line is LOW, the program counter points to the first
program instruction in the:
33. In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____.
a) 000BH, a high to low transition on pin INT1
b) 001BH, a low to high transition on pin INT1
c) 0013H, a high to low transition on pin INT1
d) 0023H, a low to high transition on pin INT1
34. In a microprocessor, the service routine for a certain interrupt starts from a fixed location of
memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an
interrupt is
(A) non-maskable and non-vectored
36. An 8255 chip is Interfaced to an 8085 Microprocessor system as an I/O Mapped I/O.
The Address lines A0, A1 of 8085 are used by the 8255 chip to decode internally its
three ports and the control register.The address lines A3-A7 and IO/M signal are
used for address decoding. The range of the addresses for which the 8255 chip
would get selected is
37. The TRAP is one of the interrupts available its INTEL 8085. Which one of the following
statements is true of TRAP?
(a) It is level triggered
(b) It is negative edge triggered
(c) It is positive edge triggered
(d) It is both positive edge triggered and level triggered
38. In a 16-bit microprocessor, words are stored in two consecutive memory locations. The
entire word can be read in one operation provided the first
39. The ESC instruction of 8086 may have two formats. In one of the formats, no memory
operand is used. Under this format, the number of external op-codes (for the co-
processor) which can be specified is?
a. 64
b. 128
c. 256
d. 512
40. DB, DW and DD directives are used to place data in particular location or to simply
allocate space without preassigning anything to space. The DW and DD directories are
used to generate