Msp430 Training Manual

M SP430x 1xx Fami ly
Users G u ide
2 00 5
M i e d S i n al Po d u c ts x g r
SLAU049E
I n dex
Section Title Page
1 MSP430 Architecture 1 1.1 Address Space.. 3 1.2 Operating Modes. 5 1.3 Status Register (SR).... 8 1.4 Addressing Modes... 9 1.5 Instruction Set...... 17 2 Basic clock Module. 18 2.1 Adjusting the DCO.. 21 2.2 Registers... ...... 23 3 Flash Memory... 25 4 Hardware Multiplier.. 30 5 DMA Controller 32 6 Digital I/O Register... 39 7 Watchdog Timer... 40 8 Timer A... 42 9 Timer B.. 49 10 USART (UART Mode)... ............... 56 11 USART (SPI Mode).. 64 12 Comparator A. 70 13 ADC12... 76 14 DAC12... 87 15 Special Function Registers 15.1 Interrupt Vector Address... 93 15.2 IE1, IE2, IFG1, IFG2 Registers.... 94 15.3 ME1, ME2 Registers.. 95 16 Reference Data sheets 16.1 Timer A Input Pin Details. 96 16.2 DS 1307 Datasheet 97 16.3 MSP430F14x Pin Diagram... 101
M S P 430 Archit ecture

1.1 Architecture
The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and m em ory data bus (MDB). Partnering a m odern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x1xx family include:
- Ultralow-power architecture extends battery life J 0.1-A RAM retention J
0.8-A real-time clock mode J
250-A / MIPS active

- High-performance analog ideal for precision measurement J
12-bit or 10-bit ADC 200 ksps, temperature sensor, VRef J Comparator-gated timers for measuring resistive elements J
12-bit dual-DAC
J
Supply voltage supervisor

-
16-bit RISC CPU enables new applications at a fraction of the code size.
J Large register file eliminates working file bottleneck J Compact core design reduces power consumption and cost J
Optimized for modern high-level programming

J Only 27 core instructions and seven addressing modes J
Extensive vectored-interrupt capability

- In-system programmable Flash permits flexible code changes, field
upgrades and data logging
1.2 Flexible Clock System

The clock system is designed specifically for battery-powered applications. A low-frequency auxiliary clock (ACLK) is driven directly from a common 32-kHz watch crystal. The ACLK can be used for a background real-time clock self wake- up f un ction. An i ntegrat ed hi gh-s peed digita lly c ontrolled o scillat or (DCO) can source the master clock (MCLK) used by the CPU and high-speed peri phera ls. By desi gn, the DCO is a cti ve and stable in le ss than 6 s. MSP430-based solutions effectively use the high-performance 16-bit RISC CPU in very short bursts.
-
Low-frequency auxiliary clock = Ultralow-power stand-by mode
- High-speed master clock = High performance signal processing
Introduction
Embedded Emulation
Figure 11. MSP430 Architecture
Clock System
MCLK
ACLK SMCLK
Flash/ ROM
RAM
Peripheral
Peripheral
Peripheral
MAB 16-Bit
RISC CPU 16-Bit

MDB 16-Bit
Bus Conv.
MDB 8-Bit
JTAG
ACLK SMCLK
Watchdog
Peripheral
Peripheral
Peripheral
Peripheral
1.3 Embedded Emulation

D edicated em bed ded emulation l ogic r esi des on the de vice itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include:
- U nobtrusi ve d evel opm en t and debug with fu ll- spe ed execu ti on ,
breakpoints, and single-steps in an application are supported.
- Development is in-system subject to the same characteristics as the final
application.
- Mixed-signal integrity is preserved and not subject to cabling interference.
Introduction
Address Space
1.4 Address Space

The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as s hown in Fi gure 12. See t he de vice-s pecif ic data s heets for s pe cific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words. The addressable memory space is 64 KB with future expansion planned.
Figure 12. Memory Map

Access 0FFFFh 0FFE0h 0FFDFh Interrupt Vector Table Word/Byte
Flash/ROM
Word/Byte
0200h 01FFh
RAM
Word/Byte
16-Bit Peripheral Modules 0100h 0FFh 010h 0Fh 0h 8-Bit Peripheral Modules Special Function Registers
Word Byte Byte
1.4.1
Flash/ROM
The start addr ess of Flash /ROM depends on t he a mount of Flash /ROM present and varies by device. The end address for Flash/ROM is 0FFFFh. Flash can be used for both code and data. W ord or byte tables can be stored and used in Flash/ROM without the need to copy the tables to RAM before using them. The interrupt vector table is mapped into the upper 16 words of Flash/ROM address space, with the highest priority interrupt vector at the highest Flash/ROM word address (0FFFEh).
1.4.2
RAM
RAM starts at 0200h. The end address of RAM depends on the amount of RAM present and varies by device. RAM can be used for both code and data.
Introduction
O p eratin g M ode s
2.3 Operating Modes
The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 210. The operating modes take into account three different needs: Ultralow-power
- S peed and data through put - Minimization of individual peripheral current consumption
The MSP430 typical current consumption is shown in Figure 29.
Figure 29. Typical Current Consumption of 13x and 14x Devices vs Operating Modes
340 225 VCC = 3 V VCC = 2.2 V 70 65 17 11 AM LPM0 2 1 0.10. 1 LPM4
315 270 225 180 135 90 45 0
LPM2 LPM3 Operating Modes
The low-power modes 04 are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the status register The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine. Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine. Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine. The mode-control bits and the stack can be accessed with any instruction. When setting any of the mode-control bits, the selected operating mode takes effect immediately. Peripherals operating with any disabled clock are disabled until the clock becomes active. The peripherals may also be disabled with their individual control register settings. All I/O port pins and RAM/registers are unchanged. W ake up is possible through all enabled interrupts.
System Resets, Interrupts, and Operating Modes
Operating Modes
Figure 210. MSP430x1xx Operating Modes For Basic Clock System
RST/NMI Reset Active
VCC On
WDT Time Expired, Overflow
POR WDTIFG = 1 WDTIFG = 1 WDTIFG = 0 PUC RST/NMI is Reset Pin WDT is Active RST/NMI NMI Active
WDT Active, Security Key Violation
CPUOFF = 1 SCG0 = 0 SCG1 = 0 LPM0 CPU Off, MCLK Off, SMCLK On, ACLK On CPUOFF = 1 SCG0 = 1 SCG1 = 0 LPM1 CPU Off, MCLK Off, SMCLK On, ACLK On DC Generator Off if DCO not used in active mode
Active Mode CPU Is Active Peripheral Modules Are Active
CPUOFF = 1 OSCOFF = 1 SCG0 = 1 SCG1 = 1 LPM4 CPU Off, MCLK Off, DCO Off, ACLK Off DC Generator Off
CPUOFF = 1 SCG0 = 0 SCG1 = 1
CPUOFF = 1 SCG0 = 1 SCG1 = 1
LPM2 CPU Off, MCLK Off, SMCLK Off, DCO Off, ACLK On
LPM3 CPU Off, MCLK Off, SMCLK Off, DCO Off, ACLK On DC Generator Off
SCG1 0 0 0
SCG0 OSCOFF CPUOFF 0 0 1 0 0 0 0 1 1
Mode Active LPM0 LPM1
CPU and Clocks Status CPU is active, all enabled clocks are active CPU, MCLK are disabled SMCLK , ACLK are active CPU, MCLK, DCO osc. are disabled DC generator is disabled if the DCO is not used for MCLK or SMCLK in active mode SMCLK , ACLK are active CPU, MCLK, SMCLK, DCO osc. are disabled DC generator remains enabled ACLK is active CPU, MCLK, SMCLK, DCO osc. are disabled DC generator disabled ACLK is active CPU and all clocks disabled
LPM2
LPM3
LPM4
System Resets, Interrupts, and Operating Modes
CPU Introduction
3.1 CPU Introduction

The CPU incorporates features specifically designed for m odern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include:
- RISC architecture with 27 instructions and 7 addressing modes. - Ort hogonal arch it ect ure with every inst ruc tion u sable wit h every
addressing mode.
- Full register access including program counter, status registers, and stack
pointer.
- Si ngle- cycle reg ister o peratio ns. - Large 16-bit register file reduces fetches to memor y. - 16-bit address bus allows direct access and branching throughout entire
memory range.
- 16-bit data bus allows direct manipulation of word-wide arguments. - Constant generator provides six m ost used immediate values and
reduces code size.
- Direct memory-to-memory transfers without intermediate register holding. -
Word and byte addressing and instruction formats. The block diagram of the CPU is shown in Figure 31.
RISC 16-Bit CPU
CPU Introduction
Figure 31. CPU Block Diagram

MDB Memory Data Bus 15 R0/PC Program Counter R1/SP Stack Pointer R2/SR/CG1 Status R3/CG2 Constant Generator R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 16 Gen er a P urpose l Gen er a P urpose l Gen er a P urpose l Gen er a P urpose l Gen er a P urpose l Gen er a P urpose l General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose 16 Zero, Z Carry, C Overflow, V Negative, N dst 16bit ALU src MCLK Memory Address Bus MAB 0 0 0
RISC 16-Bit CPU
CPU Registers
3.2.3
Status Register (SR)

The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 36 shows the SR bits.
Figure 36. Status Register Bits

15 Reserved 9 8 V 7 SCG1 rw-0 SCG0 OSC CPU OFF OFF GIE N 0 Z C
Table 31 describes the status register bits.
Table 31.Description of Status Register Bits

Bit V Description Overflow bit. This bit is set when the result of an arithmetic operation overflows the signed-variable range. ADD(.B),ADDC(.B) Set when: Positive + Positive = Negative Negative + Negative = Positive, otherwise reset Set when: Positive Negative = Negative Negative Positive = Positive, otherwise reset
SUB(.B),SUBC(.B),CMP(.B)
SCG1 SCG0 OSCOFF CPUOFF GIE N
System clock generator 1. This bit, when set, turns off the SMCLK. System clock generator 0. This bit, when set, turns off the DCO dc generator, if DCOCLK is not used for MCLK or SMCLK. Oscillator Off. This bit, when set, turns off the LFXT1 crystal oscillator, when LFXT1CLK is not use for MCLK or SMCLK CPU off. This bit, when set, turns off the CPU. General interrupt enable. This bit, when set, enables maskable interrupts. When reset, all maskable interrupts are disabled. Negative bit. This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative. Word operation: N is set to the value of bit 15 of the result Byte operation: N is set to the value of bit 7 of the result Zero bit. This bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0. Carry bit. This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred.
Z C
RISC 16-Bit CPU
A d dressin g Mod e s
3.3 Addressing Modes
Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in Table 33 describe the contents of the As (source) and Ad (destination) mode bits.
Table 33.Source/Destination Operand Addressing Modes

As/Ad 00/0 01/1 01/1 Addressing Mode Register mode Indexed mode Symbolic mode Syntax Rn X(Rn) ADDR Description Register contents are operand (Rn + X) points to the operand. X is stored in the next word. (PC + X) points to the operand. X is stored in the next word. Indexed mode X(PC) is used. The word following the instruction contains the absolute address. X is stored in the next word. Indexed mode X(SR) is used. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B instructions and by 2 for .W instructions. The word following the instruction contains the immediate constant N. Indirect autoincrement mode @PC+ is used.
01/1
Absolute mode
&ADDR
10/ 11/
Indirect register mode Indirect autoincrement
@Rn @Rn+
11/
Immediate mode
#N
The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction. Note: Use of Labels EDE, TONI, TOM, and LEO Throughout MSP430 documentation EDE, TONI, TOM, and LEO are used as generic labels. They are only labels. They have no special meaning.
RISC 16-Bit CPU
Addressing Modes
3.3.1
Register Mode
The register mode is described in Table 34.
Table 34.Register Mode Description

Assembler Code MOV R10,R11 Content of ROM MOV R10,R11
Length: Operation: Comment: Example:

Before: R10 0A023h
One or two words Move the content of R10 to R11. R10 is not affected. Valid for source and destination MOV R10,R11
After: R10 0A023h
R11
0FA15h
R11
0A023h
PC
PCold
PC
PCold + 2
Note: Data in Registers The data in the register can be accessed using word or byte instructions. If byte instructions are used, the high byte is always 0 in the result. The status bits are handled according to the result of the byte instruction.
10
RISC 16-Bit CPU
Addressing Modes
3.3.2
Indexed Mode
The indexed mode is described in Table 35.
Table 35.Indexed Mode Description

Assembler Code MOV 2(R5),6(R6) Content of ROM MOV X(R5),Y(R6) X=2 Y=6
Length: Operation:
Two or three words Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected. In index ed m ode, the p ro gram co unter is increme nted automatically so that program execution continues with the next instruction. Valid for source and destination MOV 2(R5),6(R6);
Register After: Address Space 0xxxxh 00006h 00002h 04596h Register PC R5 01080h R6 0108Ch
Comment: Example:
Before: Address Space 00006h 00002h
0FF16h 0FF14h 0FF12h
R5 R6
01080h 0108Ch
04596h PC 0108Ch +0006h 01092h
01094h 01092h 01090h
0xxxxh 05555h 0xxxxh
01094h 01092h 01090h
01084h 01082h 01080h
01080h +0002h 01082h
01084h 01082h 01080h
RISC 16-Bit CPU
11
Addressing Modes
3.3.3
Symbolic Mode
The symbolic mode is described in Table 36.
Table 36.Symbolic Mode Description

Assembler Code MOV EDE,TONI Content of ROM MOV X(PC),Y(PC) X = EDE PC Y = TONI PC
Length: Operation:
Two or three words Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y). The words after the instruction contain the differences between the PC and the source or destination addresses. The assembler computes and inserts offsets X and Y automatically. W ith symbolic mode, the program counter (PC) is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV
Address Space 011FEh 0F102h 04090h PC 0FF14h +0F102h 0F016h
Comment: Example:
Before:
EDE,TONI ;Source address EDE = 0F016h ;Dest. address TONI=01114h

Register After: Address Space 0xxxxh 011FEh 0F102h 04090h Register PC
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
0F018h 0F016h 0F014h
01116h 01114h 01112h
0FF16h +011FEh 01114h
01116h 01114h 01112h
12
RISC 16-Bit CPU
Addressing Modes
3.3.4
Absolute Mode
The absolute mode is described in Table 37.
Table 37.Absolute Mode Description

Assembler Code MOV &EDE,&TONI Content of ROM MOV X(0),Y(0) X = EDE Y = TONI
Length: Operation:
Two or three words Move the contents of the source address EDE to the destination address TONI. The words after the instruction contain the absolute address of the source and destination addresses. W ith absolute mode, the PC is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV
Address Space 01114h 0F016h 04292h PC
Comment: Example:
Before:
&EDE,&TONI ;Source address EDE=0F016h, ;dest. address TONI=01114h

Register After: Address Space 0xxxxh 01114h 0F016h 04292h Register PC
0F018h 0F016h 0F014h
0F018h 0F016h 0F014h
01116h 01114h 01112h
01116h 01114h 01112h
This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address. These are addressed with absolute mode to ensure software transportability (for example, position-independent code).
RISC 16-Bit CPU
13
Addressing Modes
3.3.5
Indirect Register Mode

The indirect register mode is described in Table 38.
Table 38.Indirect Mode Description

Assembler Code MOV @R10,0(R11) Content of ROM MOV @R10,0(R11)
Length: Operation:
One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified. Valid only for source operand. The substitute for destination operand is 0(Rd). MOV.B @R10,0(R11)
Register After: Address Space 0xxxxh 0FF16h 0000h 0FF14h 0FF12h 04AEBh 0xxxxh Register PC R10 0FA33h R11 002A7h
Comment: Example:
Before: Address Space 0xxxxh 0000h 04AEBh 0xxxxh
R10 PC R11
0FA33h 002A7h
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
002A8h 002A7h 002A6h
0xxh 012h 0xxh
002A8h 002A7h 002A6h
0xxh 05Bh 0xxh
14
RISC 16-Bit CPU
Addressing Modes
3.3.6
Indirect Autoincrement Mode

The indirect autoincrement mode is described in Table 39.
Table 39.Indirect Autoincrement Mode Description

Assembler Code MOV @R10+,0(R11) Content of ROM MOV @R10+,0(R11)
Length: Operation:
One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is i ncrem ent ed by 1 f or a byte opera tion, or 2 f or a w ord operation after the fetch; it points to the next address without any overhead. This is useful for table processing. Valid only for source operand. The substitute for destination operand is 0(Rd) plus second instruction INCD Rd. MOV @R10+,0(R11)
Register After: Address Space 0xxxxh 00000h 04ABBh 0xxxxh PC R10 0FA34h R11 010A8h Register
Comment: Example:
Before: Address Space
0FF18h 0FF16h 0FF14h 0FF12h
0xxxxh 00000h 04ABBh 0xxxxh
R10 PC R11
0FA32h 010A8h
0FF18h 0FF16h 0FF14h 0FF12h
010AAh 010A8h 010A6h
010AAh 010A8h 010A6h
The autoincrem enting of the register contents occurs after the operand is fetched. This is shown in Figure 38.
Figure 38. Operand Fetch Operation

Instruction Address Operand +1/ +2
RISC 16-Bit CPU
15
Addressing Modes
3.3.7
Immediate Mode
The immediate mode is described in Table 310.
Table 310.Immediate Mode Description

Assembler Code MOV #45h,TONI Content of ROM MOV @PC+,X(PC) 45 X = TONI PC
Length: Operation:
Two or three words It is one word less if a constant of CG1 or CG2 can be used. Move the immediate constant 45h, which is contained in the word following the instruction, to destination address TONI. When fetching the source, the program counter points to the word following the instruction and moves the contents to the destination. Valid only for a source operand. MOV
Address Space 01192h 00045h 040B0h PC 0FF16h +01192h 010A8h
Comment: Example:
Before:
#45h,TONI
Register After: 0FF18h 0FF16h 0FF14h 0FF12h Address Space 0xxxxh 01192h 00045h 040B0h Register PC
010AAh 010A8h 010A6h
010AAh 010A8h 010A6h
16
RISC 16-Bit CPU
Instr uction S et
Table 317.MSP430 Instruction Set
Mnemonic ADC(.B) ADDC(.B) AND(.B) BIC(.B) BIS(.B) BR BIT(.B) ADD(.B) dst src,dst src,dst src,dst src,dst src,dst dst dst dst src,dst Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear C Clear N Clear Z dst dst dst src,dst src,dst Compare source and destination Add C decimally to destination Add source and C decimally to dst. Decrement destination Double-decrement destination Disable interrupts Enable interrupts dst dst dst label label label label label label label src,dst dst src label Increment destination Double-increment destination Invert destination Jump if C set/Jump if higher or same Jump if equal/Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set/Jump if lower Jump if not equal/Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt dst dst dst dst dst Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not(C) from destination Set C Set N Set Z src,dst dst dst dst src,dst src,dst Subtract source from destination Subtract source and not(C) from dst. Swap bytes Extend sign Test destination Exclusive OR source and destination dst + 0FFFFh + 1 src .xor. dst dst dst + 0FFFFh + C dst 1C 1N 1C dst + .not.src + 1 dst dst + .not.src + C dst @SP dst, SP+2 SP SP 2 SP, src @SP @SP PC, SP + 2 SP src dst PC + 2 x offset PC dst + C dst src + dst dst src + dst + C dst src .and. dst dst .not.src .and. dst dst src .or. dst dst src .and. dst dst PC PC+2 stack, dst PC 0 dst 0C 0N 0Z dst src dst + C dst (decimally) src + dst + C dst (decimally) dst 1 dst dst 2 dst 0 GIE 1 GIE dst +1 dst dst+2 dst .not.dst dst V * * * 0 0 * * * * * * * * * * * 0 * * * * 0 0 * N * * * * * 0 * * * * * * * * * * * * * * 1 * * * * * Z * * * * * 0 * * * * * * * * * * * * * * 1 * * * * * C * * * * * 0 * * * * * * * * * * * * * * 1 * * * 1 *
CALL
CLR(.B) CLRC CLRN CMP(.B) CLRZ
DADC(.B) DADD(.B) DEC(.B) DINT EINT
DECD(.B)
INCD(.B) INV(.B) JC/JHS JEQ/JZ
INC(.B)
JGE JMP JN JL
JNC/JLO JNE/JNZ MOV(.B) POP(.B)
NOP
RETI
RET
PUSH(.B)
RLA(.B) RLC(.B) RRA(.B) RRC(.B) SETC SETZ
SBC(.B) SET
SWPB SXT
SUBC(.B)
SUB(.B)
TST(.B) XOR(.B)
Emulated Instruction
RISC 16Bit CPU
17
B asic Cloc k M odule Introd uction

4.1 Basic Clock Module Introduction
The basic clock module supports low system cost and ultralow-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The basic clock module can be configured to operate without any external com ponents, with one external resistor, with one or two external crystals, or with resonators, under full software control. The basic clock module includes two or three clock sources:
- LFXT 1CL K: Low-freque ncy/high-frequency o scillator th at can b e u sed
either with low-frequency 32768-Hz watch crystals, or standard crystals or resonators in the 450-kHz to 8-MHz range.
- X T2CL K: Op tiona l high-frequen cy o scillator that c an be use d with
standard crystals, resonators, or external clock sources in the 450-kHz to 8-MHz range. characteristics.
- DCOCLK: Internal digitally controlled oscillator (DCO) with RC-type
Three clock signals are available from the basic clock module:
- ACLK: Auxiliary clock. The ACLK is the buffered LFXT1CLK clock source
d ivi ded by 1 , 2 , 4, or 8. ACL K is so ftw are selectable for i ndiv idual peripheral modules.
- MCL K: Ma ster clo ck. MCL K is software selectable a s LFXT1CL K,
XT2CLK (if available), or DCOCLK. MCLK is divided by 1, 2, 4, or 8. MCLK is used by the CPU and system.
- SMCLK: Sub-main clock. SMCLK is software selectable as LFXT1CLK,
XT2CLK (if available on-chip), or DCOCLK. SMCLK is divided by 1, 2, 4, or 8. SMCLK is software selectable for individual peripheral modules.
The block diagram of the basic clock module is shown in Figure 41.
18
Basic Clock Module
Basic Clock Module Introduction
Figure 41. Basic Clock Block Diagram

DIVAx
LFXT1CLK OSCOFF XTS
Divider /1/2/4/8
ACLK Auxillary Clock
XIN
0V
12pF LF 12pF LFOff XT XT1Off SELMx DIVMx 00 XT2CLK 01 10 11 Divider /1/2/4/8 0 1 MCLK CPUOFF
XOUT
0V LFXT1 Oscillator
XT2OFF XT2IN XT
Main System Clock
XT2OUT
XT2 Oscillator MODx
VCC DCOR SCG0 RSELx DCOx
Modulator SELS 0 1 DCOCLK DIVSx SCG1
0 1 P2.5/Rosc
off
DC
Generator
n DCO n+1
0 1
Divider /1/2/4/8
0 1 SMCLK
Sub System Clock
Note:
XT2 Oscillator
The XT2 Oscillator is not present on MSP430x11xx or MSP430x12xx devices. The LFXT1CLK is used in place of XT2CLK.
Basic Clock Module
19
Basic Clock Module Operation
4.2 Basic Clock Module Operation

After a PUC, MCLK and SMCLK are sourced from DCOCLK at ~800 kHz (see device-specific datasheet for parameters) and ACLK is sourced from LFXT1 in LF mode. Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable portions of the basic clock module. See Chapter System Resets, Interrupts and Operating Modes. The DCO CTL, BCSC TL1, a nd BCSC TL2 reg isters confi gure the b asic clock module The basic clock can be configured or reconfigured by software at any time during program execution, for example:
BIS.B #RSEL2+RSEL1+RSEL0,&BCSCTL1 BIS.B #DCO2+DCO1+DCO0,&DCOCTL ; ;
Set
max
DCO
frequency
4.2.1
Basic Clock Module Features for Low-Power Applications

Conflicting requirements typically exist in battery-powered MSP430x1xx applications:
- Low clock frequency for energy conservation and time keeping - High clock frequency for fast reaction to events and fast burst processing
capability
The basic clock module addresses the above conflicting requirements by allowing the user to select from the three available clock signals: ACLK, MCLK, and SMCLK. For optimal low-power performance, the ACLK can be configured to oscillate with a low-power 32,786-Hz watch crystal, providing a stable time base for the system and low power stand-by operation. The MCLK can be configured to operate from the on-chip DCO that can be only activated when requested by interrupt-driven events. The SMCLK can be configured to operate from a crystal or the DCO, depending on peripheral requirements. A flex ible c lock di stribution and div ider system is provided to fine tune the individual clock requirements.
20
Basic Clock Module
Adjusting the DCO frequency

After a PUC, the internal resistor is selected for the DC generator, RSELx = 4, and DCOx = 3, allowing the DCO to start at a mid-range frequency. MCLK and SMCLK are sourced from DCOCLK. Because the CPU executes code from MCLK, which is sourced from the fast-starting DCO, code execution begins from PUC in less than 6 s. The typical DCOx and RSELx ranges and steps are shown in Figure 45. The frequency of DCOCLK is set by the following functions:
- The current injected into the DC generator by either the internal or external
resistor defines the fundamental frequenc y. The DCOR bit selects the internal or external resistor.
- The three RSELx bits select one of eight nominal frequency ranges for the
DCO. These ranges are de fined for an ind ividual device in t he device-specific data sheet.
- The three DCOx bits divide the DCO range selected by the RSELx bits into
8 frequency steps, separated by approximately 10%.
- The five MODx bits, switch between the frequency selected by the DCOx
bits and the next higher frequency set by DCOx+1. W hen DCOx = 07h, the MODx bits have no effect because the DCO is already at the highest setting for the selected RSELx range.
Figure 45. Typical DCOx Range and RSELx Steps

fDCO 10000 kHz RSEL=7 RSEL=6 RSEL=5 RSEL=4 1000 kHz RSEL=3 RSEL=2 RSEL=1 RSEL=0 100 kHz
DCO=0
DCO=1
DCO=2
DCO=3
DCO=4
DCO=5
DCO=6
DCO=7
Basic Clock Module
21
4.2.6
Basic Clock Module Fail-Safe Operation

The basic clock m odule incorporates an oscillator-fault detection fail-safe f eature. The o scillator fa ult detector is an analog circuit that monitors the LFXT1CLK (in HF mode) and the XT2CLK. An oscillator fault is detected when either clock signal is not present for approximately 50 s. W hen an oscillator fault is detected, and when MCLK is sourced from either LFXT1 in HF mode or XT2, MCLK is automatically switched to the DCO for its clock source. This allo ws code executi on to c on tinue, even though the cr ystal oscillator has stopped. When OFIFG is set and OFIE is set, an NMI interrupt is requested. The NMI interrupt service routine can test the OFIFG flag to determine if an oscillator fault occurred. The OFIFG flag must be cleared by software. Note: No Oscillator Fault Detection for LFXT1 in LF Mode Oscillator fault detection is only applicable for LFXT1 in HF mode and XT2. There is no oscillator fault detection for LFXT1 in LF mode. OFIFG is set by the oscillator fault signal, XT_OscFault. XT_OscFault is set at POR, when LFXT1 has an oscillator fault in HF mode, or when XT2 has an oscillator fault. W hen XT2 or LFXT1 in HF mode is stopped with software the XT_OscFault signal becomes active immediately, rem ains active until the oscillator is re-started, and becomes inactive approximately 50 s after the oscillator re-starts as shown in Figure 48.
Figure 49. Oscillator-Fault Signal
V CC software enables OSC XT1OFF/ XT2OFF LFXT1CLK/ XT2CLK 50 us XT_OscFault 50 us 50 us software disables OSC
OSC faults
22
Basic Clock Module
Basic Clock Module Registers
DCOCTL, DCO Control Register

7 6 DCOx rw0 rw1 rw1 rw0 rw0 5 4 3 2 MODx rw0 rw0 rw0 1 0
DCOx MODx
Bits 7-5 Bits 4-0
DCO frequency select. These bits select which of the eight discrete DCO frequencies of the RSELx setting is selected. Modulator selection. These bits define how often the fDCO+1 frequency is used within a period of 32 DCOCLK cycles. During the remaining clock cycles (32MOD) the fDCO frequency is used. Not useable when DCOx=7.
BCSCTL1, Basic Clock System Control Register 1

7 XT2OFF rw(1) 6 XTS rw(0) rw(0) 5 DIVAx rw(0) 4 3 XT5V rw0 rw1 2 1 RSELx rw0 rw0 0
XT2OFF
Bit 7
XT2 off. This bit turns off the XT2 oscillator 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK. LFXT1 mode select. 0 Low frequency mode 1 High frequency mode Divider for ACLK 00 /1 01 /2 10 /4 11 /8 Unused. XT5V should always be reset. Resistor Select. The internal resistor is selected in eight different steps. The value of the resistor defines the nominal frequency. The lowest nominal frequency is selected by setting RSELx=0.
XTS
Bit 6
DIVAx
Bits 5-4
XT5V RSELx
Bit 3 Bits 2-0
Basic Clock Module
23
Basic Clock Module Registers
BCSCTL2, Basic Clock System Control Register 2

7 SELMx rw(0) rw(0) rw(0) 6 5 DIVMx rw(0) 4 3 SELS rw0 rw0 2 DIVSx rw0 1 0 DCOR rw0
SELMx
Bits 7-6
Select MCLK. These bits select the MCLK source. 00 DCOCLK 01 DCOCLK 10 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when XT2 oscillator not present on-chip. 11 LFXT1CLK Divider for MCLK 00 /1 01 /2 10 /4 11 /8 Select SMCLK. This bit selects the SMCLK source. 0 DCOCLK 1 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when XT2 oscillator not present on-chip. Divider for SMCLK 00 /1 01 /2 10 /4 11 /8 DCO resistor select 0 Internal resistor 1 External resistor
DIVMx
BitS 5-4
SELS
Bit 3
DIVSx
BitS 2-1
DCOR
Bit 0
24
Basic Clock Module
Flash Mem ory I ntrod uctio n

5.1 Flash Memory Introduction
The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has three registers, a timing generator, and a voltage generator to supply program and erase voltages. MSP430 flash memory features include:
- Internal programming voltage generation - Bit, b yte or word progra mmable - Ultralow-po wer o per atio n - S egme nt erase an d mass er ase
The block diagram of the flash memory and controller is shown in Figure 51. Note: Minimum VCC During Flash Write or Erase The minimum VCC voltage during a flash write or erase operation is 2.7 V. If VCC falls below 2.7 V during a write or erase, the result of the write or erase will be unpredictable.
Figure 51. Flash Memory Module Block Diagram
MAB
MDB Address Latch Data Latch
FCTL1
FCTL2
Enable Address Latch Flash Memory Array
FCTL3
Timing Generator
Enable Data Latch
Programming Voltage Generator
25
Flash Memory Controller
Flash Memory Segmentation
5.2 Flash Memory Segmentation

MSP430 flash m em ory is partitioned into segm ents. Single bits, bytes, or words can be written to flash memory, but the segment is the smallest size of flash memory that can be erased. The flash memory is partitioned into main and information memory sections. There is no difference in the operation of the main and information memory se cti ons. Code or data c an be locat ed in eit her se cti on. The d iff erenc es between the two sections are the segment size and the physical addresses. The information memory has two 128-byte segments (MSP430F1101 devices have only one). The main memory has two or more 512-byte segments. See the device-specific datasheet for the complete memory map of a device. The segments are further dividing into blocks. A block is 64 bytes, starting at 0xx00h, 0xx40h, 0xx80h, or 0xxC0h, and ending at 0xx3Fh, 0xx7Fh, 0xxBFh, or 0xxFFh. Figure 52 shows the flash segmentation using an example of 4-KB flash that has eight main segments and both information segments.
Figure 52. Flash Memory Segments, 4-KB Example

4 KB + 256 byte FFFFh 4-kbyte Flash Main Memory F000h 10FFh 1000h 256-byte Flash Information Memory FFFFh FE00h FDFFh FC00h Segment0 Segment1 Segment2 Segment3 Segment4 Segment5 Segment6 F000h 10FFh Segment7 SegmentA SegmentB xxFFh xxC0h xxBFh xx80h xx7Fh xx40h xx3Fh xx00h Block Block Block Block
1000h
26
Flash Memory Registers
FCTL1, Flash Memory Control Register

15 14 13 12 11 10 9 8
FRKEY, Read as 096h FWKEY, Must be written as 0A5h
7 BLKWRT rw0
6 WRT rw0
5 Reserved r0
4 Reserved r0
3 Reserved r0
2 MERAS rw0
1 ERASE rw0
0 Reserved r0
FRKEY/ FWKEY BLKWRT
Bits 15-8 Bit 7
FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC will be generated. Block write mode. W RT must also be set for block write mode. BLKW RT is automatically reset when EMEX is set. 0 Block-write mode is off 1 Block-write mode is on W rite. This bit is used to select any write mode. W RT is automatically reset when EMEX is set. 0 Write mode is off 1 Write mode is on Reserved. Always read as 0. Mass erase and erase. These bits are used together to select the erase mode. MERAS and ERASE are automatically reset when EMEX is set.
MERAS ERASE 0 0 1 1 0 1 0 1 No erase Erase individual segment only Erase all main memory segments Erase all main and information memory segments Erase Cycle
WRT
Bit 6
Reserved MERAS ERASE
Bits 5-3 Bit 2 Bit 1
Reserved
Bit 0
Reserved. Always read as 0.
27
FCTL2, Flash Memory Control Register

15 14 13 12 11 10 9 8
FWKEYx, Read as 096h Must be written as 0A5h
7 FSSELx rw0
3 FNx
rw1
rw-0
rw-0
rw-0
rw0
rw-1
rw0
FWKEYx FSSELx
Bits 15-8 Bits 76
FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC will be generated. Flash controller clock source select 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK Flash controller clock divider. These six bits select the divider for the flash controller clock. The divisor value is FNx + 1. For example, when FNx=00h, the divisor is 1. W hen FNx=03Fh the divisor is 64.
FNx
Bits 5-0
28
FCTL3, Flash Memory Control Register FCTL3

15 14 13 12 11 10 9 8
FWKEYx, Read as 096h Must be written as 0A5h
7 Reserved r0
6 Reserved r0
5 EMEX rw-0
4 LOCK rw-1
3 WAIT r-1
2 ACCVIFG rw0
1 KEYV rw-(0)
0 BUSY r(w)0
FWKEYx Reserved EMEX
Bits 15-8 Bits 7-6 Bit 5
FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC will be generated. Reserved. Always read as 0. Emergency exit 0 No emergency exit 1 Emergency exit Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit c an be set a nytime during a byte/word write or erase opera tion and the operation will complete normally. In the block write mode if the LOCK bit is set while BLKW RT=W AIT=1, then BLKW RT and W AIT are reset and the mode ends normally. 0 Unlocked 1 Locked Wait. Indicates the flash memory is being written to. 0 The flash memory is not ready for the next byte/word write 1 The flash memory is ready for the next byte/word write Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash security key violation. This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set. KEYV must be reset with software. 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly Busy. This bit indicates the status of the flash timing generator. 0 Not Busy 1 Busy
LOCK
Bit 4
WAIT
Bit 3
ACCVIFG
Bit 2
KEYV
Bit 1
BUSY
Bit 0
29
ACCVIE Bit 5 Flash memory access violation interrupt enable bit is avilable in IE1
Hardw are M ultiplier Introd uction

7.1 Hardware Multiplier Introduction
The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions. The hardware multiplier supports: Unsigned multiply
- Signe d m ulti ply -
Unsi gned mu ltiply ac cumulate
- Signe d multip ly accumu late - 16 16 bits, 16 8 bits, 8 16 bits, 8 8 bits
The hardware multiplier block diagram is shown in Figure 71.
Figure 71. Hardware Multiplier Block Diagram

15 rw MPY 130h MPYS 132h OP1 MAC 134h MACS 136h 16 x 16 Multipiler Accessible Register 15 rw OP2 138h 0 0
MPY = 0000
MACS MPYS MAC MPY, MPYS Multiplexer
32bit Adder MAC, MACS
32bit Multiplexer
SUMEXT 13Eh 15 r 0
S 31
RESHI 13Ch rw
RESLO 13Ah rw 0
30
Hardware Multiplier
Hardware Multiplier Operation
7.2 Hardware Multiplier Operation

The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, RESLO, RESHI, and SUMEXT. RESLO stores the low word of the result, RESHI stores the high word of the result, and SUMEXT stores information about the result. The result is ready in three MCLK cycles and can be read with the next instruction after writing to OP2, except when using an indirect addressing mode to access the result. W hen using indirect addressing for the result, a NOP is required before the result is ready.
7.2.1
Operand Registers
The operand one register OP1 has four addresses, shown in Table 71, used to select the multiply mode. Writing the first operand to the desired address selects the type of multiply operation but does not start any operation. W riting the second operand to the operand two register OP2 initiates the multiply operation. Writing OP2 starts the selected operation with the values stored in OP1 and OP2. The result is written into the three result registers RESLO, RESHI, and SUMEXT. Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for successive operations. It is not necessary to re-write the OP1 value to perform the operations.
Table 71.OP1 addresses

OP1 Address 0130h 0132h 0134h 0136h Register Name MPY MPYS MAC MACS Operation Unsigned multiply Signed multiply Unsigned multiply accumulate Signed multiply accumulate
Hardware Multiplier
31
D MA Controller Bl ock Diagr am

DMA0TSELx 4 DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USART0 data received USART0 transmit ready DAC12_0IFG ADC12IFGx TACCR0_CCIFG TBCCR0_CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA2IFG DMAE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1110 1111 2 Halt ROUNDROBIN DMADSTINCRx DMADSTBYTE DMA Channel 0 DMA0SA DMA0DA DMA0SZ DMASRSBYTE DMASRCINCRx DT DMADTx 3 JTAG Active NMI Interrupt Request ENNMI
DMAEN
DMA1TSELx 4 DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USART0 data received USART0 transmit ready DAC12_0IFG ADC12IFGx TACCR0_CCIFG TBCCR0_CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA0IFG DMAE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1110 1111 DMADSTINCRx DMADTx DMADSTBYTE 3 DMA Channel 1 DMA1SA DMA1DA DMA1SZ 2 DMASRSBYTE DMASRCINCRx DT
Address Space
DMAEN
DMA2TSELx 4 DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USART0 data received USART0 transmit ready DAC12_0IFG ADC12IFGx TACCR0_CCIFG TBCCR0_CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA1IFG DMAE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1110 1111 2
DMADSTINCRx DMADTx DMADSTBYTE 3 DMA Channel 2 DMA2SA DMA2DA DMA2SZ DT
DMASRSBYTE DMASRCINCRx
DMAEN
DMAONFETCH Halt CPU
32
8.2 DMA Operation

The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections.
8.2.1
DMA Addressing Modes

The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 82. The addressing modes are:
- F ix ed addre ss to fixed a ddr ess - Fixed address to block of addresses - Blo ck of addre sses to fixed addre ss - Block of addresses to block of addresses
The addressing modes are configured with the DMASRCINCRx and DMADSTINCRx control bits. The DMASRCINCRx bits select if the source address is incremented, decremented, or unchanged after each transfer. The DMADSTINCRx bits select if the destination address is incremented, decremented, or unchanged after each transfer. Transfers may be byte-to-byte, word-to-word, byte-to-word, or word-to-byte. When t ransf erri ng w ord- to-byte, only t he low er byte of t he s ource-w ord transfers. W hen transferring byte-to-word, the upper byte of the destination-word is cleared when the transfer occurs.
Figure 82. DMA Addressing Modes
DMA Controller
Address Space
DMA Controller
Address Space
Fixed Address To Fixed Address
Fixed Address To Block Of Addresses
DMA Controller
Address Space
DMA Controller
Address Space
Block Of Addresses To Fixed Address
Block Of Addresses To Block Of Addresses
33
8.2.2
DMA Transfer Modes

The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 81. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeat ed blo ck mode. The t ransfer mode is c onfi gured independently from the addressing mode. Any addressing mode can be used with any transfer mode.
Table 81.DMA Transfer Modes

DM AD T x 000 Tra nsfer Mode Single transfer Description Each transfer requires a trigger. DMAEN is automatically cleared when DMAxSZ transfers have been made. A complete block is transferred with one trigger. DMAEN is automatically cleared at the end of the block transfer. CPU activity is interleaved with a block transfer. DMAEN is automatically cleared at the end of the burst-block transfer. Each transfer requires a trigger. DMAEN remains enabled. A complete block is transferred with one trigger. DMAEN remains enabled. CPU activity is interleaved with a block transfer. DMAEN remains enabled.
001
Block transfer
010, 011
Burst-block transfer Repeated single transfer Repeated block transfer Repeated burst-block transfer
100 101 110, 111
34
DMACTL0, DMA Control Register 0

15 14 Reserved rw(0) rw(0) rw(0) rw(0) rw(0) 13 12 11 10 DMA2TSELx rw(0) rw(0) rw(0) 9 8
6 DMA1TSELx
2 DMA0TSELx
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
Reserved DMA2 TSELx
Bits 1512 Bits 118
Reserved DMA trigger select. These bits select the DMA transfer trigger. 0000 DMAREQ bit (software trigger) 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFG0 (UART/SPI mode), USART0 data received (I2C mode) 0100 UTXIFG0 (UART/SPI mode), USART0 transmit ready (I2C mode) 0101 DAC12_0CTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCR0 CCIFG bit 1000 TBCCR0 CCIFG bit 1001 URXIFG1 bit 1010 UTXIFG1 bit 1011 Multiplier ready 1100 No action 1101 No action 1110 DMA0IFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111 External trigger DMAE0 Same as DMA2TSELx Same as DMA2TSELx
DMA1 TSELx DMA0 TSELx
Bits 74 Bits 3-0
35
DMACTL1, DMA Control Register 1

15 0 r0 14 0 r0 13 0 r0 12 0 r0 11 0 r0 10 0 r0 9 0 r0 8 0 r0
7 0 r0
6 0 r0
5 0 r0
4 0 r0
3 0 r0
2 DMA ONFETCH rw(0)
1 ROUND ROBIN rw(0)
0 ENNMI rw(0)
Reserved DMA ONFETCH ROUND ROBIN ENNMI
Bits 153 Bit 2
Reserved. Read only. Always read as 0. DMA on fetch 0 The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger Round robin. This bit enables the round-robin DMA channel priorities. 0 DMA channel priority is DMA0 DMA1 DMA2 1 DMA channel priority changes with each transfer Enable NMI. This bit enables the interruption of a DMA transfer by an NMI interrupt. W hen an NMI interrupts a DMA transfer, the current transfer is completed normally, further transfers are stopped, and DMAABORT is set. 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer
Bit 1
Bit 0
36
DMAxCTL, DMA Channel x Control Register

15 Reserved rw(0) rw(0) 14 13 DMADTx rw(0) rw(0) 12 11 10 9 8
DMADSTINCRx rw(0) rw(0)
DMASRCINCRx rw(0) rw(0)
7 DMA DSTBYTE rw(0)
6 DMA SRCBYTE rw(0)
5 DMALEVEL rw(0)
4 DMAEN rw(0)
3 DMAIFG rw(0)
2 DMAIE rw(0)
1 DMA ABORT rw(0)
0 DMAREQ rw(0)
Reserved DMADTx
Bit 15 Bits 1412
Reserved DMA Transfer mode. 000 Single transfer 001 Block transfer 010 Burst-block transfer 011 Burst-block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst-block transfer 111 Repeated burst-block transfer DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer. W hen DMADSTBYTE=1, the destination address increments/decrements by one. W hen DMADSTBYTE=0, the destination address increments/decrements by two. The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented. DMAxDA is not incremented or decremented. 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA source increment. This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer. W hen DMASRCBYTE=1, the source address increments/decrements by one. W hen DMASRCBYTE=0, the source address increments/decrements by two. The DMAxSA is copied into a temporary register and the temporary register is increm ented or decrem ented. DMAxSA is not increm ented or decremented. 00 Source address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented DMA destination byte. This bit selects the destination as a byte or word. 0 Word 1 Byte
DMA DSTINCRx
Bits 1110
DMA SRCINCRx
Bits 98
DMA DSTBYTE
Bit 7
37
DMA SRCBYTE DMA LEVEL
Bit 6
DMA source byte. This bit selects the source as a byte or word. 0 Word 1 Byte DMA level. This bit selects between edge-sensitive and level-sensitive triggers. 0 Edge sensitive (rising edge) 1 Level sensitive (high level) DMA enable 0 Disabled 1 Enabled DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMA interrupt enable 0 Disabled 1 Enabled DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI. 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0 No DMA start 1 Start DMA
Bit 5
DMAEN
Bit 4
DMAIFG
Bit 3
DMAIE
Bit 2
DMA ABORT DMAREQ
Bit 1
Bit 0
DMAxSA, DMA Source Address Register

15 14 13 12 DMAxSAx rw rw rw rw rw rw rw rw 11 10 9 8
4 DMAxSAx
rw
rw
rw
rw
rw
rw
rw
rw
DM AxS Ax Bits 150
DMA source address. The source address register points to the DMA source address for single transfers or the first source address for block transfers. The source address register remains unchanged during block and burst-block transfers.
38
Digital I/ O Registers
9.3 Digital I/O Registers
Seven registers are used to configure P1 and P2. Four registers are used to configure ports P3 - P6. The digital I/O registers are listed in Table 91.
Table 91.Digital I/O Registers

Port P1 Register Input Output Short Form P1IN P1OUT P1DIR P1IFG P1IES P1IE P1SEL P2IN P2OUT P2DIR P2IFG P2IES P2IE P2SEL P3IN P3OUT P3DIR P3SEL P4IN P4OUT P4DIR P4SEL P5IN P5OUT P5DIR P5SEL P6IN P6OUT P6DIR P6SEL Address 020h 021h 022h 023h 024h 025h 026h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 030h 031h 032h 033h 034h 035h 036h 037h Register Type Read only Read/write Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read only Read/write Read/write Read/write Read only Read/write Read/write Read/write Read only Read/write Read/write Read/write Initial State Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC
Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select
P2
Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select
P3
Input Output Direction Port Select
P4
P5
P6
Digital I/O
39
Watchdog T im er Introduction
Figure 101. Watchdog Timer Block Diagram
WDTCTL 4 Int. Flag WDTQn Y 3 2 1 Pulse Generator A B Clear (Asyn) CLK Q6 0 Q9 Q13 Q15 16bit Counter 1 0 1 1 0 1 0 EQU Write Enable Low Byte 16bit Password Compare MSB MDB
PUC
EQU
R/W
SMCLK ACLK
1 1 A EN
WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0 LSB
Watchdog Timer
40
Watchdog Timer Registers
WDTCTL, Watchdog Timer Register

15 14 13 12 11 10 9 8
Read as 069h WDTPW, must be written as 05Ah
7 WDTHOLD rw0
6 WDTNMIES rw0
5 WDTNMI rw0
4 WDTTMSEL rw0
3 WDTCNTCL r0(w)
2 WDTSSEL rw0
1 WDTISx rw0
rw0
WDTPW WDTHOLD
Bits 15-8 Bit 7
Watchdog timer password. Always read as 069h. Must be written as 05Ah, or a PUC will be generated. Watchdog timer hold. This bit stops the watchdog timer. Setting W DTHOLD = 1 when the W DT is not in use conserves power. 0 Watchdog timer is not stopped 1 Watchdog timer is stopped W atchdog timer NMI edge select. This bit selects the interrupt edge for the NMI interrupt when W DTNMI = 1. Modifying this bit can trigger an NMI. Modify this bit when W DTNMI = 0 to avoid triggering an accidental NMI. 0 NMI on rising edge 1 NMI on falling edge Watchdog timer NMI select. This bit selects the function for the RST/NMI pin. 0 Reset function 1 NMI function Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer counter clear. Setting W DTCNTCL = 1 clears the count value to 0000h. W DTCNTCL is automatically reset. 0 No action 1 WDTCNT = 0000h Watchdog timer clock source select 0 SMCLK 1 ACLK Watchdog timer interval select. These bits select the watchdog timer interval to set the W DTIFG flag and/or generate a PUC. 00 Watchdog clock source /32768 01 Watchdog clock source /8192 10 Watchdog clock source /512 11 Watchdog clock source /64
WDTNMIES
Bit 6
WDTNMI
Bit 5
WDTTMSEL
Bit 4
WDTCNTCL
Bit 3
WDTSSEL
Bit 2
WDTISx
Bits 1-0
41
W atch d o g Tim er T a p s:
S S EL 0 0 1 0 1 0 1 1 IS 1 1 1 1 0 1 0 0 0 IS 0 1 0 1 1 0 0 1 0 Int e rval( ms) 0.064 tSMCLK x 64 0 .5 1 .9 8 16 32 25 0 10 00 tS M CLK x 51 2 tACLK x 64 tS M CLK x 8192 tAC L K
x 51 2
tS M CLK x 3276 8 tACLK x 8192 tACLK x 32768
Ti m er _A Introduction
11.1 Timer_A Introduction
Timer_A is a 16-bit timer/counter with three capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated fr om the counter on overflow c onditi ons and from each of the capture/compare registers. Timer_A features include:
- Asynchronous 16-bit timer/counter with four operating modes -
Selectable and configurable clock source

- Three configurable capture/compare registers - Configurable outputs with PW M capability - Async hro nous inpu t and outp ut latchi ng - Interrupt vector register for fast decoding of all Timer_A interrupts The
block diagram of Timer_A is shown in Figure 111. Note: Use of the Word Count Count is used throughout this chapter. It means the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then an associated action will not take place.
42
Timer_A
Timer_A Introduction
Figure 111. Timer_A Block Diagram
TASSELx
IDx
Timer Clock 15 0 16bit Timer TAR Clear RC
MCx
Timer Block
TACLK ACLK SMCLK INCLK
00 01 10 11
Divider 1/2/4/8
Count Mode
EQU0 Set TAIFG
TACLR CCR0 CCR1 CCR2 CCISx CMx logic COV SCS CCI2A CCI2B GND VCC 00 01 10 11 CCI Capture Mode Timer Clock Sync 0 1 15 TACCR2 0
Compararator 2 EQU2 CAP
SCCI
A EN
0 1 OUT
Set TACCR2 CCIFG
EQU0
Output Unit2
Timer Clock
Set Q Reset
OUT2 Signal
OUTMODx
POR
Timer_A
43
Timer_A Operation
Output ExampleTimer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 1112 using TACCR0 and TACCR1.
Figure 1112.Output ExampleTimer in Up Mode
0FFFFh TACCR0 TACCR1
0h Output Mode 1: Set
Output Mode 2: Toggle/Reset
Output Mode 3: Set/Reset
Output Mode 4: Toggle
Output Mode 5: Reset
Output Mode 6: Toggle/Set
Output Mode 7: Reset/Set EQU0 TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 TAIFG Interrupt Events
4 4
Timer_A
Timer_A Registers
TACTL, Timer_A Control Register

15 14 13 Unused rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) 12 11 10 9 TASSELx rw(0) rw(0) 8
7 IDx rw(0)
5 MCx
3 Unused
2 TACLR w(0)
1 TAIE rw(0)
0 TAIFG rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
Unused TASSELx
Bits 15-10 Bits 9-8
Unused Timer_A clock source select 00 TACLK 01 ACLK 10 SMCLK 11 INCLK Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8 Mode control. Setting MCx = 00h when Timer_A is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TACCR0 10 Continuous mode: the timer counts up to 0FFFFh 11 Up/down mode: the timer counts up to TACCR0 then down to 0000h Unused Timer_A clear. Setting this bit resets TAR, the TACLK divider, and the count direction. The TACLR bit is automatically reset and is always read as zero. Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled Timer_A interrupt flag 0 No interrupt pending 1 Interrupt pending
IDx
Bits 7-6
MCx
Bits 5-4
Unused TACLR TAIE
Bit 3 Bit 2 Bit 1
TAIFG
Bit 0
45
Timer_A
Timer_A Registers
TAR, Timer_A Register

15 14 13 12 TARx rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) 11 10 9 8
4 TARx
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
TARx
Bits 15-0
Timer_A register. The TAR register is the count of Timer_A.
Timer_A
46
Timer_A Registers
TACCTLx, Capture/Compare Control Register

15 CMx rw(0) rw(0) rw(0) 14 13 CCISx rw(0) 12 11 SCS rw(0) 10 SCCI r(0) 9 Unused r(0) 8 CAP rw(0)
6 OUTMODx
4 CCIE
3 CCI r
2 OUT rw(0)
1 COV rw(0)
0 CCIFG rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
CMx
Bit 15-14
Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture/compare input select. These bits select the TACCRx input signal. See the device-specific datasheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be read via this bit Unused. Read only. Always read as 0. Capture mode 0 Compare mode 1 Capture mode Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0 because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set
CCISx
Bit 13-12
SCS
Bit 11
SCCI Unused CAP
Bit 10 Bit 9 Bit 8
OUTMODx
Bits 7-5
47
Timer_A
Timer_A Registers CCIE
Bit 4
Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled Capture/compare input. The selected input signal can be read by this bit. Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending
CCI OUT
Bit 3 Bit 2
COV
Bit 1
CCIFG
Bit 0
TAIV, Timer_A Interrupt Vector Register

15 0 r0 14 0 r0 13 0 r0 12 0 r0 11 0 r0 10 0 r0 9 0 r0 8 0 r0
7 0 r0
6 0 r0
5 0 r0
4 0 r0
2 TAIVx
0 0
r(0)
r(0)
r(0)
r0
TAIVx
Bits 15-0
Timer_A Interrupt Vector value
TAIV Contents 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh
Interrupt Source No interrupt pending Capture/compare 1 Capture/compare 2 Reserved Reserved Timer overflow Reserved Reserved
Interrupt Flag TACCR1 CCIFG TACCR2 CCIFG TAIFG
Interrupt Priority Highest
Lowest
Timer_A
48
Ti m er _B Introduction
12.1 Timer_B Introduction
Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B features include :
- Async hro nous 16-b it timer /counter with four operating m od es and four
selectable lengths
- Selectable and configurable clock source - Three or seven configurable capture/compare registers -
Configurable outputs with PW M capability

- Double-buffered compare latches with synchronized loading - Interrupt vector register for fast decoding of all Timer_B interrupts The
block diagram of Timer_B is shown in Figure 121. Note: Use of the Word Count Count is used throughout this chapter. It means the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then an associated action does not take place.
12.1.1 Similarities and Differences From Timer_A

Timer_B is identical to Timer_A with the following exceptions:
- The length of Timer_B is programmable to be 8, 10, 12, or 16 bits. - Timer_B TBCCRx registers are double-buffered and can be grouped. - All
Timer_B outputs can be put into a high-impedance state.

- The SCCI bit function is not implemented in Timer_B.
49
Timer_B
Timer_B Introduction
Figure 121. Timer_B Block Diagram

TBSSELx IDx Timer Clock 15 TBCLK ACLK SMCLK 00 01 10 11 TBCLR TBCLGRPx Divider 1/2/4/8 Clear 16bit Timer TBR 8 RC 10 12 16 0 Count Mode CNTLx 00 01 10 11 CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCISx CMx logic COV SCS CCI6A CCI6B GND VCC 00 01 10 11 CCI VCC TBR=0 EQU0 UP/DOWN Capture Mode Timer Clock CLLDx Sync 0 1 Load 15 TBCCR6 0 CCR6 Set TBIFG EQU0 MCx Timer Block
Group Load Logic
Group Load Logic
Compare Latch TBCL6
00 01 10 11 CCR5 CCR4 CCR1 0 1 OUT Set TBCCR6 CCIFG Compararator 6 EQU6 CAP
EQU0
Output Unit6
Timer Clock
D S et Q Reset
OUT6 Signal
OUTMODx
POR
Timer_B
50
Timer_B Registers
Timer_B Control Register TBCTL

15 Unused rw(0) 14 TBCLGRPx rw(0) rw(0) rw(0) 13 12 CNTLx rw(0) 11 10 Unused rw(0) 9 TBSSELx rw(0) rw(0) 8
7 IDx rw(0)
5 MCx
3 Unused
2 TBCLR w(0)
1 TBIE rw(0)
0 TBIFG rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
Unused TBCLGRP
Bit 15 Bit 14-13
Unused TBCLx group 00 Each TBCLx latch loads independently 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update) TBCL0 independent 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update) Counter Length 00 16-bit, TBR(max) = 0FFFFh 01 12-bit, TBR(max) = 0FFFh 10 10-bit, TBR(max) = 03FFh 11 8-bit, TBR(max) = 0FFh Unused Timer_B clock source select. 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8 Mode control. Setting MCx = 00h when Timer_B is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TBCL0 10 Continuous mode: the timer counts up to the value set by TBCNTLx 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h
CNTLx
Bits 12-11
Unused TBSSELx
Bit 10 Bits 9-8
IDx
Bits 7-6
MCx
Bits 5-4
Timer_B
51
Timer_B Registers Unused TBCLR TBIE
Bit 3 Bit 2 Bit 1
Unused Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled Timer_B interrupt flag. 0 No interrupt pending 1 Interrupt pending
TBIFG
Bit 0
TBR, Timer_B Register

15 14 13 12 TBRx rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) 11 10 9 8
4 TBRx
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
TBRx
Bits 15-0
Timer_B register. The TBR register is the count of Timer_B.
52
Timer_B
Timer_B Registers
TBCCTLx, Capture/Compare Control Register

15 CMx rw(0) rw(0) rw(0) 14 13 CCISx rw(0) 12 11 SCS rw(0) rw(0) 10 CLLDx r(0) 9 8 CAP rw(0)
6 OUTMODx
4 CCIE
3 CCI r
2 OUT rw(0)
1 COV rw(0)
0 CCIFG rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
CMx
Bit 15-14
Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture/compare input select. These bits select the TBCCRx input signal. See the device-specific datasheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture Compare latch load. These bits select the compare latch load event. 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to 0 (up or continuous mode) TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode) 11 TBCLx loads when TBR counts to TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set
CCISx
Bit 13-12
SCS
Bit 11
CLLDx
Bit 10-9
CAP
Bit 8
OUTMODx
Bits 7-5
Timer_B
53
Timer_B Registers CCIE
Bit 4
Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled Capture/compare input. The selected input signal can be read by this bit. Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending
CCI OUT
Bit 3 Bit 2
COV
Bit 1
CCIFG
Bit 0
54
Timer_B
Timer_B Registers
TBIV, Timer_B Interrupt Vector Register

15 0 r0 14 0 r0 13 0 r0 12 0 r0 11 0 r0 10 0 r0 9 0 r0 8 0 r0
7 0 r0
6 0 r0
5 0 r0
4 0 r0
2 TBIVx
0 0
r(0)
r(0)
r(0)
r0
TBIVx
Bits 15-0
Timer_B interrupt vector value
TBIV Contents 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh
Interrupt Source No interrupt pending Capture/compare 1 Capture/compare 2 Capture/compare 3 Capture/compare 4 Capture/compare 5 Capture/compare 6 Timer overflow

Interrupt Flag TBCCR1 CCIFG TBCCR2 CCIFG TBCCR3 CCIFG TBCCR4 CCIFG TBCCR5 CCIFG TBCCR6 CCIFG TBIFG
MSP430x14x, MSP430x16x devices only
Lowest
Timer_B
55
U S ART I ntrod uction: U ART M ode

13.1 USART Introduction: UART Mode
In as ynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared. UART mode features include:
- 7- or 8-bit data with odd, even, or non-parity - Independent transmit and receive shift registers -
Separate transmit and receive buffer registers LSB-first data transmit and receive
- B uilt-in idle-li ne
and address-b it multiprocessor systems
comm uni cation prot ocol s f or
- Receiver start-edge detection for auto-wake up from LPMx modes - Programmable baud rate with modulation for fractional baud rate support - Status flags for error detection and suppression and address detection - Independent interrupt capability for receive and transmit
Figure 131 shows the USART when configured for UART mode.
56
USART Peripheral Interface, UART Mode
USART Introduction: UART Mode
Figure 131. USART Block Diagram: UART Mode
SW RST URXEx* URXEIE URXWIE URXIFGx* SYNC= 0
FE PE OE BRK
Receive Control
Receive Status
Receiver Buffer UxRXBUF
LISTEN 0
MM 1 0
SYNC 1 0 1 URXD SOMI
RXERR
RXWAKE
Receiver Shift Register 1
SSEL1 SSEL0 SP UCLKI ACLK SMCLK SMCLK 00 01 10 11 SP
CHAR
PEV
PENA UCLKS
BaudRate Generator Prescaler/Divider UxBRx Modulator UxMCTL CHAR PEV PENA
STE
UTXD
WUT
Transmit Shift Register
SIMO
0 TXWAKE UTXIFGx* Transmit Buffer UxTXBUF
Transmit Control SYNC CKPH CKPL
SW RST UTXEx* TXEPT UCLKI
STC Clock Phase and Polarity
UCLK
* Refer to the device-specific datasheet for SFR locations
57
USART Operation: UART Mode
13.2 USART Operation: UART Mode

In UART mode, the USART transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USART. The transmit and receive functions use the same baud rate frequency.
13.2.1 USART Initialization and Reset

The USART is reset by a PUC or by setting the SWRST bit. After a PUC, the SWRST bit is automatically set, keeping the USART in a reset condition. When set, the SW RST bit resets the URXIEx, UTXIEx, URXIFGx, RXW AKE, TXW AKE, RXERR, BRK, PE, OE, and FE bits and sets the UTXIFGx and TXEPT bits. The receive and transmit enable flags, URXEx and UTXEx, are not altered by SW RST. Clearing SW RST releases the USART for operation. See also chapter USART Module, I2C mode for USART0 when reconfiguring from I2C mode to UART mode. Note: Initializing or Re-Configuring the USART Module The required USART initialization/re-configuration process is: 1) Set SW RST (BIS.B #SWRST,&UxCTL) 2) Initialize all USART registers with SW RST = 1 (including UxCTL) 3) Enable USART module via the MEx SFRs (URXEx and/or UTXEx) 4) Clear SW RST via software (BIC.B #SWRST,&UxCTL) 5) Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx) Failure to follow this process may result in unpredictable USART behavior.
13.2.2 Character Format

The UART character format, shown in Figure 132, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit (address-bit mode), and one or two stop bits. The bit period is defined by the selected clock source and setup of the baud rate registers.
Figure 132. Character Format

Mark Space [2nd Stop Bit, SP = 1] [Parity Bit, PENA = 1] [Address Bit, MM = 1] [Optional Bit, Condition] [8th Data Bit, CHAR = 1]
ST
D0
D6
D7 AD PA
SP SP
58
USART Registers: UART Mode
UxCTL, USART Control Register

7 PENA rw0 6 PEV rw0 5 SPB rw0 4 CHAR rw0 3 LISTEN rw0 2 SYNC rw0 1 MM rw0 0 SWRST rw1
PENA
Bit 7
Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Parity select. PEV is not used when parity is disabled. 0 Odd parity 1 Even parity Stop bit select. Number of stop bits transmitted. The receiver always checks for one stop bit. 0 One stop bit 1 Two stop bits Character length. Selects 7-bit or 8-bit character length. 0 7-bit data 1 8-bit data Listen enable. The LISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UTXDx is internally fed back to the receiver. Synchronous mode enable 0 UART mode 1 SPI Mode Multiprocessor mode select 0 Idle-line multiprocessor protocol 1 Address-bit multiprocessor protocol Software reset enable 0 Disabled. USART reset released for operation 1 Enabled. USART logic held in reset state
PEV
Bit 6
SPB
Bit 5
CHAR
Bit 4
LISTEN
Bit 3
SYNC
Bit 2
MM
Bit 1
SWRST
Bit 0
59
UxTCTL, USART Transmit Control Register

7 Unused rw0 6 CKPL rw0 rw0 5 SSELx rw0 4 3 URXSE rw0 2 TXWAKE rw0 1 Unused rw0 0 TXEPT rw1
Unused CKPL
Bit 7 Bit 6
Unused Clock polarity select 0 UCLKI = UCLK 1 UCLKI = inverted UCLK Source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK UART receive start-edge. The bit enables the UART receive start-edge feature. 0 Disabled 1 Enabled Transmitter wake 0 Next character transmitted is data 1 Next character transmitted is an address Unused Transmitter empty flag 0 UART is transmitting data and/or data is waiting in UxTXBUF 1 Transmitter shift register and UxTXBUF are empty or SWRST=1
SSELx
Bits 5-4
URXSE
Bit 3
TXWAKE
Bit 2
Unused TXEPT
Bit 1 Bit 0
60
UxRCTL, USART Receive Control Register

7 FE rw0 6 PE rw0 5 OE rw0 4 BRK rw0 3 URXEIE rw0 2 URXWIE rw0 1 RXWAKE rw0 0 RXERR rw0
FE
Bit 7
Framing error flag 0 No error 1 Character received with low stop bit Parity error flag. W hen PENA = 0, PE is read as 0. 0 No error 1 Character received with parity error Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. 0 No error 1 Overrun error occurred Break detect flag 0 No break condition 1 Break condition occurred Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received will set URXIFGx Receive wake-up interrupt-enable. This bit enables URXIFGx to be set when an address character is received. W hen URXEIE = 0, an address character will not set URXIFGx if it is received with errors. 0 All received characters set URXIFGx 1 Only received address characters set URXIFGx Receive wake-up flag 0 Received character is data 1 Received character is an address Receive error flag. This bit indicates a character was received with error(s). When RXERR = 1, on or more error flags (FE,PE,OE, BRK) is also set. RXERR is cleared when UxRXBUF is read. 0 No receive errors detected 1 Receive error detected
PE
Bit 6
OE
Bit 5
BRK
Bit 4
URXEIE
Bit 3
URXWIE
Bit 2
RXWAKE
Bit 1
RXERR
Bit 0
61
UxBR0, USART Baud Rate Control Register 0

7 27 rw 6 26 rw 5 25 rw 4 24 rw 3 23 rw 2 22 rw 1 21 rw 0 20 rw
UxBR1, USART Baud Rate Control Register 1

UxBRx
The valid baud-rate control range is 3 UxBR < 0FFFFh, where UxBR = {UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if UxBR <3.
UxMCTL, USART Modulation Control Register

7 m7 rw 6 m6 rw 5 m5 rw 4 m4 rw 3 m3 rw 2 m2 rw 1 m1 rw 0 m0 rw
UxMCTLx
Bits 70
Modulation bits. These bits select the modulation for BRCLK.
62
UxRXBUF, USART Receive Buffer Register

7 27 r 6 26 r 5 25 r 4 24 r 3 23 r 2 22 r 1 21 r 0 20 r
UxRXBUFx
Bits 70
The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
UxTXBUF, USART Transmit Buffer Register

UxTXBUFx
Bits 70
The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UTXDx. W riting to the transmit data buffer clears UTXIFGx. The MSB of UxTXBUF is not used for 7-bit data and is reset.
63
UBR = 32768/4800 = 6.82667 This means the Baud Rate Register, UBR1, (MSBs) is loaded with 0 and the UBR0 Register contains 6. To get a rough value for the 8-bit modulation register, UMCTL, the fractional part (0.826667) is multiplied by 8 (the number of bits in the register UMCTL). UMCTL = 0.82667 * 8 = 6.613 The rounded result, 7, is the number of 1s to be placed in to the Modulation Register, UMCTL. The resulting, corrected Baud rate with the UMCTL register containing seven 1s is: Baud rate = 32768/ ((7*7+1*6)/8) = 4766.2545 This result in an average Baud rate error of: Baud Rate Error = (4766.2545 - 4800/4800) *100 = -0.703% To get the bit sequence for the modulation register, UMCTL, that fits best, the following algorithm can be used. The fractional part of the theoretical division factor is summed eight times and if a carry to a integer part occurs, the actual mbit is set. Otherwise it is cleared. An example with the above fraction 0.82667 follows. Fraction Addition 0.82667+0.82667 = 1.65333 1.65333+0.82667 = 2.48000 2.48000+0.82667 = 3.30667 3.30667+0.82667 = 4.13333 4.13333+0.82667 = 4.96000 4.96000+0.82667 = 5.78667 5.78667+0.82667 = 6.61333 6.61333+0.82667 = 7.44000 Carry to the Integer Yes Yes Yes Yes No Yes Yes Yes UMC TL Bits m0 m1 m2 m3 m4 m5 m6 m7 1 1 1 1 0 1 1 1
The result of the calculated bits m7.m0 (11101111b) is EFh.
USA RT Introdu ction: S PI Mo de

In syn chronous mode, the USART c onne cts the M SP 430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared. SPI mode features include:
- 7- or 8-b it data length -
3-pin and 4-pin SPI operation -
Master or slave modes

- Independent transmit and receive shift registers - Separate transmit and receive buffer registers - Selectable UCLK polarity and phase control - Programmable UCLK frequenc y in master mode - Independent interrupt capability for receive and transmit
Figure 141 shows the USART when configured for SPI mode.
64
USART Peripheral Interface, SPI Mode
USART Operation: SPI Mode
14.2.2 Master Mode Figure 142. USART Master and External Slave
MASTER SLAVE
SIMO
SIMO
Receive Buffer UxRXBUF
Transmit Buffer UxTXBUF Px.x STE SOMI STE SS Port.x SOMI
SPI Receive Buffer
Receive Shift Register MSB LSB
Transmit Shift Register MSB LSB
Data Shift Register (DSR) MSB LSB COMMON SPI
MSP430 USART
UCLK
SCLK
Figure 142 shows the USART as a master in both 3-pin and 4-pin configurations. The USART initiates data transfer when data is moved to the transmit data buffer UxTXBUF. The UxTXBUF data is moved to the TX shift register when the TX shift register is empty, initiating data transfer on SIMO starting with the most-significant bit. Data on SOMI is shifted into the receive shift register on the opposite clock edge, starting with the most-significant bit. When the character is received, the receive data is moved from the RX shift register to the received data buffer UxRXBUF and the receive interrupt flag, URXIFGx, is set, indicating the RX/TX operation is complete. A set transmit interrupt flag, UTXIFGx, indicates that data has moved from UxTXBUF to the TX shift register and UxTXBUF is ready for new data. It does not indicate RX/TX completion. To receive data into the USART in m aster m ode, data must be written to UxTXBUF because receive and transmit operations operate concurrently.
Four-Pin SPI Master Mode

In 4-pin master mode, STE is used to prevent conflicts with another master. The master operates normally when STE is high. W hen STE is low:
- SIMO and UCLK are set to inputs and no longer drive the bus - The error bit FE is set indicating a communication integrity violation to be
handled by the user
A low STE signal does not reset the USART module. The STE input signal is not used in 3-pin master mode.
65
USART Operation: SPI Mode
14.2.3 Slave Mode Figure 143. USART Slave and External Master
MASTER SLAVE
SIMO
SIMO
SPI Receive Buffer Px.x STE SOMI STE
Transmit Buffer UxTXBUF
Receive Buffer UxRXBUF
SS Port.x SOMI
Data Shift Register DSR MSB COMMON SPI LSB
Transmit Shift Register MSB LSB
Receive Shift Register MSB LSB
SCLK
UCLK
MSP430 USART
Figure 143 shows the USART as a slave in both 3-pin and 4-pin c onfi gurati ons. UCLK is us ed as t he i nput for t he SPI clo ck and mu st be supplied by the external master. The data-transfer rate is determined by this clock and not by the internal baud rate generator. Data written to UxTXBUF and moved to the TX shift register before the start of UCLK is transmitted on SOMI. Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and m oved to UxRXBUF when the set num ber of bits are received. W hen data is moved from the RX shift register to UxRXBUF, the URXIFGx interrupt flag is set, indicating that data has been received. The overrun error bit, OE, is set when the previously received data is not read from UxRXBUF before new data is moved to UxRXBUF.
Four-Pin SPI Slave Mode

In 4-pin slave m ode, STE is used by the slave to enable the transm it and receive operations and is provided by the SPI master. W hen STE is low, the slave operates normally. W hen STE is high:
- Any receive operation in progress on SIMO is halted -
SOMI is set to the input direction A high STE signal does not reset the USART module. The STE input signal is not used in 3-pin slave mode.
66
USART Registers: SPI Mode
UxCTL, USART Control Register

7 Unused rw0 6 Unused rw0 5 I2C rw0 4 CHAR rw0 3 LISTEN rw0 2 SYNC rw0 1 MM rw0 0 SWRST rw1
Unused I2C
Bits 76 Bit 5
Unused I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. 0 SPI mode 1 I2C mode Character length 0 7-bit data 1 8-bit data Listen enable. The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled. The transmit signal is internally fed back to the receiver Synchronous mode enable 0 UART mode 1 SPI mode Master mode 0 USART is slave 1 USART is master Software reset enable 0 Disabled. USART reset released for operation 1 Enabled. USART logic held in reset state
CHAR
Bit 4
LISTEN
Bit 3
SYNC
Bit 2
MM
Bit 1
SWRST
Bit 0
Applies to USART0 on MSP430x15x and MSP430x16x devices only.
67
UxTCTL, USART Transmit Control Register

7 CKPH rw0 6 CKPL rw0 rw0 5 SSELx rw0 4 3 Unused rw0 2 Unused rw0 1 STC rw0 0 TXEPT rw1
CKPH
Bit 7
Clock phase select. Controls the phase of UCLK. 0 Normal UCLK clocking scheme 1 UCLK is delayed by one half cycle Clock polarity select 0 The inactive level is low; data is output with the rising edge of UCLK; input data is latched with the falling edge of UCLK. 1 The inactive level is high; data is output with the falling edge of UCLK; input data is latched with the rising edge of UCLK. Source select. These bits select the BRCLK source clock. 00 External UCLK (valid for slave mode only) 01 ACLK (valid for master mode only) 10 SMCLK (valid for master mode only) 11 SMCLK (valid for master mode only) Unused Unused Slave transmit control. 0 4-pin SPI mode: STE enabled. 1 3-pin SPI mode: STE disabled. Transmitter empty flag. The TXEPT flag is not used in slave mode. 0 Transmission active and/or data waiting in UxTXBUF 1 UxTXBUF and TX shift register are empty
CKPL
Bit 6
SSELx
Bits 5-4
Unused Unused STC
Bit 3 Bit 2 Bit 1
TXEPT
Bit 0
68
UxRCTL, USART Receive Control Register

7 FE rw0 6 Unused rw0 5 OE rw0 4 Unused rw0 3 Unused rw0 2 Unused rw0 1 Unused rw0 0 Unused rw0
FE
Bit 7
Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. 0 No conflict detected 1 A negative edge occurred on STE, indicating bus conflict Unused Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. OE is automatically reset when UxRXBUF is read, when SW RST = 1, or can be reset by software. 0 No error 1 Overrun error occurred Unused Unused Unused Unused Unused
Undefined OE
Bit 6 Bit 5
Unused Unused Unused Unused Unused
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
69
Comparato r _A I ntrod uctio n

16.1 Comparator_A Introduction
The c omparator_A m odule s upports pr ecision sl ope analog- to-digital conversions, supply voltage supervision, and monitoring of external analog signals. Features of Comparator_A include:
- Inverting and non-inverting terminal input multiplexer -
Software selectable RC-filter for the comparator output Output provided to Tim er_A capture input
- Software control of the port input buffer - Int errupt capab ility - Selectable reference voltage generator -
Comparator and reference generator can be powered down
The Comparator_A block diagram is shown in Figure 161.
70
Comparator_A
Comparator_A Introduction
Figure 161. Comparator_A Block Diagram

VCC 0V P2CA0 0 CA0 0 1 0 CA1 0 1 P2CA1 1 Tau ~ 2.0ms Set_CAIFG 1 ++ 0 1 CAF CCI1B 0 1 CAOUT CAEX 1 0 CAON
0V 1 CAREFx 0
CARSEL 00 0 1 V CAREF 01 10 11 G D S 0.25x VCC 0.5x VCC
Comparator_A
71
Comparator_A Operation
16.2 Comparator_A Operation

The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections.
16.2.1 Comparator
The comparator compares the analog voltages at the + and - input terminals. If the + terminal is more positive than the - terminal, the comparator output CAOUT is high. The comparator can be switched on or off using control bit CAON. The comparator should be switched off when not in use to reduce current consumption. W hen the comparator is switched off, the CAOUT is always low.
16.2.2 Input Analog Switches

The analog input switches connect or disconnect the two comparator input t erminals to associated port pins u sing the P2 CAx b its. Both comparator terminal inputs can be controlled individually. The P2CAx bits allow:
- Application of an external signal to the + and - terminals of the comparator - Routing of an internal reference voltage to an associated output port pin
Internally, the input switch is constructed as a T-switch to suppress distortion in the signal path. Note: Comparator Input Connection W hen the comparator is on, the input terminals should be connected to a signal, power, or ground. Otherwise, floating levels may cause unexpected interrupts and increased current consumption. The CAEX bit controls the input multiplexer, exchanging which input signals are connected to the comparators + and - terminals. Additionally, when the comparator terminals are exchanged, the output signal from the comparator is inverted. This allows the user to determine or compensate for the comparator input offset voltage.
72
Comparator_A
Comparator_A Operation
16.2.3 Output Filter

The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small. Internal and external parasitic effects and cross coupling on and between signal lines, power supply lines, and other parts of the system are responsible for this behavior as shown in Figure 162. The comparator output oscillation reduces accuracy and resolution of the comparison result. Selecti ng t he out put filter c an reduce errors a ss ociat ed with c omparator oscillation.
Figure 162. RC-Filter Response at the Output of the Comparator
+ Terminal Terminal Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT
16.2.4 Voltage Reference Generator

The voltage reference generator is used to generate VCAREF, which can be appli ed to e ither comparator input term inal. The C AREFx b its control the output of the voltage generator. The CARSEL bit selects the com parator terminal to which VCAREF is applied. If external signals are applied to both comparator input terminals, the internal reference generator should be turned off to reduce cur rent co ns um pti on. The volt age reference generator can generate a fraction of the devices VCC or a fixed transistor threshold voltage of ~ 0.55 V.
Comparator_A
73
Comparator_A Registers
CACTL1, Comparator_A Control Register 1

7 CAEX rw(0) 6 CARSEL rw(0) 5 CAREFx rw(0) rw(0) 4 3 CAON rw(0) 2 CAIES rw(0) 1 CAIE rw(0) 0 CAIFG rw(0)
CAEX CARSEL
Bit 7 Bit 6
Comparator_A exchange. This bit exchanges the comparator inputs and inverts the comparator output. Comparator_A reference select. This bit selects which terminal the VCAREF is applied to. When CAEX = 0: is applied to the + terminal 0 VCAREF is applied to the - terminal 1 V
CARE = When CAEX F 1: 0 V is applied to the - terminal 1 VCAREF is applied to the + terminal CAREF
CAREF
Bits 5-4
Comparator_A reference. These bits select the reference voltage VCAREF. 00 Internal reference off. An external reference can be applied. 01 0.25*VCC 10 0.50*VCC 11 Diode reference is selected Comparator_A on. This bit turns on the comparator. W hen the comparator is off it consumes no current. The reference circuitry is enabled or disabled independently. 0 Off 1 On Comparator_A interrupt edge select 0 Rising edge 1 Falling edge Comparator_A interrupt enable 0 Disabled 1 Enabled The Comparator_A interrupt flag 0 No interrupt pending 1 Interrupt pending
CAON
Bit 3
CAIES
Bit 2
CAIE
Bit 1
CAIFG
Bit 0
74
Comparator_A
Comparator_A Registers
CACTL2, Comparator_A, Control Register

7 6 Unused rw(0) rw(0) rw(0) rw(0) 5 4 3 P2CA1 rw(0) 2 P2CA0 rw(0) 1 CAF rw(0) 0 CAOUT r(0)
Unused P2CA1
Bits 7-4 Bit 3
Unused. Pin to CA1. This bit selects the CA1 pin function. 0 The pin is not connected to CA1 1 The pin is connected to CA1 Pin to CA0. This bit selects the CA0 pin function. 0 The pin is not connected to CA0 1 The pin is connected to CA0 Comparator_A output filter 0 Comparator_A output is not filtered 1 Comparator_A output is filtered Comparator_A output. This bit reflects the value of the comparator output. Writing this bit has no effect.
P2CA0
Bit 2
CAF
Bit 1
CAOUT
Bit 0
CAPD, Comparator_A, Port Disable Register

7 CAPD7 rw(0) 6 CAPD6 rw(0) 5 CAPD5 rw(0) 4 CAPD4 rw(0) 3 CAPD3 rw(0) 2 CAPD2 rw(0) 1 CAPD1 rw(0) 0 CAPD0 rw(0)
CAPDx
Bits 7-0
Comparator_A port disable. These bits individually disable the input buffer for the pins of the port associated with Comparator_A. For example, if CA0 is on pin P2.3, the CAPDx bits can be used to individually enable or disable each P2.x pin buffer. CAPD0 disables P2.0, CAPD1 disables P2.1, etc. 0 The input buffer is enabled. 1 The input buffer is disabled.
Comparator_A
75
A DC12 I ntrod uction

17.1 ADC12 Introduction
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module im plem ents a 12-bit SAR core, sam ple select control, reference generator an d a 16 word conver sion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. ADC12 features include:
-
Greater than 200 ksps maximum conversion rate
- Monotonic 12-bit converter with no m issing codes - Sam ple-and-hol d wi th pr og ramma ble s ampling perio ds controlled by
software or timers.
- Conversion initiation by software, Timer_A, or Timer_B - Software selectable on-chip reference voltage generation (1.5 V or 2.5 V) -
Software selectable internal or external reference

- Eight individually configurable external input channels - Conversion channels for internal temperature sensor, AVCC, and external
references
- Independent channel-selectable reference sources for both positive and
negative references
- Sele ct able c onversion clo ck source - Single-channel, repeat-single-channel, sequence, and repeat-sequence
conversion modes
- ADC core and reference voltage can be powered down separately - Interrupt vector register for fast decoding of 18 ADC interrupts -
16 conversion-result storage registers
The block diagram of ADC12 is shown in Figure 171.
76
ADC12
ADC12 Introduction
Figure 171. ADC12 Block Diagram
REF2_5V Ve REF+ REF+ V REF / Ve REF AVCC INCHx 4 A0 A1 A2 A3 A4 A5 A6 A7 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SREF2 1 V AVSS 0 V 11 10 01 00 SREF1 SREF0 Ref_x ADC12OSC ADC12SSELx ADC12DIVx Sample and Hold S/H R R+ 00 Divider /1 .. /8 ADC12CLK BUSY SHP SHT0x 4 Sample Timer /4 .. /1024 4 SHT1x MSC SHI ISSH ENC 0 1 00 01 10 11 01 10 11 ACLK MCLK SMCLK V on 1.5 V or 2.5 V Reference
REFON INCHx=0A
AVCC
ADC12ON
12bit SAR Convert
SHSx
1 AVCC SAMPCON INCHx=0Bh Ref_x R CSTARTADDx 0
Sync
ADC12SC TA1 TB0 TB1
ADC12MEM0 16 x 12 Memory Buffer ADC12MEM15
ADC12MCTL0 16 x 8 Memory Control ADC12MCTL15
R AVSS
CONSEQx
ADC12
77
ADC12 Operation
17.2.5 Sample and Conversion Timing

An analog-to-digital conversion is initiated with a rising edge of the sample in put signal S HI. The s ource for SHI is selected with the SHSx bi ts an d includes the following:
- T he ADC1 2SC b it - The Ti mer_A Out put Unit 1 - The Ti mer_B Out put Unit 0 - The Tim er_ B Outp ut Uni t 1
The polarity of the SHI signal source can be inverted with the ISSH bit. The SAMPCON signal controls the sample period and start of conversion. W hen SAMPCON is high, sampling is active. The high-to-low SAMPCON transition starts the analog-to-digital conversion, which requires 13 ADC12CLK cycles. Two different sample-timing methods are defined by control bit SHP, extended sample mode and pulse mode.
Extended Sample Mode

The extended sample mode is selected when SHP = 0. The SHI signal directly controls SAMPCON and defines the length of the sample period tsample. When SAMPCON is high, sampling is active. The high-to-low SAMPCON transition starts the conversion after synchronization with ADC12CLK. See Figure 173.
Figure 173. Extended Sample Mode

Start Sampling Stop Sampling Start Conversion Conversion Complete
SHI
SAMPCON tsample t sync ADC12CLK
13 x ADC12CLK tconvert
ADC12
78
ADC12 Operation
Pulse Sample Mode

The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period tsample. The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample. The total sampling time is tsample plus tsync. See Figure 174. The SHTx bits select the sampling time in 4x multiples of ADC12CLK. SHT0x selects the sa mp ling time for ADC12MCTL0 to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15.
Figure 174. Pulse Sample Mode

Start Sampling Stop Sampling Start Conversion Conversion Complete
SHI
SAMPCON tsample tsync ADC12CLK
13 x ADC12CLK t convert
79
ADC12
ADC12 Registers
ADC12CTL0, ADC12 Control Register 0

15 14 SHT1x rw(0) rw(0) rw(0) rw(0) rw(0) rw(0) 13 12 11 10 SHT0x rw(0) rw(0) 9 8
7 MSC rw(0)
6 REF2_5V rw(0)
5 REFON rw(0)
4 ADC12ON rw(0)
3 ADC12OVIE rw(0)
2 ADC12 TOVIE rw(0)
1 ENC rw(0)
0 ADC12SC rw(0)
Modifiable only when ENC = 0
SHT1x SHT0x
Bits 15-12 Bits 11-8
Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15. Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7.
SHTx Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC12CLK cycles 4 8 16 32 64 96 128 192 256 384 512 768 1024 1024 1024 1024
ADC12
80
ADC12 Registers MSC
Bit 7
Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed. Reference generator voltage. REFON must also be set. 0 1.5 V 1 2.5 V Reference generator on 0 Reference off 1 Reference on ADC12 on 0 ADC12 off 1 ADC12 on ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC12 disabled 1 ADC12 enabled Start conversion. Software-controlled sample-and-conversion start. ADC12SC and ENC may be set together with one instruction. ADC12SC is reset automatically. 0 No sample-and-conversion-start 1 Start sample-and-conversion
REF2_5V
Bit 6
REFON
Bit 5
ADC12ON
Bit 4
ADC12OVIE Bit 3
ADC12 TOVIE
Bit 2
ENC
Bit 1
ADC12SC
Bit 0
81
ADC12
ADC12 Registers
ADC12CTL1, ADC12 Control Register 1

15 14 13 12 11 SHSx rw(0) rw(0) rw(0) 10 9 SHP rw(0) 8 ISSH rw(0)
CSTARTADDx rw(0) rw(0) rw(0)
6 ADC12DIVx
4 ADC12SSELx
2 CONSEQx rw(0)
0 ADC12 BUSY r(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
CSTART ADDx
Bits 15-12
Conversion start address. These bits select which ADC12 conversion-m em ory register is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15. Sample-and-hold source select 00 ADC12SC bit 01 Timer_A.OUT1 10 Timer_B.OUT0 11 Timer_B.OUT1 Sample-and-hold pulse-mode select. This bit selects the source of the sampling signal (SAMPCON) to be either the output of the sampling timer or the sample-input signal directly. 0 SAMPCON signal is sourced from the sample-input signal. 1 SAMPCON signal is sourced from the sampling timer. Invert signal sample-and-hold 0 The sample-input signal is not inverted. 1 The sample-input signal is inverted. ADC12 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8
SHSx
Bits 11-10
SHP
Bit 9
ISSH
Bit 8
ADC12DIVx
Bits 7-5
ADC12
82
ADC12 Registers ADC12 SSELx
Bits 4-3
ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC12 busy. This bit indicates an active sample or conversion operation. 0 No operation is active. 1 A sequence, sample, or conversion is active.
CONSEQx
Bits 2-1
ADC12 BUSY
Bit 0
ADC12MEMx, ADC12 Conversion Memory Registers

15 0 r0 14 0 r0 13 0 r0 12 0 r0 rw 11 10 9 8
Conversion Results rw rw rw
Conversion Results rw rw rw rw rw rw rw rw
Conversion Results
Bits 15-0
The 12-bit conversion results are right-justified. Bit 11 is the MSB. Bits 15-12 are always 0. W riting to the conversion memory registers will corrupt the results.
83
ADC12
ADC12 Registers
ADC12MCTLx, ADC12 Conversion Memory Control Registers

7 EOS rw(0) rw(0) 6 5 SREFx rw(0) rw(0) rw(0) rw(0) 4 3 2 INCHx rw(0) rw(0) 1 0
EOS
Bit 7
End of sequence. Indicates the last conversion in a sequence. 0 Not end of sequence 1 End of sequence Select reference = AV and V = AV 000 VR+ R = AV S S = V CC 001 VR+ REF+ and VR S = Ve = AV S 010 VR+ REF+ and VR = Ve = AVSS 011 VR+ REF+ and VR SS = AV and V = V / Ve 100 VR+ CC R REF R =V =V / Ve EF 101 VR+ REF+ and VR REF = Ve =V / VREF e 110 VR+ REF+ and VR REF = Ve =V / VeREF 111 VR+ REF+ and VR REF REF Input channel select 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF+ /Ve 1001 VREF REF 1010 Temperature sensor 1011 (AVCC - AVSS) / 2 1100 (AVCC - AVSS) / 2 1101 (AVCC - AVSS) / 2 1110 (AVCC - AVSS) / 2 1111 (AVCC - AVSS) / 2
SREFx
Bits 6-4
INCHx
Bits 3-0
ADC12
84
ADC12 Registers
ADC12IE, ADC12 Interrupt Enable Register

15 ADC12IE15 rw(0) 14 ADC12IE14 rw(0) 13 ADC12IE13 rw(0) 12 ADC12IE12 rw(0) 11 ADC12IE11 rw(0) 10 ADC12IE10 rw(0) 9 ADC12IE9 rw(0) 8 ADC12IE8 rw(0)
7 ADC12IE7 rw(0)
6 ADC12IE6 rw(0)
5 ADC12IE5 rw(0)
4 ADC12IE4 rw(0)
3 ADC12IE3 rw(0)
2 ADC12IE2 rw(0)
1 ADC12IE1 rw(0)
0 ADC12IE0 rw(0)
ADC12IEx
Bits 15-0
Interrupt enable. These bits enable or disable the interrupt request for the ADC12IFGx bits. 0 Interrupt disabled 1 Interrupt enabled
ADC12IFG, ADC12 Interrupt Flag Register

15 ADC12 IFG15 rw(0) 14 ADC12 IFG14 rw(0) 13 ADC12 IFG13 rw(0) 12 ADC12 IFG12 rw(0) 11 ADC12 IFG11 rw(0) 10 ADC12 IFG10 rw(0) 9 ADC12 IFG9 rw(0) 8 ADC12 IFG8 rw(0)
7 ADC12 IFG7 rw(0)
6 ADC12 IFG6 rw(0)
5 ADC12 IFG5 rw(0)
4 ADC12 IFG4 rw(0)
3 ADC12 IFG3 rw(0)
2 ADC12 IFG2 rw(0)
1 ADC12 IFG1 rw(0)
0 ADC12 IFG0 rw(0)
ADC12IFGx Bits
15-0
ADC12MEMx Interrupt flag. These bits are set when corresponding ADC12MEMx is loaded with a conversion result. The ADC12IFGx bits are reset if the corresponding ADC12MEMx is accessed, or may be reset with software. 0 No interrupt pending 1 Interrupt pending
85
ADC12
ADC12 Registers
ADC12IV, ADC12 Interrupt Vector Register

15 0 r0 14 0 r0 13 0 r0 12 0 r0 11 0 r0 10 0 r0 9 0 r0 8 0 r0
7 0 r0
6 0 r0
3 ADC12IVx
0 0
r(0)
r(0)
r(0)
r(0)
r(0)
r0
ADC12IVx
Bits 15-0
ADC12 interrupt vector value
ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h
Interrupt Source No interrupt pending ADC12MEMx overflow Conversion time overflow ADC12MEM0 interrupt flag ADC12MEM1 interrupt flag ADC12MEM2 interrupt flag ADC12MEM3 interrupt flag ADC12MEM4 interrupt flag ADC12MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEM7 interrupt flag ADC12MEM8 interrupt flag ADC12MEM9 interrupt flag ADC12MEM10 interrupt flag ADC12MEM11 interrupt flag ADC12MEM12 interrupt flag ADC12MEM13 interrupt flag ADC12MEM14 interrupt flag ADC12MEM15 interrupt flag
Interrupt Flag ADC12IFG0 ADC12IFG1 ADC12IFG2 ADC12IFG3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15
Lowest
ADC12
86
D AC12 I ntrod uction

19.1 DAC12 Introduction
The DAC 12 module is a 12-bit, voltage out put DAC. The DAC12 can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. W hen multiple DAC12 modules are present, they may be grouped together for synchronous update operation. Features of the DAC12 include:
- 12-bit mono ton ic ou tput - 8- or 12-bit voltage output resolution - Programmable settling time vs power consumption - Internal or external reference selection - Straight binar y or 2s compliment data format - Self-calibration option for offset correction - Sync hroniz ed update ca pab ility for multiple DAC12s
Note: Multiple DAC12 Modules Some devices may integrate more than one DAC12 module. In the case where more than one DAC12 is present on a device, the multiple DAC12 modules operate identically. Throughout this chapter, nomenclature appears such as DAC12_xDAT or DAC12_xCTL to describe register names. W hen this occurs, the x is used to i ndi cate whi ch D AC12 m odule is bei ng dis cuss ed. In cases w here operation is identical, the register is simply referred to as DAC12_xCTL. The blo ck dia gram of the two D AC 12 mo dules in t he MSP 430F15x/16x devices is shown in Figure 191.
87
DAC12
DAC12 Introduction
Figure 191. DAC12 Block Diagram

Ve REF+ V REF+
To ADC12 module 2.5V or 1.5V reference from ADC12 DAC12SREFx DAC12IR 00 01 10 11 AV SS /3 DAC12AMPx 3
DAC12LSELx
V R DAC12_0
V R+ x3 DAC12_0OUT
00 01 TA1 TB2 10 11
Latch Bypass 0 1 DAC12GRP 1 0 ENC DAC12RES DAC12DF
DAC12_0Latch
DAC12_0DAT
DAC12_0DAT Updated Group Load Logic
DAC12SREFx DAC12IR 00 01 10 11 AV SS /3 DAC12AMPx 3
DAC12LSELx
V R DAC12_1
V R+ x3
DAC12_1OUT
00 01 TA1 TB2 10 11
Latch Bypass 0 1 DAC12GRP 1 0 ENC DAC12RES DAC12DF
DAC12_1Latch
DAC12_1DAT
DAC12_1DAT Updated
DAC12
88
DAC12 Operation
19.2 DAC12 Operation

The DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections.
19.2.1 DAC12 Core

The DAC 12 c an be c onfi gured to operate in 8- or 12-bit mode u sing the DAC12RES bit. The full-scale output is programmable to be 1x or 3x the selected reference voltage via the DAC12IR bit. This feature allows the user to control the dynamic range of the DAC12. The DAC12DF bit allows the user to select between straight binary data and 2s compliment data for the DAC. W hen using straight binary data format, the formula for the output voltage is given in Table 191.
Table 191.DAC12 Full-Scale Range (Vref = VeREF+ or VREF+ )

Resolution DAC12RES 12 bit 12 bit 8 bit 8 bit 0 0 1 1 DAC12IR 0 1 0 1 Output Voltage Formula Vout + Vref V o u t + V r ef Vout + Vref V o u t + V r ef 3 DAC12_xDAT 4096
D A C 1 2 _ xD A T 4096 3 DAC12_xDAT 256
DAC12_ xDAT 256
In 8-bit mode the maximum useable value for DAC12_xDAT is 0FFh and in 12-bit mode the maximum useable value for DAC12_xDAT is 0FFFh. Values greater t han t hese may be wr itt en to t he reg ister, but all l eadi ng bits are ignored.
DAC12 Port Selection

The DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog inputs. W hen DAC12AMPx > 0, the DAC12 function is automatically selected for the pin, regardless of the state of the associated P6SELx and P6DIRx bits.
89
DAC12
DAC12 Registers
DAC12_xCTL, DAC12 Control Register

15 Reserved rw(0) 14 13 12 DAC12RES rw(0) 11 10 9 DAC12 CALON rw(0) 8 DAC12IR rw(0)
DAC12SREFx rw(0) rw(0)
DAC12LSELx rw(0) rw(0)
6 DAC12AMPx
4 DAC12DF
3 DAC12IE rw(0)
2 DAC12IFG rw(0)
1 DAC12ENC rw(0)
0 DAC12 GRP rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
Modifiable only when DAC12ENC = 0
Reserved DAC12 SREFx
Bit 15 Bits 14-13
Reserved DAC12 select reference voltage 00 VREF+ 01 VREF+ 10 VeREF+ 11 VeREF+ DAC12 resolution select 0 12-bit resolution 1 8-bit resolution DAC12 load select. Selects the load trigger for the DAC12 latch. DAC12ENC must be set for the DAC to update, except when DAC12LSELx = 0. 00 DAC12 latch loads when DAC12_xDAT written (DAC12ENC is ignored) 01 DAC12 latch loads when DAC12_xDAT written, or, when grouped, when all DAC12_xDAT registers in the group have been written. 10 Rising edge of Timer_A.OUT1 (TA1) 11 Rising edge of Timer_B.OUT2 (TB2) DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes. 0 Calibration is not active 1 Initiate calibration/calibration in progress DAC12 input range. This bit sets the reference input and voltage output range. 0 DAC12 full-scale output = 3x reference voltage 1 DAC12 full-scale output = 1x reference voltage
DAC12 RES DAC12 LSELx
Bit 12
Bits 11-10
DAC12 CALON
Bit 9
DAC12IR
Bit 8
DAC12
90
DAC12 Registers DAC12 AMPx
Bits 7-5
DAC12 amplifier setting. These bits select settling time vs. current consumption for the DAC12 input and output amplifiers. DAC12AMPx 000 001 010 011 100 101 110 111 Off Off Low speed/current Low speed/current Low speed/current Medium speed/current Medium speed/current High speed/current Input Buffer Output Buffer DAC12 off, output high Z DAC12 off, output 0 V Low speed/current Medium speed/current High speed/current Medium speed/current High speed/current High speed/current
DAC12DF
Bit 4
DAC12 data format 0 Straight binary 1 2s compliment DAC12 interrupt enable 0 Disabled 1 Enabled DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending DAC12 enable conversion. This bit enables the DAC12 module when DAC12LSELx > 0. when DAC12LSELx = 0, DAC12ENC is ignored. 0 DAC12 disabled 1 DAC12 enabled DAC12 group. Groups DAC12_x with the next higher DAC12_x. Not used for DAC12_1 on MSP430x15x and MSP430x16x devices. 0 Not grouped 1 Grouped
DAC12IE
Bit 3
DAC12IFG
Bit 2
DAC12 ENC
Bit 1
DAC12 GRP
Bit 0
91
DAC12
DAC12 Registers
DAC12_xDAT, DAC12 Data Register

15 0 r(0) 14 0 r(0) 13 0 r(0) 12 0 r(0) rw(0) 11 10 DAC12 Data rw(0) rw(0) rw(0) 9 8
4 DAC12 Data
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
Unused
Bits 15-12 11-0
Unused. These bits are always 0 and do not affect the DAC12 core. DAC12 data
DAC12 Data Bits
DAC12 Data Format 12-bit binary 12-bit 2s complement 8-bit binary
DAC12 Data The DAC12 data are right-justified. Bit 11 is the MSB. The DAC12 data are right-justified. Bit 11 is the MSB (sign). The DAC12 data are right-justified. Bit 7 is the MSB. Bits 11-8 are dont care and do not effect the DAC12 core. The DAC12 data are right-justified. Bit 7 is the MSB (sign). Bits 11-8 are dont care and do not effect the DAC12 core.
8-bit 2s complement
DAC12
92
Interrupt V e ct or Addre s s e s
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh - 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE Power-up External Reset Watchdog Flash memory NMI Oscillator Fault Flash memory access violation Timer_B7 (see Note 5) Timer_B7 (see Note 5) Comparator_A Watchdog timer USART0 receive USART0 transmit ADC Timer_A3 Timer_A3 INTERRUPT FLAG WDTIFG KEYV (see Note 1) NMIIFG (see Notes 1 & 4) OFIFG (see Notes 1 & 4) ACCVIFG (see Notes 1 & 4) BCCIFG0 (see Note 2) BCCIFG1 to BCCIFG6 TBIFG (see Notes 1 & 2) CAIFG WDTIFG URXIFG0 UTXIFG0 ADCIFG (see Notes 1 & 2) CCIFG0 (see Note 2) CCIFG1, CCIFG2, TAIFG (see Notes 1 & 2) P1IFG.0 (see Notes 1 & 2) To P1IFG.7 (see Notes 1 & 2) URXIFG1 UTXIFG1 P2IFG.0 (see Notes 1 & 2) To P2IFG.7 (see Notes 1 & 2) Maskable SYSTEM INTERRUPT Reset WORD ADDRESS 0FFFEh PRIORITY 15, highest
(Non)maskable (Non)maskable (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh
14 13 12 11 10 9 8 7 6 5
I/O port P1 (eight flags) USART1 receive USART1 transmit I/O port P2 (eight flags)
Maskable Maskable
0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0,
4 3 2 1 lowest
NOTES: 1. 2. 3. 4.
Multiple source flags Interrupt flags are located in the module. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. 5. Timer_B7 in MSP430x14x family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs; in Timer_B3 there are only interrupt flags CCIFG0, 1, and 2, and the interrupt-enable bits CCIE0, 1, and 2 integrated.
special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
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IE 1
Address 0h
7 UTXIE0 rw-0 rw-0
6 URXIE0 rw-0
5 ACCVIE rw-0
4 NMIIE
2 rw-0
1 OFIE rw-0
0 WDTIE
WDTIE: OFIE: NMIIE: ACCVIE: URXIE0: UTXIE0:

Address 01h 7
Watchdog-timer-interrupt enable signal Oscillator-fault-interrupt enable signal Nonmaskable-interrupt enable signal (Non)maskable-interrupt enable signal, access violation if FLASH memory/module is busy USART0, UART, and SPI receive-interrupt enable signal USART0, UART, and SPI transmit-interrupt enable signal
6 rw-0 5 UTXIE1 rw-0 4 URXIE1 3 2 1 0
IE2
URXIE1: UTXIE1:
USART1, UART, and SPI receive-interrupt enable signal USART1, UART, and SPI transmit-interrupt enable signal
I FG 1
Address 02h rw-1
7 UTXIFG0 rw-0
6 URXIFG0
5 rw-0
4 NMIIFG
2 rw-1
1 OFIFG rw-0
0 WDTIFG
W DTIFG: OFIFG: NMIIFG: URXIFG0: UTXIFG0:

Address 03h 7
Set on overflow or security key violation or reset on VCC power-on or reset condition at RST/NMI Flag set on oscillator fault Set via RST/NMI pin USART0, UART, and SPI receive flag USART0, UART, and SPI transmit flag
6 rw-1 5 UTXIFG1 rw-0 4 URXIFG1 3 2 1 0
IFG2
URXIFG1: UTXIFG1:
USART1, UART, and SPI receive flag USART1, UART, and SPI transmit flag
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94
ME 1
Address 04h
7 UTXE0 rw-0
6 URXE0 USPIE0 rw-0
URXE0: UTXE0: USPIE0:
USART0, UART receive enable USART0, UART transmit enable USART0, SPI (synchronous peripheral interface) transmit and receive enable
7 6 5 UTXE1 rw-0 4 URXE1 USPIE1 rw-0 3 2 1 0
M E2
Address 05h
URXE1: UTXE1: USPIE1:

Legend: rw: rw-0:
USART1, UART receive enable USART1, UART transmit enable USART1, SPI (synchronous peripheral interface) transmit and receive enable
Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device
memory organization
MSP430F133 Memory Main: interrupt vector Main: code memory Information memory Boot memory RAM Peripherals Size Flash Flash Size Flash Size ROM Size 16-bit 8-bit 8-bit SFR 8kB 0FFFFh - 0FFE0h 0FFFFh - 0E000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 256 Byte 02FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F135 16kB 0FFFFh - 0FFE0h 0FFFFh - 0C000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 512 Byte 03FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F147 32kB 0FFFFh - 0FFE0h 0FFFFh - 08000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 1kB 05FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F148 48kB 0FFFFh - 0FFE0h 0FFFFh - 04000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 2kB 09FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F149 60kB 0FFFFh - 0FFE0h 0FFFFh - 01100h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 2kB 09FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h
boot ROM containing bootstrap loader

The intention of the bootstrap loader is to download data into the flash memory module. Various write, read, and erase operations are needed for a proper download environment. The bootstrap loader is only available on F devices. functions of the bootstrap loader: Definition of read: write: unprotected functions Mass erase, erase of the main memory (segment 0 to segment n) and information memory (segment A and segment B) Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key. Apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX) Read data from pin P2.2 (BSLRX) and write them into flash memory
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Ti m er_A (th ree capture/compare regist e rs)

The timer module offers one sixteen-bit counter and three capture/compare registers. The timer clock source can be selected from two external sources P1.0/TACLK (SSEL=0) or P2.1/TAINCLK (SSEL=3), or from two internal sourcesACLK (SSEL=1) or SMCLK (SSEL=2). The clock source can be divided by one, two, four, or eight. The timer can be fully controlled (in word mode)it can be halted, read, and written; it can be stopped, run continuously, or made to count up or up/down using one compare block to determine the period. The three capture/compare blocks are configured by the application to run in capture or compare mode. The capture mode is mostly used to individually measure internal or external events from any combination of positive, negative, or positive and negative edges. It can also be stopped by software. Three different external events can be selected: TA0, TA1, and TA2. In the capture/compare register CCR2, ACLK is the capture signal if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3. The compare mode is mostly used to generate timing for the software or application hardware, or to generate pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An individual output module is assigned to each of the three capture/compare registers. This module can run independently of the compare function or can be triggered in several ways.
P1.0/TACLK SSEL1 SSEL0 0 TACLK 1 ACLK 2 SMCLK 3 INCLK 32kHz to 8MHz Timer Clock 15 Input Divider ID1 ID0 CCIS01 CCIS00 Clk RC POR/CLR Timer Bus Capture Mode CCI0 CCM01 CCM00 CCIS11CCIS10 0 CCI1A 1 CCI1B GND VCC 2 3 Comparator 0 Capture Carry/Zero 16-bit Timer Data 0 Mode Control Equ0 Set_TAIFG 16-bit Timer
P2.1/TAINCLK
MC1 MC0 0
P2.2/CAOUT/TA0
P1.1/TA0
CCI0A CCI0B GND VCC
0 1 2 3
15 a ure/Compare C ptture/Compare Register CCR0
OM02OM01OM00 Out0 Output Unit0 EQU0 P1.1/TA0 P1.5/TA0 P2.7/TA0
Capture/Compare Reg. CCR1 15 Capture Mode CCI1 CCM11 CCM10 Capture Capture/Compare Register CCR1 0 OM12OM11 OM10 P1.2/TA1 Output Unit1 Comparator 1 EQU1 Out1 P1.6/TA1 P2.3/CA0/TA1 ADC12I1 (i/p at ADC12)
P1.2/TA1 CAOUT from Comparator_A
CCIS21CCIS20 P1.3/TA2 ACLK CCI2A CCI2B GND VCC 0 1 2 3 Capture Mode CCI2 CCM21 CCM20 Capture 15 0 a C om pa e C ptture/Comparre Register CCR2 Comparator 2 Output Unit2 EQU2 OM22OM21OM20 Out2
P1.3/TA2 P1.7/TA2 P2.4/CA1/TA2
Figure 2. Timer_A, MSP430x13x/14x Configuration Two interrupt vectors are used by the module. One vector is assigned to capture/compare block CCR0, and one common-interrupt vector is implemented for the timer and the other two capture/compare blocks. The three interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector word is used to add an offset to the program counter so that the interrupt handler software continues at the corresponding program location. This simplifies the interrupt handler and assigns each interrupt event the same five-cycle overhead.
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96
D S 1 307 64 x 8 S eri al R eal-T i me Clo ck

www.maxim-ic.com
FEATURES
Real-time clock (RTC) counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap-year compensation valid up to 2100 56-byte, battery-backed, nonvolatile (NV) RAM for data storage Two-wire serial interface Programmable squarewave output signal Automatic power-fail detect and switch circuitry Consumes less than 500nA in battery backup mode with oscillator running Optional industrial temperature range: -40C to +85C Available in 8-pin DIP or SOIC Underwriters Laboratory (UL) recognized
PIN ASSIGNMENT
X1 X2 VBAT GND l 2 3 4 8 7 6 5 VCC SQW/OUT SCL SDA
DS1307 8-Pin DIP (300-mil)

X1 X2 VBAT GND l 2 3 4 8 7 6 5 VCC SQW/OUT SCL SDA
DS1307 8-Pin SOIC (150-mil)
ORDERING INFORMATION
DS1307 DS1307Z DS1307N DS1307ZN
8-Pin DIP (300-mil) 8-Pin SOIC (150-mil) 8-Pin DIP (Industrial) 8-Pin SOIC (Industrial)
VCC X1, X2 VBAT GND SDA SCL SQW/OUT
PIN DESCRIPTION
- Primary Power Supply - 32.768kHz Crystal Connection - +3V Battery Input - Ground - Serial Data - Serial Clock - Square Wave/Output Driver
DESCRIPTION
The DS1307 Serial Real-Time Clock is a low-power, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially via a 2-wire, bi-directional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1307 has a built-in power sense circuit that detects power failures and automatically switches to the battery supply.
97
DS1307 TIMEKEEPER REGISTERS Figure 3
DS1307
0 0 0 0 0 0 0 0 0 0 0 0
CONTROL REGISTER
BIT 7 OUT BIT 6 0
The DS1307 control register is used to control the operation of the SQW/OUT pin. BIT 5 0 BIT 4 SQWE BIT 3 0 BIT 2 0 BIT 1 RS1 BIT 0 RS0
OUT (Output control): This bit controls the output level of the SQW/OUT pin when the square wave output is di sabled. If SQWE = 0, the logic level on the SQW/OU T pin is 1 if OU T = 1 and is 0 if OUT = 0. SQWE (Square Wave Enable): This bit, when set to a logic 1, will enable the oscillator output. The frequency of the square wave output depends upon the value of the RS0 and RS1 bits. With the square wave output set to 1Hz, the clock registers update on the falling edge of the square wave. RS (Rate Select): These bits control the frequency of the square wave output when the square wave output has been enabled. Table 1 lists the square wave frequencies that can be selected with the RS bits.
SQUAREWAVE OUTPUT FREQUENCY Table 1

RS1 0 0 1 1 RS0 0 1 0 1
SQW OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz
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Philips Semiconductors
The I C-bus specification

Since control of the I C-bus is decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus. Special attention must be paid if, during a serial transfer, the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is 2 transmitted to the I C-bus. If its possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration isnt allowed between: A repeated START condition and a data bit A STOP condition and a data bit A repeated START condition and a STOP condition.
2
then hold the SCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure (see Fig.6). On the bit level, a device such as a microcontroller with or 2 without limited hardware for the I C-bus, can slow down the bus clock by extending each clock LOW period. The speed of any master is thereby adapted to the internal operating rate of this device. In Hs-mode, this handshake feature can only be used on byte level (see Section 13). 9 FORMATS WITH 7-BIT ADDRESSES
Data transfers follow the format shown in Fig.10. After the START condition (S), a slave address is sent. This Slaves are not involved in the arbitration procedure. address is 7 bits long followed by an eighth bit which is a data direction bit (R/W ) - a zero indicates a transmission 8.3 Use of the clock synchronizing mechanism as (W RITE), a one indicates a request for data (READ). A a handshake data transfer is always terminated by a STOP condition (P) In addition to being used during the arbitration procedure, generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated the clock synchronization mechanism can be used to enable receivers to cope with fast data transfers, on either a START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of byte level or a bit level. read/write formats are then possible within such a transfer. On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can
handbook, full pagewidth
SDA
SCL S START condition
1-7
1-7
1-7
9 P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP condition
MBC604
Fig.10 A complete data transfer.
99
Philips Semiconductors
The I C-bus specification

Possible data transfer formats are: Master-transmitter transmits to slave-receiver. The transfer direction is not changed (see Fig.11). Master reads slave immediately after first byte (see Fig.12). At the moment of the first acknowledge, the master- transmitter becomes a master- receiver and the slave-receiver becomes a slave-transmitter. This first acknowledge is still generated by the slave. The STOP condition is generated by the master, which has previously sent a not-acknowledge (A). Combined format (see Fig.13). During a change of direction within a transfer, the START condition and the slave address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previously sent a not-acknowledge (A). NOTES: 1. Combined formats can be used, for example, to control a serial memory. During the first data byte, the internal memory location has to be written. After the START condition and slave address is repeated, data can be transferred. 2. All decisions on auto-increment or decrement of previously accessed memory locations etc. are taken by the designer of the device. 3. Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in the sequence. 4. I C-bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address, even if these START conditions are not positioned according to the proper format. 5. A START condition immediately followed by a STOP condition (void message) is an illegal format.
2
SLAVE ADDRESS
R/W
DATA
DATA
A/A
'0' (write) from master to slave from slave to master

MBC605
data transferred (n bytes + acknowledge)
A = acknowledge (SDA LOW ) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition
Fig.11 A master-transmitter addressing a slave receiver with a 7-bit address. The transfer direction is not changed.
1 S SLAVE ADDRESS R/W A DATA A DATA A P
data transferred
MBC606
(read)
(n bytes + acknowledge)
Fig.12 A master reads a slave immediately after the first byte.
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M S P 43 x 13x MS 4 30 x 4 x 0 , P 1 M I X E D S I G N A L M I C R O C O N T R OL E R L
SLAS272C - JULY 2000 - REVISED FEBRUARY 2001
pin designation, MSP430F147, MSP430F148, MSP430F149

PM PACKAGE (TOP VIEW)
DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 VREF+ XIN XOUT/TCLK VeREF+ VREF-/VeREFP1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK
1 2 3 4 5 6 7 8 9
64 63 6261 6059 58 57
56 55 54 5352 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
10 11 12 13 14 15
16 33 1718 19 20 21 22 2 3 24 25 26 2728 29 3031 32
P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0
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101

Msp430 Training Manual

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Msp430 Training Manual

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M SP430x 1xx Fami ly

M S P 430 Archit ecture

0.8-A real-time clock mode J

250-A / MIPS active

Supply voltage supervisor

Optimized for modern high-level programming

Extensive vectored-interrupt capability

upgrades and data logging

1.2 Flexible Clock System

Low-frequency auxiliary clock = Ultralow-power stand-by mode

- High-speed master clock = High performance signal processing

Figure 11. MSP430 Architecture

RISC CPU 16-Bit

1.3 Embedded Emulation

breakpoints, and single-steps in an application are supported.

- Development is in-system subject to the same characteristics as the final

- Mixed-signal integrity is preserved and not subject to cabling interference.

1.4 Address Space

Figure 12. Memory Map

Word Byte Byte

The MSP430 typical current consumption is shown in Figure 29.

315 270 225 180 135 90 45 0

LPM2 LPM3 Operating Modes

System Resets, Interrupts, and Operating Modes

Figure 210. MSP430x1xx Operating Modes For Basic Clock System

RST/NMI Reset Active

WDT Time Expired, Overflow

WDT Active, Security Key Violation

Active Mode CPU Is Active Peripheral Modules Are Active

CPUOFF = 1 SCG0 = 0 SCG1 = 1

CPUOFF = 1 SCG0 = 1 SCG1 = 1

SCG0 OSCOFF CPUOFF 0 0 1 0 0 0 0 1 1

Mode Active LPM0 LPM1

System Resets, Interrupts, and Operating Modes

3.1 CPU Introduction

reduces code size.

- Direct memory-to-memory transfers without intermediate register holding. -

RISC 16-Bit CPU

Figure 31. CPU Block Diagram

RISC 16-Bit CPU

Status Register (SR)

Figure 36. Status Register Bits

Table 31 describes the status register bits.

Table 31.Description of Status Register Bits

SCG1 SCG0 OSCOFF CPUOFF GIE N

RISC 16-Bit CPU

Table 33.Source/Destination Operand Addressing Modes

Indirect register mode Indirect autoincrement

RISC 16-Bit CPU

Table 34.Register Mode Description

Length: Operation: Comment: Example:

RISC 16-Bit CPU

Table 35.Indexed Mode Description

0FF16h 0FF14h 0FF12h

0FF16h 0FF14h 0FF12h

04596h PC 0108Ch +0006h 01092h

01094h 01092h 01090h

0xxxxh 05555h 0xxxxh

01094h 01092h 01090h

0xxxxh 01234h 0xxxxh

01084h 01082h 01080h

0xxxxh 01234h 0xxxxh

01080h +0002h 01082h