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Subject: COMPUTER ARCHITECTURE AND ORGANIZATION Subject code: CSE-210 F

INDEX
S. No. 1 2 3 4 5 6 7 8 9 10 11 Contents Improvement in Lesson Plans Syllabus as per M.D. University Teaching Methodology Teaching Plan Links for Online study material (General: For all subjects) Links for Online study material (Subject specific) Seminar details Assignment details Assignments Student feedback form Monthly report form

MERI - CET DEPTT. OF COMPUTERR SCIENCE /INFORMATION TECHNOLOGY Improvement in Lesson plan 1. Links for online study material for all important subjects have been added. 2. Links for respective subjects have also been included. 3. After completion of each unit , not only the assignments will be given tests will also be taken. 4. Questions related to each unit will be discussed on completion of the unit. 5. Improvement and vast topics will be covered using LCD projectors. 6. Revision lecture for each unit has been planned for the session 2011-2012. 7. Indiscipline will be handled more strictly. 8. Timely submission of assignments will be given more weightage. 9. Lectures have been planned more interactive. 10. Questions from latest question papers have been added.

MERI - CET DEPTT. OF COMPUTER SCIENCE

TEACHING METHODLOGY
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION Branch: ECE Subject Code: CSE-210 F Semester: V

Lecturer: Ms. Sonia


COURSE OBJECTIVE

Course

To provide knowledge of General system architecture and instruction set architecture. and to give introduction about memory hierarchy and parallelism. METHODOLOGY The pedagogy will be lectures, tutorials, assignments, interactive class work, seminars, project etc. ACHIEVEMENTS 1. Basic knowledge of Instruction set. 2. Properties of regular sets. 3. Ability to understand the computer organization EVALUATION Besides the semester end examination,the stuents will be continuously assessed during the course on following basis S. no. 1 2 3 4 Description Mid term examinations Internal assessment (Assignment + Attendance) Class performance End semester examination Total Marks distribution 20 20 10 100 150

Syllabus as per M. D. University Session: 2011-2012


B.TECH (CSE) - SEMESTER V SUBJECT: COMPUTER ARCHITECTURE AND ORGANIZATION SUBJECT CODE: CSE-210 F

Section A: Boolean algebra and Logic gates, Combinational logic blocks(Adders, Multiplexers, Encoders, de-coder), Sequential logic blocks(Latches, Flip-Flops, Registers, Counters) Store program control concept, Flynns classification of computers (SISD, MISD, MIMD); Multilevel viewpoint of a machine: digital logic, micro architecture, ISA, operating systems, high level language; structured organization; CPU, caches, main memory, secondary memory units & I/O; Performance metrics; MIPS, MFLOPS. Section B: Instruction Set Architecture: Instruction set based classification of processors (RISC, CISC, and their comparison); addressing modes: register, immediate, direct, indirect, indexed; Operations in the instruction set; Arithmetic and Logical, Data Transfer, Control Flow; Instruction set formats (fixed, variable, hybrid); Language of the machine: 8086 ; simulation using MSAM. Section C: Basic non pipelined CPU Architecture and Memory Hierarchy & I/O Techniques CPU Architecture types (accumulator, register, stack, memory/ register) detailed data path of a typical register based CPU, Fetch-Decode-Execute cycle (typically 3 to 5 stage); microinstruction sequencing, implementation of control unit, Enhancing performance with pipelining. The need for a memory hierarchy (Locality of reference principle, Memory hierarchy in practice: Cache, main memory and secondary memory, Memory parameters: access/ cycle time, cost per bit); Main memory (Semiconductor RAM & ROM organization, memory expansion, Static & dynamic memory types); Cache memory (Associative & direct mapped cache organizations. Section D: Introduction to Parallelism and Computer Organization [80x86]: Goals of parallelism (Exploitation of concurrency, throughput enhancement); Amdahls law; Instruction level parallelism (pipelining, super scaling basic features); Processor level parallelism (Multiprocessor systems overview). Instruction codes, computer register, computer instructions, timing and control, instruction cycle, type of instructions, memory reference, register reference. I/O reference, Basics of

Logic Design, accumulator logic, Control memory, address sequencing, microinstruction formats, micro-program sequencer, Stack Organization, Instruction Formats, Types of interrupts; Memory Hierarchy. Text Books: Computer Organization and Design, 2 Ed., by David A. Patterson and John L. Hennessy, Morgan 1997, Kauffmann. Computer Architecture and Organization, 3 Edi, by John P. Hayes, 1998, TMH. Reference Books: Operating Systems Internals and Design Principles by William Stallings,4th edition, 2001, Prentice-Hall Upper Saddle River, New Jersey Computer Organization, 5th Edi, by Carl Hamacher, Zvonko Vranesic,2002, Safwat Zaky. Structured Computer Organisation by A.S. Tanenbaum, 4th edition, PrenticeHall of India, 1999, Eastern Economic Edition. Computer Organisation & Architecture: Designing for performance by W. Stallings, 4 edition, 1996, Prentice-Hall International edition. Computer System Architecture by M. Mano, 2001, Prentice-Hall. Computer Architecture- Nicholas Carter, 2002, T.M.H. NOTE: Examiner will set 9 questions in total, with two questions from each section and one question covering all sections which will be Q.1. This Q.1 is compulsory and of short answers type. Each question carries equal mark (20 marks). Students have to attempt 5 questions in total at least one question from each section.

TEACHING PLAN
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION Branch: ECE Subject Code: CSE-210 F Semester: V Total No. of Lectures: 50 Detailed Course Outline References No.Of Lectures 13

Unit1: Basic Principles and General System Architecture: Boolean algebra and Logic gates, Combinational logic blocks(Adders, Multiplexers, Encoders, decoder), Sequential logic blocks(Latches, FlipFlops, Registers, Counters) Store program control concept, Flynn s classification of computers (SISD, MISD, MIMD); Multilevel viewpoint of a machine: digital logic, micro architecture, ISA, operating systems, high level language; structured organization; CPU, caches, main memory, secondary memory units & I/O; Performance metrics; MIPS, MFLOPS. Unit-2: Instruction Set Architecture: Instruction set based classification of processors (RISC, CISC, and their comparison); addressing modes: register, immediate, direct, indirect, indexed; Operations in the instruction set; Arithmetic and Logical, Data Transfer, Control Flow; Instruction set formats (fixed, variable, hybrid); Language of the machine: 8086 ; simulation using MSAM. CPU Architecture types (accumulator, register, stack, memory/ register) detailed data path of a typical register based CPU, Fetch-Decode-Execute cycle (typically 3 to 5 stage); microinstruction sequencing, implementation of control unit, Enhancing performance with pipelining. Unit-3: Memory Hierarchy & I/O Techniques: The need for a memory hierarchy (Locality of reference principle, Memory hierarchy in practice: Cache, main memory and

M Morris Mano Chapter 2, 9, 12 Andrew S.Tanenbaum Chapter 3, 8

William Stallings

15 M Morris Mano Chapter 5 David A. Patterson Chapter 5

M Morris Mano Chapter 12

secondary memory, Memory parameters: access/ cycle time, cost per bit); Main memory (Semiconductor RAM & ROM organization, memory expansion, Static & dynamic memory types); Cache memory (Associative & direct mapped cache organizations. Unit-4: Introduction to Parallelism[80X86]: Goals of parallelism (Exploitation of concurrency, throughput enhancement); Amdahl s law; Instruction level parallelism (pipelining, super scaling basic features); Processor level parallelism (Multiprocessor systems overview). Unit5: Computer Organization [80x86]: Instruction codes, computer register, computer instructions, timing and control, instruction cycle, type of instructions, memory reference, register reference. I/O reference, Basics of Logic Design, accumulator logic, Control memory, address sequencing, micro-instruction formats, micro-program sequencer, Stack Organization, Instruction Formats, Types of interrupts; Memory Hierarchy. Total No. of Lectures

David A. Patterson Chapter 5

M Morris Mano Chapter 9 David A. Patterson Chapter 2, 3

M Morris Mano Chapter 7, 11 Andrew S.Tanenbaum Appendix C Internet

50

Text Books:
Computer System Architecture by M. Mano, 2001, Prentice-Hall. Computer Architecture- Nicholas Carter, 2002, T.M.H. Computer Organization and Design, 2nd Ed., by David A. Patterson and John L. Hennessy, Morgan 1997, Kauffmann. Structured Computer Organisation by A.S. Tanenbaum, 4th edition, Prentice-Hall of India, 1999, Eastern Economic Edition.

Reference Books:
Operating Systems Internals and Design Principles by William Stallings,4th edition, 2001, Prentice-Hall Upper Saddle River, New Jersey Advanced Computer Architectures by Terence Fountain, Pearson Education Computer Architecture and Organization by Hayes, McGraw Hill

SEMINAR DETAILS
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

S. No. 1 2 3 4 5 6 7

Topic

Group [Rollno wise]

Proposed Date

Combinational and Sequential 1-6 logic blocks

Aug 27, 11 Sep 03, 11 Sep 10, 11 Sep 17, 11 Sep 24, 11 Oct 1, 11 Oct 8, 11

Multilevel viewpoint of a machine

7-12

Instruction set architecture 13-18 Memory hierarchy and I/O techniques Parallelism Microprogrammed control memory 8086 Computer Organization
19-24 25-30 31-36 37-upto last rollno.

ASSIGNMENT DETAILS
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

S. No. 1 2 3 4 5 6

Assignment

Assignment giving dates

Assignment Collection date

Assignment check/discussio n date

Assignment 1 Assignment 2 Assignment 3 Assignment 4 Assignment 5 Assignment 6

Aug 09, 11 Aug 23, 11 Sep 06, 11 Sep 20, 11 Oct 04, 11 Oct 18, 11

Aug 16, 11 Aug 30, 11 Sep 13, 11 Sep 27, 11 Oct 11, 11 Oct 25, 11

Aug 23, 11 Sep 06, 11 Sep 20, 11 Oct 04, 11 Oct 18, 11 Nov 01, 11

MERI - CET DEPTT. OF COMPUTER SCIENCE

ASSIGNMENT 1
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

Submitted to: Ms. Sonia


Assignment giving date Assignment Collection date Assignment check/discussion date

Aug 09, 11

Aug 16, 11

Aug 23, 11

Q 1- Describe the various fundamental components of digital computer. Q 2- What is the difference between a sequential circuit and a combinational circuit? Discuss logic gates with their truth tables. Q 3- Explain the following terms: Memory Register Program Counter on program status Words. Latch Q 4- Describe Von Neumann Model for computers and stored program concept. Q 5- Make block diagram of control unit and explain various computer cycles. Q 6- Explain and design Johnson counter. Q 7- Draw and discuss a 4-bit binary incremented. Q 8- Represent +82 in 8 bit register using: a. Signed magnitude representation b. 1s complement representation c. 2s complement representation Q 9- Differentiate between write back and write through cache. In what particular scenarios, which one is better? Q 10- Show that an over flow occurs when -74 is added to -86 using 8 bit register using signed 2s complement notation.

MERI - CET DEPTT. OF COMPUTER SCIENCE

ASSIGNMENT 2
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

Submitted to: Ms. Sonia


Assignment giving date Assignment Collection date Assignment check/discussion date

Aug 23, 11
Q Q Q Q 1234-

Aug 30, 11

Sep 06, 11

Q Q Q Q Q Q

Design a 4 bit combinational circuit for binary adder and sub tractor. Explain MACRO & SUB ROUTINE with the help of example. Define interrupt. Explain the various types of interrupt. Explain the following Memory with suitable diagrams: RAM ROM Cache Memory 5- Explain the difference between normal subprogram and macro. Can parameter be passed to a macro? If yes, how? 6- Draw and explain the detailed data path for a register based CPU and stack based CPU. 7- Draw and Explain Flowchart for interrupt cycle and write down the Register transfer statements for interrupt cycle. 8- Explain given terms in detail with diagrams: Associate Memory with their merits and demerits. EPROM with their merits and demerits. 9- Explain interleaved memory system in detail. 10- Give memory hierarchy. Also, explain direct mapping scheme for cache memory.

MERI - CET DEPTT. OF COMPUTER SCIENCE

ASSIGNMENT - 3
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

Submitted to: Ms. Sonia


Assignment giving date Assignment Collection date Assignment check/discussion date

Sep 06, 11
Q1

Sep 13, 11

Sep 20, 11

Describe the term addressing modes. Explain various addressing modes as available in instruction set of microprocessor. Q 2- Describe relative merits and demerits of hardwired control unit and microprogrammed control unit. Q 3- Explain the following Multiport memory Cross bar switch Q4- Define the following in your own words Control memory Control word Microinstruction Q 5- Differentiate between write back cache and write through cache. Q 6- Explain the given terms in detail: Microprogram Micro-operation Macro-operation Q 7- What is virtual memory? What are its advantages? The logical address space in computer system consisting of 128 segments. Each segment can have upto 32 pages of 4 K words each. Physical memory consists of 4096 blocks of 4096 words in each. Formulate the logical and physical address format. Q 8- Construct 4096X8 bits RAM using 512X8 bits. Show address and data line connection and chip enable lines and multiplexing arrangement. Q 9- Why does DMA has priority over CPU when both request a memory transfer?

Q 10- What is meant by locality of reference? Describe various mapping procedures considering the organization of cache memory.

MERI - CET DEPTT. OF COMPUTER SCIENCE

ASSIGNMENT - 4
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

Submitted to: Ms. Sonia


Assignment giving date Assignment Collection date Assignment check/discussion date

Sep 20, 11
Q 1-

Sep 27, 11

Oct 04, 11

(a) Explain the concept of memory hierarchy. (b) Explain the working of associative memory (c) Describe the concept of memory interleaving.

Q 2- With the help of block diagram explain the daisy chain priority interrupt. Q 3Q 4What is the difference between I/O program control transfer and DMA transfer. Explain DMA in detail. Write a program to evaluate the arithmetic statement: X = (A+B*C)/ (D-E*F) a. Using general register type CPU with three address instruction. b. Using accumulator type computer with one address instruction. c. Stack organized CPU with zero address operation instruction. Make a block diagram of bit sliced CPU.

Q 5-

Q 6- What are the various parameters that can be used to evaluate the performance of a memory unit. Q 7Q 8What do you mean by structured organization. Explain the given terms in detail: Hardwired control Microprogrammed control

Q 9- Differentiate between logical address and physical address. What do you understand by the term page fault. Give example for the same. Q 10- A virtual memory system has an address space of 8K words, a memory space of 4K words and a page and block size of 1K words. The following page reference changes occur during a given time interval: 5 4 2 0 1 2 6 1 4 0 1 0 7 Determine the four pages which will be resident in main memory at the end if policy used is (i) FIFO (ii) LIFO

MERI - CET DEPTT. OF COMPUTER SCIENCE

ASSIGNMENT - 5
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

Submitted to: Ms. Sonia


Assignment giving date Assignment Collection date Assignment check/discussion date

Oct 04, 11
Q 1-

Oct 11, 11

Oct 18, 11

Write short notes on the following: Direct mapping Memory management hardware Microprogram Shifter Input/Output processor. Explain the concept of associative memory. What is its hardware organization. What is meant by locality of reference? Describe various mapping procedures considering the organization of cache memory. Describe the instruction formats of a basic computer in detail. Discuss RISC instructions. Describe various phases of instruction cycle in detail. What is an effective address? Discuss some of the memory reference instructions in brief. State and explain the Amdahls law. How the throughput of a system can be enhanced with parallel mechanism?

Q 2Q 3Q 4Q 5-

Q 6Q 7-

Q 8Q 9-

What are the various types of instructions supported by the 8086 family. discuss each briefly. Explain the algorithm in flow chart for addition and subtraction of signed-magnitude numbers.

Q 10- A virtual memory has page size of 1K words. There are 8 pages and four blocks. The associative memory page table contain following entries: Page Blocks 0 3 1 1 4 2 6 0 Make a list of all virtual address that will cause a page fault.

MERI - CET DEPTT. OF COMPUTER SCIENCE

ASSIGNMENT - 6
Subject: COMPUTER ARCHITECTURE AND ORGANIZATION ECE Subject Code: CSE-210 F Semester: V Branch:

Submitted to: Ms. Sonia


Assignment giving date Assignment Collection date Assignment check/discussion date

Oct 18, 11

Oct 25, 11

Nov 01 11

1. What is the difference between computer organization and computer architecture? 2. What are the various types of ISAs possible? Discuss 3. Give the organization of typical hardwired control unit and explain the functions performed by the various blocks. 4. Explain the instruction cycle highlighting the sub-cycles and sequence of steps to be followed. 5. Consider a processor is having single bus organization of the datapath inside a processor. Write the sequence of control steps required for each of the following instructions: a) Add the (immediate) number NUM to register R1 b) Add the contents of memory location NUM to register R1 c) Add the contents of the memory location whose address is at memory location 6. Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to overcome/minimize these hazards?

7. The five stages of the simple MIPS pipeline are: instruction fetch,
instruction decode and register read, execute or calculate address, memory access, and register write. Describe the purpose of each of these stages.

8. Explain arithmetic pipeline in detail. 9. Explain the concept of overlapped register windows in RISC in detail 10. Explain the concept of address sequencing in microprogrammed
control.

MERI - CET DEPTT. OF COMPUTER SCIENCE

Links for Online study material (General: For all subjects)

http://en.wikipedia.org/wiki/Computer_science

www.sciencedaily.com/news/computers_math/computer_science

http://www.springer.com/series/7592
www.smartertechnology.com www.crazyengineers.com/...topics/1115-seminar-topics-computer www.cs.cmu.edu www.cs.stanford.edu www.cs.princeton.edu/academics/ugradpgm/topics.php katemarieldizon.blogspot.com/.../current-state-of-cs-research-topics www.cs.colorado.edu/courses/csci7000.html

MERI - CET DEPTT. OF COMPUTER SCIENCE


Subject: COMPUTER ARCHITECTURE AND ORGANIZATION

Links for Online study material (Subject specific)

ece.eng.wayne.edu/~gchen/ece4680/lecture-notes/lecture-notes.html

http://engineeringppt.blogspot.com/20010/11/computerarchitecture-and-organization.html
www.gogetpapers.com/Lectures/Brief_architecture - United States freecomputerbooks.com/compscArchitectureBooks.html www.techvyom.com/.../free-gate-study-material-and-ebooks-for.htm http://be-organic.info/organic-architecture/notes-on-computer-architecture-andorganization http://www.techinterviews.com/hardware-architecture-interview-questions www.scs.ryerson.ca/mfiala/courses/cps310.../murdocca_Ch01CAO.pdf www.youtube.com/watch?v=4TzMyXmzL8M http://freescienceonline.blogspot.com/2006/06/free-computer-science-videolecture_24.html 1