VHDL Lecture Notes - Navabi

Chapter 1
Hardware design environments
1.1 DIGITAL SYSTEM DESIGN PROCESS 1.1.1 Design Automation 1.2 The Art of Modeling 1.3 HARDWARE DESCRIPTION LANGUAGES 1.3.1 A Language for Behavioral Descriptions 1.3.2 A Language for Describing Flow of Data 1.3.3 A Language for Describing Netlists 1.4 HARDWARE SIMULATION 1.4.1 Oblivious Simulation 1.4.2 Event Driven Simulation 1.5 HARDWARE SYNTHESIS TEST APPLICATIONS 1.6 LEVELS OF ABSTRACTION 1.7 SUMMARY
CHAPTER 1
1999, Z. Navabi and McGraw-Hill Inc.
A digital system design process
Design Idea
Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing
Chip or Board
Top-down design process Starting with a design idea Generating a chip or board
CHAPTER 1
Result of the data path design phase.
DATA
CONTROL
REG1
REG2 Procedure for Control of Movement of Data Between Registers and Buses.
...
MAIN LOGIC UNIT
REG3
LOGIC
...
Dataflow description Control Data partitioning
CHAPTER 1
An ISPS example, a simple processor.
mark1 := BEGIN ** memory.state ** m[0:8191]<31:0>, ** processor.state ** pi\present.instruction<15:0>' f\function<0:2> := pi<15:13>, s<0:12> := pi<12:0>, cr\control.register<12:0>, acc\accumulator<31:0>, ** instruction.execution ** {tc} MAIN i.cycle := BEGIN pi = m[cr]<15:0> NEXT DECODE f => BEGIN 0\jmp := cr = m[s], 1\jrp := cr = cr + m[s], 2\ldn := acc = - m[s], 3\sto := m[s] = acc, 4:5\sub := acc = acc - m[s], 6\cmp := IF acc LSS 0 => cr = cr + 1, 7\stp := STOP(), END NEXT cr = cr + 1 NEXT RESTART i.cycle END
Behavioral Example Only describing functionality
CHAPTER 1
An AHPL example, a sequential multiplier.
AHPLMODULE: multiplier. MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy. EXINPUTS: dataready. EXBUSES: inputbus[8]. OUTPUTS: result[8]; done. CLUNITS: INC[2](count); ADD[5](extra; ac2); 1 ac1 <= inputbus[0:5]; ac2 <= inputbus[4:7]; extra <= 4$0; => ( ^dataready, dataready ) / (1, 2). 2 busy <= \1\; => ( ^ac1[3], ac1[3] ) / (4, 3). 3 extra <= ADD[1:4] (extra; ac2). 4 extra, ac1 <= \0\, extra, ac1[0:2]; count <= INC(count); => ( ^(&/count), (&/count) ) / (2, 5). 5 result = extra, ac1; done = \1\; busy <= \0\; => (1). ENDSEQUENCE CONTROLRESET(1). END.
Dataflow description Describing clock control timing AHPL, A Hardware Programming Language
CHAPTER 1
Full-adder, logical diagram and Verilog code.

a b c g1 w1 g5 s
g2 g3 g4 w3
w2
g6 w4
co
`timescale 1 ns / 1 ns // A 6-gate full adder; this is a comment module fulladder (s, co, a, c, c); // Port declarations output s, co; input a, b, c; // Intermediate wires wire w1, w2, w3, w4; // Netlist description xor #(16, 12) g1 (w1, a, b); xor #(16, 12) g5 (s, w1, c); and #(12, 10) g2 (w2, c, b); and #(12, 10) g3 (w3, c, a); and #(12, 10) g4 (w4, b, a); or #(12, 10) g6 (co, w2, w3, w4); endmodule
Gate level structural description Describes gate level timing Graphical and language based descriptions
CHAPTER 1 6 1999, Z. Navabi and McGraw-Hill Inc.
Hardware simulation.
Hardware Description (Model)
Simulation Hardware Model
Simulation Engine Component Library (Models)
Simulation Results (Output)
Test Data (Stimuli)
Hardware simulation process Component models, unit model form hardware model Testbench may provide test data
CHAPTER 1
Verifying each design stage.
Design Idea SIMULATION TOOLS Behavioral Design Flow Graph, Pseudo Code, .. Data Path Design Bus & Register Structure. Logic Design Gate Wirelist, Netlist. Physical Design Transistor List, Layout, ... Manufacturing Product Sample. Chip or Board Final Testing Device Simulator Gate Level Simulator Dataflow Simulator Behavioral Simulator
Simulate at each step Simulate to verify translation into lower level Simulation cost increases at lower levels
CHAPTER 1
Simulating an exclusive-OR
1 3
7 4 b 2 6
t a b
Simulating an XOR Apply data at given time intervals or Apply data as events occur
CHAPTER 1
Oblivious simulation.
GATE 1 2 3 4 5 6 7
FUNCTION Input Input NOT NOT AND AND OR
INPUT 1 a b 2 1 1 4 5
INPUT 2 ----3 2 6
VALUE 0 0 1 1 0 0 0
Table representation Simulate until no changes are made Record values at table entries
CHAPTER 1
10
Event driven simulation.
1 a Inp 0
3 -
5 0 AND 0
NOT
OR 2 b Inp 0 NOT 0 AND 0 4 6
Legend: In1 In2 Fnc Out In1: Input 1; In2: Input2; Fnc: Function; Out: Output Value
Linked list representation Simulate links with input events Record values at node entries
CHAPTER 1
11
Categories of synthesis tools.
Design Idea
Behavioral Design SYNTHESIS TOOLS 1 4 6 5 3 Physical Design Transistor List, Layout, ... Manufacturing 2 Flow Graph, Pseudo Code, ... Data Path Design Bus & Register Structure Logic Design
Chip or Board
Synthesis Transformation from one level to another Ideal is 6, most commercial tools are 2
CHAPTER 1
12
Synthesis process.
Synthesizable Model Synthesis Hardware Description Scheduling Synthesis Directives
Synthesis Engine
Logic Optimization
Binding
Synthesized Hardware (Netlist)
Hardware description and directives are tool inputs Three synthesis stages Layout or netlist is generated
CHAPTER 1
13
Resource sharing.
c <= a + b; d <= a + b;
c <= a + b; c <= x + y;
b a ADDER
x b
ADDER c d c
Input description affects synthesis results Explicit specification of resource sharing Sharing without and with extra overhead
CHAPTER 1
14
Chapter 2
VHDL Background
2.1 VHDL INITIATION 2.2 EXISTING LANGUAGES 2.2.1 AHPL 2.2.2 CDL 2.2.3 CONLAN 2.2.4 IDL 2.2.5 ISPS 2.2.6 TEGAS 2.2.7 TI-HDL 2.2.8 ZEUS 2.3 VHDL REQUIREMENTS 2.3.1 General Features 2.3.2 Support for Design Hierarchy 2.3.3 Library Support 2.3.4 Sequential Statement 2.3.5 Generic Design 2.3.6 Type Declaration and Usage 2.3.7 Use of Subprograms 2.3.8 Timing Control 2.3.9 Structural Specification 2.4 THE VHDL LANGUAGE 2.5 SUMMARY
CHAPTER 2
VHDL Initiation
1981 DoD Woods Hole MA : Workshop on HDLs Part of VHSIC program
CHAPTER 2
VHDL Initiation
1981 DoD Woods Hole MA : Workshop on HDLs ITAR restrictions 1983 DoD : Requirements were established Contract was awarded to IBM, TI, Intermetrics ITAR restrictions removed from language 1984 IBM, TI, Intermetrics : VHDL 2.0 was defined December 1984 : VHDL 6.0 was released Software development started 1985 : VHDL 7.2 was released to IEEE ITAR removed from software May 1985 : Standard VHDL 1076/A December 1987 : VHDL 1076-1987 became IEEE standard 1993 : VHDL 1076-1993 was approved
CHAPTER 2
Languages reviewed
AHPL CDL CONLAN IDL ISPS TEGAS TI-HDL ZEUS
: A Hardware Programming Language : Computer Design Language : CONsensus LANguage : Interactive Design Language : Instruction Set Processor Specification : TEst Generation And Simulation : TI Hardware Description Language : An HDL by GE corpration
CHAPTER 2
VHDL Requirements
General Features Documentation, High level design, Simulation, Synthesis, Test, Automatic hardware Design Hierarchy Multi-level description Partitioning Library Support Standard Packages Cell based design Sequential Statements Behavioral software-like constructs
CHAPTER 2
VHDL Requirements
Generic Design Binding to specific libraries Type Declaration Strongly typed language Subprograms Timing Delays, concurrency Structural Specification Wiring components
CHAPTER 2
VHDL Requirements
CPU
STACK
ALU
MUX COUNTER
ALU
BIT n
BIT n-1
BIT 0
ALU_BIT
ADDER
MUX
LOGIC
MUX
AND
OR
NOT
Use various levels of abstraction for defining a system Upper level systems are partitioned into lower
CHAPTER 2
Example for hierarchical partitioning.
CPU
STA CK
A LU
M UX COUNTER
AL U
BI T n
BIT n-1
BIT 0
AL U_BI T
A DDER
M UX
L OGIC
M UX
AND
OR
NOT
Recursive partitioning Simple components as terminals
CHAPTER 2
An example VHDL environment.
LIBRARY SYSTEM .3
VHDL Simulator Layout Synthesizer Netlist Synthesizer Other Tools
VHDL Input
Analyzer
Lib. 1
.2
Design Libraries
Library Management
Library Environment
VHDL defines library usage Tools define library management
CHAPTER 2
Chapter 3
Design Methodology Based on VHDL
3.1 ELEMENTS OF VHDL 3.1.1 Describing Components 3.1.2 Packages 3.1.3 Libraries and Binding 3.2 TOP-DOWN DESIGN 3.2.1 Verification 3.3 TOP-DOWN DESIGN WITH VHDL 3.3.1 Design to Perform 3.3.2 Setting The Stage 3.3.3 Design Scenario 3.3.4 Final Act 3.3.5 Real World 3.4 SUBPROGRAMS 3.5 CONTROLLER DESCRIPTION 3.6 VHDL OPERATORS 3.7 CONVENTIONS AND SYNTAX 3.8 SUMMARY
CHAPTER 3
Interface and architectural specifications.
ENTITY component_name IS input and output ports. physical and other parameters. END component_name;
ARCHITECTURE identifier OF component_name IS declarations. BEGIN specification of the functionality of the component in terms of its input lines and influenced by physical and other parameters. END identifier;
CHAPTER 3
Multiple architectural specifications.
ENTITY component_i IS PORT (. . )
..
ARCHITECTURE behavioral OF component_i IS ... ARCHITECTURE dataflow OF component_i IS ... ARCHITECTURE structural OF component_i IS ... other ARCHITECTURES OF component_i ... ...
.. .. ..
CHAPTER 3
Packages.
PACKAGE package_name IS component declarations. sub-program declasrations. END package_name;
PACKAGE BODY package_name IS type definitions. sub-programs. END package_name;
CHAPTER 3
Design binding.
LIBRARY library_name; CONFIGURATION configuration_name OF component_name IS binding of Entities and Architectures. specifying parameters of a design. binding components of a library to subcomponents. END CONFIGURATION;
CHAPTER 3
Recursive partition procedure.
Partition (system) IF HardwareMappingOf (system) IS done THEN SaveHardwareOf (system) ELSE FOR EVERY Functionally-Distinct part_i OF system Partition (part_i); END FOR; END IF; END Partition;
CHAPTER 3
Top-down design, bottom-up implementation.
SUD
Design Implementation
SSC1
SSC2
SSC3
SSC4
SSC31
...
SSC3n
SSC41
SSC42
SSC311
SSC312
SSC3n1
SSC3n2
SUD: System Under Design SSC : System Sub-Component Shaded areas designate sub-componts with hardware implementation.
CHAPTER 3
Verifying the first level of partitioning.
Behavioral Model
are mp Co
SUD
SSC1
SSC2
SSC3
SSC4
Interconnection of Behavioral Models
CHAPTER 3
Verifying hardware implementation.
Behavioral Model
are omp C
SUD
SSC1
SSC2
SSC3
SSC4
Mixed Level Model
CHAPTER 3
Verifying the final design.
Behavioral Model
e par Com
SUD
SSC1
SSC2
SSC3
SSC4
Har dwa re M odel
SSC31
...
SSC3n
SSC41
SSC42
SSC311
SSC312
CHAPTER 3
10
Verifying hardware implementation of SSC3.
Behavioral Model
SSC3
Co
pa
re
SSC31
...
SSC3n
SSC311
SSC312
...
SSC3n1
SSC3n2
Hardware Model
CHAPTER 3
11
Verifying the final design.
p Com
are
SUD
SSC1
SSC2
SSC3
SSC4
Mixed Level Model

SSC41 SSC42
Verifying the final design, an alternative to the setup of Figure 3.9.
CHAPTER 3
12
Serial adder.
a b start clock Synchronously add data on a and b put result on result.
result
ready
CHAPTER 3
13
Available library elements.
1R S1 1D Z 1D C1
1D
(a) Multiplexer
(b) Flipflop
CHAPTER 3
14
Multiplexer library element.
ENTITY mux2_1 IS GENERIC (dz_delay : TIME := 6 NS); PORT (sel, data1, data0 : IN BIT; z : OUT BIT); END mux2_1; -ARCHITECTURE dataflow OF mux2_1 IS BEGIN z <= data1 AFTER dz_delay WHEN sel = '1' ELSE data0 AFTER dz_delay; END dataflow;
VHDL model of the multiplexer library element.
CHAPTER 3
15
Dataflow descriptions.
Busb Reg File Reg1
Alu
Controller
Reg2
Busa
Dataflow descriptions.
CHAPTER 3
16
Flip-flop library element.
ENTITY flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT := '0'); END flop; -ARCHITECTURE behavioral OF flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0' AFTER td_reset; ELSE qout <= din AFTER td_in; END IF; END IF; END PROCESS; END behavioral;
VHDL model of the flip-flop library element.
CHAPTER 3
17
Behavioral descriptions.
Receive
FOR all data : Process data : Queue data : END FOR;
Valid ?
Transmit
. . .
Behavioral descriptions.
CHAPTER 3
18
Divide by 8, counter.
ENTITY counter IS GENERIC (td_cnt : TIME := 8 NS); PORT (reset, clk : IN BIT; counting : OUT BIT := '0'); CONSTANT limit : INTEGER := 8; END counter; -ARCHITECTURE behavioral OF counter IS BEGIN PROCESS (clk) VARIABLE count : INTEGER := limit; BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN count := 0; ELSE IF count < limit THEN count := count + 1; END IF; END IF; IF count = limit THEN counting <= '0' AFTER td_cnt; ELSE counting <= '1' AFTER td_cnt; END IF; END IF; END PROCESS; END behavioral;
Divide by 8, counter.
CHAPTER 3
19
Design stage setting.
VHDL Boolean p r e d e s i g n e d layouts
Synthesize
l i b r a r y
mux2-1
Count
flop
CMOS layout
CHAPTER 3
20
Serial adder behavioral description.
ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0)); END serial_adder; -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) VARIABLE count : INTEGER := 8; VARIABLE sum, carry : BIT; BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0; carry := '0'; ELSE IF count < 8 THEN count := count + 1; sum := a XOR b XOR carry; carry := (a AND b) OR (a AND carry) OR (b AND carry); result <= sum & result (7 DOWNTO 1); END IF; END IF; IF count = 8 THEN ready <= '1'; ELSE ready <= '0'; END IF; END IF; END PROCESS; END behavioral;
Serial adder behavioral description.
CHAPTER 3
21
VHDL simulation results.
CHAPTER 3
22
Partial code of serail_adder.
ELSE IF count < 8 THEN count := count + 1;
sum := a XOR b XOR carry; carry := (a AND b) OR (a AND carry) OR (b AND carry );
result <= sum & result (7 DOWNTO 1); END IF;
CHAPTER 3
23
General layout of serial_adder.
counting counter
serial_sum en si a b Adder carry_out Flop
result Shift Regiser
carry_in
clock
CHAPTER 3
24
First level of partitioning.
serial_adder
full_adder
flip_flop
shifter
counter
CHAPTER 3
25
Full_adder description.
ENTITY fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END fulladder; -ARCHITECTURE behavioral OF fulladder IS BEGIN sum <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin); END behavioral;
CHAPTER 3
26
Shifter VHDL description.
ENTITY shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR (7 DOWNTO 0)); END shifter; -ARCHITECTURE dataflow OF shifter IS BEGIN sh: BLOCK (clk = '0' AND clk'EVENT) BEGIN parout <= "00000000" WHEN reset = '1' ELSE sin & parout (7 DOWNTO 1) WHEN enable = '1' ELSE UNAFFECTED; END BLOCK; END dataflow;
CHAPTER 3
27
Completed parts of first partitioning.
serial_adder
full_adder
flop
shifter
counter
CHAPTER 3
28
Structural description of serial_adder.
ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0)); END serial_adder; -ARCHITECTURE structural OF serial_adder IS COMPONENT counter IS GENERIC (td_cnt : TIME := 8 NS); PORT (reset, clk : IN BIT; counting : OUT BIT := '0'); END COMPONENT; COMPONENT shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR(7 DOWNTO 0)); END COMPONENT; COMPONENT fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END COMPONENT; COMPONENT flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT := '0'); END COMPONENT; -SIGNAL serial_sum, carry_in, carry_out, counting : BIT; BEGIN u1 : fulladder PORT MAP (a, b, carry_in, serial_sum, carry_out); u2 : flop PORT MAP (start, carry_out, clock, carry_in); u3 : counter PORT MAP (start, clock, counting); u4 : shifter PORT MAP (serial_sum, start, counting, clock, result); u5 : ready <= NOT counting; END structural;
CHAPTER 3
29
Signal mapping for fulladder instantiation.
Signals in structural architecture of serial_adder a b carry_in serial_sum carry_out
cin
sum
count
Signals in the interface of fulladder
CHAPTER 3
30
Interconnecting ports.
COMPONENT fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END COMPONENT; COMPONENT flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din , clk : IN BIT; qout : BUFFER BIT := '0'); END COMPONENT; -SIGNAL serial_sum, carry_in, carry_out, counting : BIT; BEGIN u1 : fulladder PORT MAP (a, b, carry_in, serial_sum, carry_out ); u2 : flop PORT MAP (start, carry_out , clock, carry_in);
CHAPTER 3
31
Partitioning shifter.
. . .
shifter
der_flop
der_flop
der_flop
der_flop
der_flop
der_flop
der_flop
der_flop
CHAPTER 3
32
Behavioral model of der_flop.
ENTITY der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : OUT BIT := '0'); END der_flop; -ARCHITECTURE behavioral OF der_flop IS BEGIN PROCESS (clk) BEGIN IF (clk = '0' AND clk'EVENT) THEN IF reset = '1' THEN qout <= '0'; ELSE IF enable = '1' THEN qout <= din; END IF; END IF; END IF; END PROCESS; END behavioral;
CHAPTER 3
33
Structural description of shifter.
ENTITY shifter IS PORT (sin, reset, enable, clk : IN BIT; parout : BUFFER BIT_VECTOR (7 DOWNTO 0)); END shifter; -ARCHITECTURE structural OF shifter IS COMPONENT der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : BUFFER BIT := '0'); END COMPONENT; BEGIN b7 : der_flop PORT MAP ( sin, reset, enable, clk, parout(7)); b6 : der_flop PORT MAP (parout(7), reset, enable, clk, parout(6)); b5 : der_flop PORT MAP (parout(6), reset, enable, clk, parout(5)); b4 : der_flop PORT MAP (parout(5), reset, enable, clk, parout(4)); b3 : der_flop PORT MAP (parout(4), reset, enable, clk, parout(3)); b2 : der_flop PORT MAP (parout(3), reset, enable, clk, parout(2)); b1 : der_flop PORT MAP (parout(2), reset, enable, clk, parout(1)); b0 : der_flop PORT MAP (parout(1), reset, enable, clk, parout(0)); END structural;
CHAPTER 3
34
Hardware realization of der_flop.
enable reset din

S1 1D
qout
1R 1D C1 Q
dff_in
_
1D
clock
CHAPTER 3
35
Partitioning der_flop.
der_flop
mux2_1
flop
CHAPTER 3
36
Structural description of der_flop.
ENTITY der_flop IS PORT (din, reset, enable, clk : IN BIT; qout : BUFFER BIT := '0'); END der_flop; -ARCHITECTURE behavioral OF der_flop IS COMPONENT flop IS GENERIC (td_reset, td_in : TIME := 8 NS); PORT (reset, din, clk : IN BIT; qout : BUFFER BIT); END COMPONENT; COMPONENT mux2_1 IS GENERIC (dz_delay : TIME := 6 NS); PORT (sel, data1, data0 : IN BIT; z : OUT BIT); END COMPONENT; SIGNAL dff_in : BIT; BEGIN mx : mux2_1 PORT MAP (enable, din, qout, dff_in); ff : flop PORT MAP (reset, dff_in, clk, qout); END behavioral;
CHAPTER 3
37
Complete design of seraial_adder.
serial-adder
fulladder
flop
shifter
counter
der-flop
der-flop
. . .
der-flop
. . .
mux2-1 flop
. . .
CHAPTER 3
38
Final Design.
reset Counter counting
. . .
a b Fulladder serial-sum 1 s1 1
1R Q 1D 1R Q 1D
1 s1 1
. . . 1 s1 ...
1
1R Q 1D C1
carry_in
1R 1D C1
C1
C1
carry_out clk
. . .
CHAPTER 3
39
Synthesizable serial adder.
ENTITY serial_adder IS PORT (a, b, start, clock : IN BIT; ready : OUT BIT; result : BUFFER BIT_VECTOR (7 DOWNTO 0)); END serial_adder; -ARCHITECTURE behavioral OF serial_adder IS BEGIN PROCESS (clock) SUBTYPE CNT8 IS INTEGER RANGE 0 TO 8; VARIABLE count : CNT8 := 8; VARIABLE sum, carry : BIT; BEGIN IF (clock = '0' AND clock'EVENT) THEN IF start = '1' THEN count := 0; carry := '0'; ELSE IF count < 8 THEN count := count + 1; sum := a XOR b XOR carry; carry := (a AND b) OR (a AND carry) OR (b AND carry); result <= sum & result (7 DOWNTO 1); END IF; END IF; IF count = 8 THEN ready <= '1'; ELSE ready <= '0'; END IF; END IF; END PROCESS; END behavioral;
CHAPTER 3
40
FPGA layout of serial_adder.
CHAPTER 3
41
Type conversion procedure.
TYPE byte IS ARRAY ( 7 DOWNTO 0 ) OF BIT; ... PROCEDURE byte_to_integer (ib : IN byte; oi : OUT INTEGER) IS VARIABLE result : INTEGER := 0; BEGIN FOR i IN 0 TO 7 LOOP IF ib(i) = '1' THEN result := result + 2**i; END IF; END LOOP; oi := result; END byte_to_integer;
CHAPTER 3
42
The fadd (full adder) function.
FUNCTION fadd (a, b, c : IN BIT) RETURN BIT_VECTOR IS VARIABLE sc : BIT_VECTOR(1 DOWNTO 0); BEGIN sc(1) := a XOR b XOR c; sc(0) := (a AND b) OR (a AND c) OR (b AND c); RETURN sc; END;
CHAPTER 3
43
fulladder using fadd.
ENTITY fulladder IS PORT (a, b, cin : IN BIT; sum, cout : OUT BIT); END fulladder; -ARCHITECTURE behavioral OF fulladder IS BEGIN (sum, cout) <= fadd (a, b, cin); END behavioral;
CHAPTER 3
44
General outline of a controller.
x1
x= ... z<= . . .
z1
. . .
xn
z<= . . .
x= ...
. . .
zn
z<= . . .
clock
CHAPTER 3
45
Moore machine description.
IF 110 sequence is detected on x THEN z gets '1' x ELSE z gets '0' END; z
clk
CHAPTER 3
46
Sequence detector state machine.
1 reset 0 0 0 got1 0
1 got11 0 1
0 got110 1
CHAPTER 3
47
VHDL Description of 110 detector.
ENTITY moore_110_detector IS PORT (x, clk : IN BIT ; z : OUT BIT); END moore_110_detector; -ARCHITECTURE behavioral OF moore_110_detector IS TYPE state IS (reset, got1, got11, got110); SIGNAL current : state := reset; BEGIN PROCESS(clk) BEGIN IF clk = 1 AND clkEVENT THEN CASE current IS WHEN reset => IF x = 1 THEN current <= got1; ELSE current <= reset; END IF; WHEN got1 => IF x = 1 THEN current <= got11; ELSE current <= reset; END IF; WHEN got11 => IF x = 1 THEN current <= got11; ELSE current <= got110; END IF; WHEN got110 => IF x = 1 THEN current <= got1; ELSE current <= reset; END IF; END CASE; END IF; END PROCESS; z <= 1 WHEN current = got110 ELSE 0; END behavioral;
CHAPTER 3
48
State transition and corresponding VHDL code.
1 reset 0 0 got1 0 got11 0
...
...
WHEN got1 => IF x='1' THEN current <= got11 ELSE current <= reset; END IF;
VHDL operators.
Operators AND NAND XOR = < > SLL SLA ROL + OR NOR XNOR /= <= >= SRL SRA ROR &
Operand Type BIT or BOOLEAN All Types Left: BIT or BOOLEAN Vector Right: INTEGER Numeric Array or Array Element Numeric
Result Type BIT or BOOLEAN BOOLEAN
LOGICAL
RELATIONAL
SHIFT
BOOLEAN
ADDING
Same Type
SIGN
Same Type
* MULTIPLYING MOD
INTEGER, REAL
Same Type
REM
INTEGER
Same Type
ABS MISCELLENEOUS **
Numeric Left: Numeric Right: Integer
Same Type
Same as Left
CHAPTER 3
50
Syntax details of the architecture body.
A C I E T R d m O e a p IS R HT C U E e o F z m le S IGNAL a, b, c : B := '0'; IT B G E IN a <= '1' A T R1 N ; FE 5 S b< N TaA T R5N ; = O FE S c <= a AFTER 10 NS; E Dd m ; N e o
architecture declarative_part
architecture body
architecture statem n e t_part
CHAPTER 3
51
Basic Concepts in VHDL
4.1 CHARACTERIZING HARDWARE LANGUAGES 4.1.1 Timing 4.1.2 Concurrency 4.1.3 Modeling Hardware 4.2 OBJECTS AND CLASSES 4.3 SIGNAL ASSIGNMENTS 4.3.1 Inertial Delay Mechanism 4.3.2 Transport Delay Mechanism 4.3.3 Comparing Inertial and Transport 4.4 CONCURRENT AND SEQUENTIAL ASSIGNEMNTS 4.4.1 Concurrent Assignments 4.4.2 Events and Transactions 4.4.3 Delta Delay 4.4.4 Sequential Placements of Transactions 4.5 SUMMARY
CHAPTER 4
Value transfer through wires.
What happens in a real hardware Must be able to model properly
CHAPTER 4
Value transfer through wires.
a := x; b := x;
a <= x AFTER 4*unit_delay; b <= x AFTER 3*unit_delay;
In one case immediate assignemnts are done In another case scheduling is done
CHAPTER 4
Describing sub-components.
S A
Hardware description requires concurrent constructs Concurrent bodies can be described behaviorally or at the dataflow level
CHAPTER 4
A VHDL concurrent body
A VHDL concurrent body Statements are executed when events occur
CHAPTER 4
A VHDL sequential body
ARCHITECTURE sequential ... BEGIN ... PROCESS ... BEGIN . . . IF THEN ELSE . . . FOR LOOP . . . END PROCESS ... END ARCHITECTURE
A VHDL sequential body Statements are executed when program flow reaches them
CHAPTER 4
Illustrating timing and concurrency.
a b g2
x z
g4 c g1 w g3 y
Four concurrent gates Each has a delay of 12 ns Change in inputs may result in in output hazards
CHAPTER 4
Gates reacting to changes.
g1 g2 g3 g4
R a tin e c g R a tin e c g R a tin e c g

R a t e c ing
R a tin e c g
12
24
36
Nanosecond
a changes from 1 to 0
A change in the a input results in domino changes each 12 ns apart No more events occur when output is reached
CHAPTER 4
a b c w x y
12
24
36
Nanosecond
Timing diagram resulting from input a changing from 1 to 0 at time zero A glitch appears on the output Must model hardware to imitate this behavior Requires timing and concurrency in the language
CHAPTER 4
Objects and Classes
del1_constant
del2_constant
concurrent_body_1 sequential_body_1 a_signal a_variable := ... b_signal y_signal <= ... w_signal <= ... loop_variable_i ... x_signal y_signal <= ... w_signal v_signal concurrent_body_3 u_signal <= local_constant v_signal <= ... u_signal concurrent_body_2 x_signal <= ... y_signal
z_signal <= ...
z_signal
Objects and classes in sequential and concurrent bodies Foundation for modeling timing and concurrency are signals Variables are used as software variables
CHAPTER 4
10
Objects and Classes
Using Objects In VHDL O B J E C T Signal Variable Constant File
BODY Declare YES NO YES YES Concurrent Assign to YES NO --Use YES YES YES YES Declare NO YES YES YES Sequential Assign to YES YES --Use YES YES YES YES
Objects in VHDL bodies Cannot declare signals in sequential bodies Variable assignments are only done in sequential bodies
CHAPTER 4
11
Delay Mechanisms
ENTITY example IS END ENTITY; -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT; SIGNAL target1, target2, target3 : BIT; SIGNAL diff12, diff13, diff23 : BIT; -- This is a comment BEGIN -- Illustrating inertial delay target1 <= waveform AFTER 5 NS; target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS; -- Illustrating transport delay target3 <= TRANSPORT waveform AFTER 5 NS; -- Comparing targets diff12 <= target1 XOR target2; diff13 <= target1 XOR target3; diff23 <= target2 XOR target3; -- Creating waveform waveform <=
1 AFTER 03 NS, 1 AFTER 24 NS, 1 AFTER 41 NS, 1 AFTER 62 NS, 1 AFTER 79 NS, 0 AFTER 08 NS, 0 AFTER 27 NS, 0 AFTER 47 NS, 0 AFTER 68 NS, 0 AFTER 85 NS; 1 AFTER 14 NS, 1 AFTER 33 NS, 1 AFTER 52 NS, 1 AFTER 71 NS, 0 AFTER 18 NS, 0 AFTER 35 NS, 0 AFTER 58 NS, 0 AFTER 77 NS,
END delay;
VHDL description for the demonstration of delay mechanisms Example shows several concurrent statements Inertial, Reject and Transport Inertial: rejects anything less than its delay Reject: rejects anything less than or equal to its reject Transport: does not reject
CHAPTER 4
12
Delay Mechanisms
R Target 1 or Target 2 C
The RC delay is best represented by inertial delay mechanism This is a simple version of Inertial For more accurate modeling Reject can be used
CHAPTER 4
13
Delay Mechanisms
2 6
Illustrating differences between delay mechanism in VHDL Positive and negative pulses appear on the LHS
CHAPTER 4
14
Concurrency
ENTITY figure_5_example IS PORT (a, b, c : IN BIT; z : OUT BIT); END figure_5_example; ARCHITECTURE concurrent OF figure_5_example IS SIGNAL w, x, y : BIT; BEGIN w <= NOT a AFTER 12 NS; x <= a AND b AFTER 12 NS; y <= c AND w AFTER 12 NS; z <= x OR y AFTER 12 NS; END concurrent;
VHDL description for the gate level circuit for the demonstration of timing and concurrency Four concurrent statements model gates of the circuit Events of the RHS cause evaluation and scheduling A scheduled value may or may not appear on the LHS A scheduled value is a transaction on the driver of the LHS signal
CHAPTER 4
15
Concurrency
Resolution Function
Multiple Driving Values
Signal Value
A signal may have more than one driver Resolving a single value from multiple driving values Each driver has its own timing Independent handling of all drivers A driving value that is current contributes to the resolution function
CHAPTER 4
16
Events and Transactions
transaction time component
tri = (v, d)
d-t0
tri = (v, d-t ) 0 EXPIRED
0 t t 0 t1 d
tri = (v, 0) now
A transaction, from being created to being expired A transaction that expires generates a current driving value This value contributes to the resolution function
CHAPTER 4
17
ARCHITECTURE demo OF example IS SIGNAL a, b, c : BIT := '0'; BEGIN a <= '1' AFTER 15 NS; b <= NOT a AFTER 5 NS; c <= a AFTER 10 NS; END demo;
A simple description for illustrating events and transactions Transactions are scheduled on the 3 LHS signals Order is not significant Initial transaction are placed on all 3 signals
CHAPTER 4
18
0 0 0
b c
10 (a)
15
20
25
NS
Transactions W hen They Are Placed on Signals
(1, 15) on a (1, 05) on b (0, 10) on c
(1, 05) on b (0, 10) on c
10 (b)
15
20
25
NS
Transactions At 5 NS Intervals a c b a c a c b c
10 (c)
15
20
25
NS
Path Of Transactions To Expiration
a c b b NS c
10
15
20
25
Events and transactions
(d)
CHAPTER 4
19
Delta Delay
ENTITY timing IS PORT (a, b : IN BIT; z, zbar : BUFFER BIT); END ENTITY; -ARCHITECTURE delta of timing IS BEGIN z_bar <= NOT z; z <= a AND b AFTER 10 NS; END delta;
Demonstrating need for delta delay A hidden delay exists between z and z_bar Delta delay makes us believe that they take place at the same real time The hidden delay is Delta which is not real-time
CHAPTER 4
20
Delta Delay
ARCHITECTURE not_properly_timed OF figure_5_example IS SIGNAL w, x, y : BIT := '0'; BEGIN y <= c AND w; w <= NOT a; x <= a AND b; z <= x OR y AFTER 36 NS; END not_properly_timed;
VHDL description for demonstrating the delta delay Sequentiality in execution, same exact real time
CHAPTER 4
21
Delta Delay
a1 b1 c1 w0 x0 y 0 z1 0 1 2 3 0 12 24 36 NS
Timing diagram showing delta delays Looking at real times, we do not see Sequentiality
CHAPTER 4
22
Delta Delay
ARCHITECTURE concurrent OF timing_demo IS SIGNAL a, b, c : BIT := '0'; BEGIN a <= '1'; b <= NOT a; c <= NOT b; END concurrent;
Description for a chain of two inverters Demonstrating Delta, transactions and concurrency
CHAPTER 4
23
Delta Delay
a 0
b0
c 0
NS
Timing diagram for timing_demo Everything happens at real-time 0
CHAPTER 4
24
Delta Delay
Ideal elements with zero real time delay.
ARCHITECTURE forever OF oscillating IS SIGNAL x: BIT := 0; SIGNAL y: BIT := 1; BEGIN x <= y; y <= NOT x; END forever;
0 0 1 2 3 4 5 6 7 0
1 0 1 2 3 4 5 6 0
Oscillation in zero real time Dont try this at home

Sequential Placement of Transactions
ARCHITECTURE sequential OF sequential_placement IS ... BEGIN PROCESS x<= v1 AFTER t1; x<= v2 AFTER t2; WAIT; END PROCESS; END sequential;
Sequential placement of transactions in a sequential body of VHDL A wait; statement suspends a sequential body forever Sequentially values are placed on the LHS
CHAPTER 4
26
ARCHITECTURE concurrent OF sequential_placement IS ... BEGIN a <= v1, v2 AFTER t2-t1 x <= a AFTER t2; END concurrent;
Sequential placement of transaction in a concurrent body of VHDL Same effect as the above process statement
CHAPTER 4
27
Projected output waveform A new transaction will be compared with all existing transactions It appends, or overrides existing ones
CHAPTER 4
28
Multiple drivers of a resolved signal Each driver timing is treated independently
CHAPTER 4
29
TRANSPORT 1 New Transaction is BEFORE Already Existing Overwrite existing transaction 3
INERTIAL
Overwrite existing transaction
2 New Transaction is AFTER Already Existing Append the new transaction.
v = v existing new 4 Append the new transaction.
Difference between time of new and existing is greater than the reject value
v /=v existing new 5 Append the new transaction
Difference between time of new and existing is less than or equal to reject value
v /=v existing new 6 Overwrite existing transaction
Effective transactions on the driver of a signal Multiple transactions are sequentially placed on the signal driver
CHAPTER 4
30
ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit := Z; BEGIN PROCESS BEGIN x <= 1 AFTER 5 NS; x <= TRANSPORT 0 AFTER 3 NS; WAIT; END PROCESS; END sequential;
x z z 0 7 8 9
0 1 2 3 4 5 6
Discarding previous transactions The new transaction is scheduled before the existing one.
CHAPTER 4
31
ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := Z; BEGIN PROCESS BEGIN x <= 1 AFTER 5 NS; x <= TRANSPORT 0 AFTER 8 NS; WAIT; END PROCESS; END sequential;
x z z 1 0 7 8 9
0 1 2 3 4 5 6
Appending transactions Delay type is transport The new transaction is after the existing one.
CHAPTER 4
32
ARCHITECTURE sequential OF overwriting_old IS SIGNAL x : rit := Z; BEGIN PROCESS BEGIN x <= 1 AFTER 5 NS; x <= 0 AFTER 3 NS; WAIT; END PROCESS; END sequential;
x z z 0 7 8 9
0 1 2 3 4 5 6
Discarding previous transactions The new transaction is scheduled before the existing one
CHAPTER 4
33
ARCHITECTURE sequential OF saving_all IS SIGNAL x : rit := Z; BEGIN PROCESS BEGIN x <= 0 AFTER 5 NS; x <= 0 AFTER 8 NS; WAIT; END PROCESS; END sequential;
x z z 0 7 8 9
0 1 2 3 4 5 6
Saving previous transactions of same value Transactions with the same value are both kept on the driver of x
CHAPTER 4
34
ARCHITECTURE sequential OF appending IS SIGNAL x : rit :=Z; BEGIN PROCESS BEGIN x <= 1 AFTER 5 NS; x <= REJECT 2 NS INERTIAL 0 AFTER 8 NS; WAIT; END PROCESS; END sequential;
x
Z z Z 1 0
Appending the new transaction of different value Time difference of new and existing is greater than reject value
CHAPTER 4
35
ARCHITECTURE sequential OF discarding_old IS SIGNAL x : rit :=Z; BEGIN PROCESS BEGIN x <= 1 AFTER 5 NS; x <= REJECT 4 NS INERTIAL 0 AFTER 8 NS; WAIT; END PROCESS; END sequential
x z z 0
7 8 9
0 1 2 3 4 5 6
Discarding previous transactions of different value The new transaction is scheduled after the existing, and has a different value
CHAPTER 4
36
ENTITY example IS END ENTITY; -ARCHITECTURE delay OF example IS SIGNAL waveform : BIT; SIGNAL target1, target2, target3 : BIT; BEGIN -- Signal assignments target1 <= waveform AFTER 5 NS; target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS; target3 <= TRANSPORT waveform AFTER 5 NS; -- Creating waveform waveform <=
'1' AFTER 03 NS, '0' AFTER 08 NS, '1' AFTER 14 NS, '0' AFTER 18 NS, '1' AFTER 24 NS, '0' AFTER 27 NS, '1' AFTER 33 NS, '0' AFTER 35 NS;
END delay;
14
18
24
27
29
32 33
35
38
40
Pulse rejection in inertial, reject, and transport delay mechanisms This is a result of sequential placement of transactions
CHAPTER 4
37
CHAPTER 4
(1,3) (0,5) (0,0) (1,2) (0,0) (1,5) (1,3) (0,0) (1,5) (0,5) (1,5) (0,5) (0,5) (1,0) (0,0) (1,1) (1,3) (0,5) (0,5) (1,0) (1,5) (1,2) (0,0) (0,0) (1,0) (0,0) (1,1) (1,5) (0,5) (0,5) (1,3) (1,5) (1,3) (0,0) (1,3) (0,5) (0,5) (1,1) (1,5) (1,0) (0,0) (1,2) (0,5) (1,0) (0,0) (1,5) (0,5) (0,0) (1,0) (0,0) (1,5) (1,3) (1,0) (0,0)
(1,5)
(0,5)
(0,2)
target1
(1,5)
(0,5)
(0,2)
target2
New, pending, and expired transactions on targets of example
38
5 8 13 14 18 19 23 24 27 29
(1,5)
(0,2)
target3
32 33
35
38
40
ENTITY example IS END ENTITY; -ARCHITECTURE delay OF example IS SIGNAL a, b : BIT; BEGIN -- Signal assignments a <= '1' AFTER 5 NS, '0' AFTER 10 NS, '1' AFTER 15 NS; b <= '0', a AFTER 3 NS; END delay;
Sequential placement of transactions by executing concurrent signal assignments Events on a cause placement of transactions on b In a waveform, all but the first are TRANSPORT
CHAPTER 4
39
CHAPTER 5 STRUCTURAL SPECIFICATION OF HARDWARE
5.1 PARTS LIBRARY 5.1.1 Inverter Model 5.1.2 NAND Gate Models 5.2 WIRING OF PRIMITIVES 5.2.1 Logic Design of Comparator 5.2.2 VHDL Description of bit_comparator 5.3 WIRING ITERATIVE NETWORKS 5.3.1 Design of a 4-Bit Comparator 5.3.2 VHDL Description of a 4-Bit Comparator 5.4 MODELING A TEST BENCH 5.4.1 VHDL Description of A Simple Test Bench 5.4.2 Simulation 5.6 BINDING ALTERNATIVES 5.6 TOP-DOWN WIRING 5.6.1 Sequential Comparator 5.6.2 Byte Latch 5.6.3 Byte Comparator 5.7 SUMMARY
CHAPTER 5
1999, Zainalabedin Navabi
Parts Library
(a)
ENTITY inv IS PORT (i1 : IN BIT; o1 : OUT BIT); END inv; (b) ARCHITECTURE single_delay OF inv IS BEGIN o1 <= NOT i1 AFTER 4 NS; END single_delay; (c)
inv i1 o1
(d)
Inverter Symbol Entity declaration Architecture body Notation.
CHAPTER 5
Parts Library
ENTITY inv IS PORT ( entity declaration i1 : IN BIT ; o1 : OUT BIT ) ; END inv; interface_signal_declaration interface_signal_declaration port clause
Details of the entity declaration of inverter Port clause Interface signal declaration
CHAPTER 5
Parts Library
entity_name
Interface Aspect Input Port Output Port Bidirectional Port Buffer Port

CHAPTER 5
Elements of aspect notation Input Output Inout Buffer is output that can be used on RHS
4 1999, Zainalabedin Navabi
Parts Library
Using ports, Inputs, Outputs, Bi-directional ports, Buffers Inout implies In and Out (two wires) Buffer can be used inside an architecture
CHAPTER 5
Parts Library
(a) ENTITY nand2 IS PORT (i1, i2 : IN BIT; o1 : OUT BIT); END nand2; (b) ARCHITECTURE single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 5 NS; END single_delay; (c)
nand2 i1 i2
(d)
o1
Two-input NAND symbol Entity declaration Architecture body uses NAND operator
CHAPTER 5
Parts Library
PORT ( i1, i2 : IN BIT ; o1 : OUT BIT )
identifier_list mode type interface signal declaration port clause
interface list
interface_signal_declaration
Port clause details for nand2 Signal declaration includes identifier list Mode and type are the same as those of the inverter
CHAPTER 5
Parts Library
(a) ENTITY nand3 IS PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT); END nand3; (b) ARCHITECTURE single_delay OF nand3 IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER 6 NS; END single_delay; (c)
i1 i2 i3
nand3 o1
Three-input NAND symbol Architecture body and notation are shown Must use AND and NOT
CHAPTER 5
Wiring Components
Comparator A B A>B A=B > = < A 0 1 1 1 a>b 00 01 11 10 1 1
a, b = 0 1 1 a=b 1 00 01 11 10
a, b < 0 1 1 00 01 1 1 a<b 1 11 10
Karnaugh maps for the outputs of the single bit comparator Each output depends on data inputs and its corresponding control input
CHAPTER 5
10
Wiring Components
a_gt_b = a . gt + b . gt + a . b a_eq_b = a . b . eq + a . b . eq a_lt_b = a . lt + b . lt + a . b
a_gt_b = ((a . gt).( b . gt).( a . b)) a_eq_b = ((a . b . eq).(a . b . eq)) a_lt_b = ((a . lt).(b . lt).( a . b))
Boolean expression for the outputs Use DeMorgans for all-NAND implementation
CHAPTER 5
11
Wiring Components
a gt
a_gt_b b
a b eq
a_eq_b
a a_lt_b
lt
Logic diagram of bit_comparator Using only our primitive components
CHAPTER 5
12
Wiring Components
bit_comparator a b gt eq lt a_gt_b a_eq_b a_lt_b
(a) ENTITY bit_comparator IS PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END bit_comparator; -- data inputs -- previous greater than -- previous equal -- previous less than -- greater -- equal -- less than
(b)
Interface description of bit_comparator Inputs and outputs of BIT type are declared
CHAPTER 5
13
Wiring Components
bit_comparator (gate_level) a nand2 i1 i2 o1 im3
nand2 i1 i2 o1
im4
i1 i2 i3
nand3 o1 a_gt_b
inv i1 o1
im2
i1 i2
nand2 o1 im5
gt i1 i2 i3 nand3 o1 nand2 nand3 o1 im7 i1 i2 o1 a_eq_b im6
eq lt
i1 i2 i3
nand2 i1 i2 o1
im8
inv i1 o1
im1 i1 i2
nand2 o1
im9
i1 i2 i3
nand3 o1
a_lt_b
nand2 i1 i2 o1 im10
Composition Aspect of bit_comparator.

CHAPTER 5 14 1999, Zainalabedin Navabi
Wiring Components
ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n1 USE ENTITY WORK.inv (single_delay); FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay); -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN -- a_gt_b output g0 : n1 PORT MAP (a, im1); g1 : n1 PORT MAP (b, im2); g2 : n2 PORT MAP (a, im2, im3); g3 : n2 PORT MAP (a, gt, im4); g4 : n2 PORT MAP (im2, gt, im5); g5 : n3 PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : n3 PORT MAP (im1, im2, eq, im6); g7 : n3 PORT MAP (a, b, eq, im7); g8 : n2 PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : n2 PORT MAP (im1, b, im8); g10 : n2 PORT MAP (im1, lt, im9); g11 : n2 PORT MAP (b, lt, im10); g12 : n3 PORT MAP (im8, im9, im10, a_lt_b); END gate_level;
Architecture body of bit_comparator identified as gate_level Components instantiations constitute the body Each instantiation has a label, component name, and PORT MAP Component declarations are local to the architecture
Wiring Components
ARCHITECTURE gate_level OF bit_comparator IS COMPONENT n3 PORT (i1, i2, i3: IN BIT; O1: OUT BIT); END COMPONENT; ... FOR ALL : n3 USE ENTITY ... SIGNAL im1, im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN ... g7 : n3 PORT MAP (a, b, eq, im7); ... ... END gate_level;
component declaration
configuration specification
architecture declarative part architecture body
signal declaration
component instantiation statement
architecture statement part
Syntax details of the architecture body bit_comparator Signals in the entity are visible to the architecture
of
CHAPTER 5
16
Wiring Components
g7 : n3 PORT MAP ( a, b, eq, im7 ) ;
instantiation_label component_name component instantiation statement
association_list
port map aspect
Component instantiation statement syntax details A label is required It includes an association list
CHAPTER 5
17
Wiring Components
ARCHITECTURE netlist OF bit_comparator IS -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN -- a_gt_b output g0 : ENTITY WORK.inv(single_delay) PORT MAP (a, im1); g1 : ENTITY WORK.inv(single_delay) PORT MAP (b, im2); g2 : ENTITY WORK.nand2(single_delay) PORT MAP (a, im2, im3); g3 : ENTITY WORK.nand2(single_delay) PORT MAP (a, gt, im4); g4 : ENTITY WORK.nand2(single_delay) PORT MAP (im2, gt, im5); g5 : ENTITY WORK.nand3(single_delay) PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : ENTITY WORK.nand3(single_delay) PORT MAP (im1, im2, eq, im6); g7 : ENTITY WORK.nand3(single_delay) PORT MAP (a, b, eq, im7); g8 : ENTITY WORK.nand2(single_delay) PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : ENTITY WORK.nand2(single_delay) PORT MAP (im1, b, im8); g10 : ENTITY WORK.nand2(single_delay) PORT MAP (im1, lt, im9); g11 : ENTITY WORK.nand2(single_delay) PORT MAP (b, lt, im10); g12 : ENTITY WORK.nand3(single_delay) PORT MAP (im8, im9, im10, a_lt_b); END netlist;
Netlist description of bit_comparator This is direct instantiation If architecture name is not specified, the most recently compiled architecture will be used
CHAPTER 5
18
Wiring Components
bit_comparator simulation run keeping control inputs at 010
CHAPTER 5
19
Wiring Iterative Networks
4 Data inputs 4
Four Bit Comparator A B A>B A=B Compare outputs
Control inputs
> = <
A = < A>B A=B A = < A>B A=B AB A=B A
A 4-bit comparator using four single bit comparators Numbers different in MSB, produce results faster Worst case delay for equal inputs
CHAPTER 5
21
nibble_comparator a(3:0) a_gt_b b(3:0) gt eq lt a_eq_b a_lt_b
(a)
ENTITY nibble_comparator IS PORT (a, b : IN BIT_VECTOR (3 DOWNTO 0);-- a and b data inputs gt, -- previous greater than eq, -- previous equal lt : IN BIT; -- previous less than a_gt_b, -- a > b a_eq_b, -- a = b a_lt_b : OUT BIT); -- a < b END nibble_comparator;
Interface description of nibble_comparator, interface aspect, (b) entity declaration Inputs of of BIT_VECTOR type Can use any range
(a)
CHAPTER 5
22
nibble_comparator(iterative) a(3:0) b(3:0) a(3) b(3) bit_comparator a (gate_level) Bit 3 b gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b
a(2) b(2)
bit_comparator a (gate_level) Bit 2 b gt a_gt_b a_eq_b a_lt_b
c1to2:
im(6) im(7) im(8)
gt
eq lt
eq
lt a(1) b(1)
bit_comparator a (gate_level) Bit 1 b gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5)
a(0) b(0)
bit_comparator a (gate_level) Bit 0 b gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2)
Composition aspect of nibble_comparator
CHAPTER 5
23
ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (gate_level); SIGNAL im : BIT_VECTOR ( 0 TO 8); BEGIN c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b, a_lt_b); END iterative;
Iterative architecture of nibble_comparator Uses nested generate statements Can easily expand by changing numbers
CHAPTER 5
24
PORT MAP (a(i),
b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) )
i=1
i=1
i=1
i=1
i=1
i=1
i=1
i=1
PORT MAP (a(1),
b(1),
im(0),
im(1),
im(2),
im(3),
im(4),
im(5)
Association list of c instance of comp1 within generate statement Bit 1 is configured for i value of 1
CHAPTER 5
25
c1to2 : FOR i IN 1 TO 2 GENERATE c: COMP1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2)); END GENERATE ;
generate_label generation_scheme generate statement concurrent_statement
Generate statement syntax details This is a concurrent statement The body of a generate statement is concurrent Can use FOR or IF generation scheme
CHAPTER 5
26
ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (gate_level); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END iterative;
A more flexible iterative architecture of nibble_comparator Constant n sizes the comparator There is still a better way, use unconstrained arrays; Chap 7.
CHAPTER 5
27
l: IF i = 0 GENERATE FOR least : comp1 USE ENTITY WORK.bit_comparator (gate_level); BEGIN least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE;
Configuration specifications create some ambiguities Problem is corrected by Generate Statement Declarative Part Binding indication appears here
CHAPTER 5
28
Modeling a Test Bench
test_bench (input_output) nibble_comparator (iterative) a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b
A test bench for nibble_comparator, the composition aspect A test bench does not use ports All signals used must be explicitly declared
CHAPTER 5
29

ENTITY nibble_comparator_test_bench IS END nibble_comparator_test_bench ; -ARCHITECTURE input_output OF nibble_comparator_test_bench IS COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0); a_gt_b, a_eq_b, a_lt_b : IN BIT; a_gt_b_out, a_eq_b_out, a_lt_b_out : OUT BIT); END COMPONENT; FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(iterative); SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); a2: a <= "0000", ---- a = b (steady state) "1111" AFTER 0500 NS, -- a > b (worst case) "1110" AFTER 1500 NS, -- a b (need bit 1 info) "1010" AFTER 3500 NS, -- a < b (need bit 2 info) "0000" AFTER 4000 NS, -- a < b (steady state, prepare for next) "1111" AFTER 4500 NS, -- a = b (worst case) "0000" AFTER 5000 NS, -- a b (need bit 3 only, best case) a3 : b <= "0000", ---- a = b (steady state) "1110" AFTER 0500 NS, -- a > b (worst case) "1111" AFTER 1500 NS, -- a b (need bit 1 info) "1100" AFTER 3500 NS, -- a < b (need bit 2 info) "1111" AFTER 4000 NS, -- a < b (steady state, prepare for next) "1111" AFTER 4500 NS, -- a = b (worst case) "1111" AFTER 5000 NS, -- a b (need bit 3 only, best case) END input_output;
Test bench for nibble_comparator.

CHAPTER 5 30
iterative
architecture
of
TIME (NS) 0 5 500 544 548 1500 1544 1548 2500 2533 2537 3500 3522 3526 4000 4500 4544 4548 5000 5011 5015 5500 5544 5548 6000 6011 6015
a(3:0) "0000" ...... "1111" ...... ...... "1110" ...... ...... ...... ...... ...... "1010" ...... ...... "0000" "1111" ...... ...... "0000" ...... ...... ...... ...... ...... "1111" ...... ......
SIGNALS b(3:0) gtr "0000" ...... "1110" ...... ...... "1111" ...... ...... "1100" ...... ...... ...... ...... ...... "1111" ...... ...... ...... ...... ...... ...... "0000" ...... ...... ...... ...... ...... '0' ... ... '1' ... ... '0' ... ... ... '1' ... '0' ... ... ... ... ... ... ... ... ... ... ... ... '1' ...
eql '0' '1' ... ... '0' ... ... ... ... ... ... ... ... ... ... ... '1' ... ... '0' ... ... ... '1' ... ... '0'
lss '0' ... ... ... ... ... ... '1' ... '0' ... ... ... '1' ... ... ... '0' ... ... '1' ... '0' ... ... ... ...
Simulation report for simulating iterative comparator test bench All events are observed
CHAPTER 5
31
Binding Alternatives
C S 1 3 Q
R 2
Logical diagram of a simple latch With equal timing this will not work Will use this example for showing binding alternatives Correct the oscillation problem by binding to NAND gates of different delay values
CHAPTER 5
ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT); END sr_latch; -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); SIGNAL im1, im2, im3, im4 : BIT; BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3; END gate_level;
VHDL description of set-reset latch This is using the 2-input NAND for all four instances Signal assignment avoids use of Buffer The single_delay architecture is used
CHAPTER 5
33
ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1, i2: IN BIT; o1: BUFFER BIT); END COMPONENT; FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); SIGNAL im1, im2, im4 : BIT; BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, q); g4 : n2 PORT MAP (q, im2, im4); END gate_level;
sr_latch (gate_level) architecture using BUFFER componet declaration and the actual entity must match is PORT MAP is not used with the configuration specification The 2-input NAND must change to use BUFFER instead of OUT
ARCHITECTURE fast_single_delay OF nand2 IS BEGIN o1 <= i1 NAND i2 AFTER 3 NS; END fast_single_delay;
A faster NAND gate The gate delay is 3 NS Uses the same entity as the single_delay NAND Using this NAND corrects the oscillation problem
CHAPTER 5
35
c s i1 i2
(fast_single_delay)
sr_latch (gate_level) nand2 g1: im1

(fast_single_delay)
nand2 g3:
o1
i1 i2
o1
im3
i1 i2
(single_delay)
nand2 g2:
o1
im2
i1 i2
(single_delay)
nand2 g4:
o1 im4
(a)
SR-latch, using gates with different delays, composition aspect Same wiring as the latch that oscillates
CHAPTER 5
36
ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; FOR g1, g3 : n2 USE ENTITY WORK.nand2 (fast_single_delay); FOR g2, g4 : n2 USE ENTITY WORK.nand2 (single_delay); SIGNAL im1, im2, im3, im4 : BIT; BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3; END gate_level;
SR-latch, using gates with different delays, architecture body Same wiring, different binding Fast_single_delay architecture is used for g1 and g3
CHAPTER 5
37
c s i1 i2
(single_delay)
sr_latch (gate_level) nand2 g1: im1 nand2 g3: q
o1
i1 i2
(single_delay)
o1
im3
i1 i2 i3
nand3
(single_delay)
o1 g2:
im2
i1 i2 i3
(single_delay)
nand3
im4 o1
g4:
(a)
SR-latch, using nand2 and nand3 gates, composition aspect This solution uses 3-input NAND gates The 3-input gates have different delay values than the 2-input NAND gates
CHAPTER 5
38
ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (x, y: IN BIT; z: OUT BIT); END COMPONENT; FOR g1, g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x, y, z); FOR g2, g4 : n2 USE ENTITY WORK.nand3 (single_delay) PORT MAP (x, x, y, z); SIGNAL im1, im2, im3, im4 : BIT; BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3; END gate_level;
ALTERNATIVELY: FOR g1, g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x, y, z); FOR OTHERS : n2 USE ENTITY WORK.nand3 (single_delay) PORT MAP (x, x, y, z);
SR-latch, using nand2 and nand3 gates, architecture Configuration specification takes caring of wiring the 3-input NAND into a 2-input NAND PORT MAP in binding, overrides the default Could use OTHERS
Signals of gate_level of sr_latch
im2 Port map association of instantiation statement
Local ports of g2 instance of n2
z Port map association of configuration specification
Formal ports of nand3
in1 in2
in3
o1
Two-step association Declaration is local Names in declaration are used only when not specified in a configuration specification
CHAPTER 5
40
FOR g1, g3 : n2 USE ENTITY WORK.nand2 (single_delay) PORT MAP (x, y, z) ;
instantiation_list component_name component specification
entity aspect binding indication port map aspect
configuration specification
Configuration specification syntax details Binding indication contains entity aspect, port map aspect, and generic map aspect If not specified, those of the declaration will be used Declarations are still needed unless direct instantiations are used
Top-Down Wiring
old_new_comparator byte_comparator i di byte_latch con1 clk clk a b gt eq lt a_gt_b a_eq_b a_lt_b
Will develop a complete example, compare old and new data, keep a count Defaults will be used Most recently compiled architectures are used in the absence of configuration specifications Composition aspect of old_new_comparator
Top-Down Wiring
ENTITY old_new_comparator IS PORT (i : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; gt_compare, eq_compare : OUT BIT); END old_new_comparator; -ARCHITECTURE wiring OF old_new_comparator IS COMPONENT byte_latch PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR (7 DOWNTO 0)); END COMPONENT; COMPONENT byte_comparator PORT(a, b : BIT_VECTOR (7 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL con1 : BIT_VECTOR (7 DOWNTO 0); SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN l : byte_latch PORT MAP(i, clk, con1); c : byte_comparator PORT MAP(con1, i, gnd, vdd, gnd, gt_compare, eq_compare, OPEN); END wiring;

CHAPTER 5
old_new_comparator VHDL description Declarations are present Configuration specifications are missing Use OPEN for unconnected outputs OPEN inputs must have a default value
Top-Down Wiring
ENTITY byte_latch IS PORT (di : IN BIT_VECTOR (7 DOWNTO 0); clk : IN BIT; qo : OUT BIT_VECTOR( 7 DOWNTO 0)); END byte_latch; -ARCHITECTURE iterative OF byte_latch IS COMPONENT d_latch PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT; BEGIN g : FOR i IN di'RANGE GENERATE l7dt0 : d_latch PORT MAP (di(i), clk, qo(i)); END GENERATE; END iterative;
An 8-bit latch is required for this design Use a configurable description based on D-type latch VHDL description of byte_latch. Iterative architecture is used
CHAPTER 5
44
Top-Down Wiring
c d inv i1 o1
sr_latch C S q q
(a)
Build a D-latch using our sr_latch and an inverter Composition aspect is shown
CHAPTER 5
45
Top-Down Wiring
ENTITY d_latch IS PORT(d,c : IN BIT;q: OUT BIT); END d_latch; -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr_latch PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT inv PORT (i1 : IN BIT; o1 : OUT BIT); END COMPONENT; SIGNAL dbar: BIT; BEGIN c1 : sr_latch PORT MAP (d, dbar, c, q); c2 : inv PORT MAP (d, dbar); END sr_based; (b)
Design of d_latch, VHDL description Configuration specifications are not used Local declarations are used for ports and name of the actual entity
CHAPTER 5
46
Top-Down Wiring
ARCHITECTURE iterative OF nibble_comparator IS COMPONENT bit_comparator PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; CONSTANT n : INTEGER := 8; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE
least: bit_comparator PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );
END GENERATE; m: IF i = n-1 GENERATE most: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: bit_comparator PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END iterative;
Another necessary component for this design is an 8bit comparator Byte comparator VHDL description Uses 8 instances of bit_comparator Constant n is changed to 8 Default architectures are used
Top-Down Wiring
A structural description for a design consists of a wiring specification of its subcomponents. In this chapter, the
definition and usage of components in larger designs was illustrated. Generate statements also were introduced as a convenient way to describe repetitive hardware structures and a notation was defined for graphical representation of structural descriptions. In addition, various forms and
options in component declarations and configuration specifications were discussed. The last part of this chapter presented a top-down design using basic gates and components presented in the earlier sections. Using simple gates, the reader should now be able to design larger digital circuits with many levels of component nesting.
End Of Chapter 5
CHAPTER 5
48
CHAPTER 6 DESIGN ORGANIZATION AND PARAMETERIZATION
6.1 DEFINITION AND USAGE OF SUBPROGRAMS 6.1.1 A Functional Single Bit Comparator 6.1.2 Using Procedures in a Test Bench 6.1.3 Language Aspects of Subprograms 6.1.4 Utility Procedures 6.2 PACKAGING PARTS AND UTILITIES 6.2.1 Packaging Components 6.2.2 Packaging Subprograms 6.3 DESIGN PARAMETRIZATION 6.3.1 Using Default Values 6.3.2 Using Fixed Values 6.3.3 Passing Generic Parameters 6.4 DESIGN CONFIGURATION 6.4.1 A General Purpose Test Bench 6.4.2 Configuring Nested Components 6.4.3 Incremental Binding 6.4.4 An n-bit Register Example 6.4.5 Iterative Parity Checking 6.5 DESIGN LIBRARIES 6.5.1 Existing Libraries 6.5.2 Library Management 6.6 SUMMARY
CHAPTER 6
Definition and Usage of Subprograms
GT Equation EQ Equation LT Equation
a_gt_b = a . gt + b' . gt + a . b' a_eq_b = a . b . eq + a' . b' . eq a_lt_b = b . lt + a' . lt + b . a'
ARCHITECTURE functional OF bit_comparator IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; BEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS; END functional;
An architecture for demonstrating use of subprograms
Demonstrating the use of functions Use functions in place of Bololean expresssions A functional bit_comparator, using the same function for two outputs
FUNCTION fgl ( w, x, g1 :BIT) RETURN BIT IS BEGIN RETURN (w AND g1) OR (NOT x AND g1) OR (w AND NOT x) ; END;
designator formal_parameter_list type_mark subprogram body expression return statement sequential statement subprogram statement part subprogram specification
Function body is sequential Use functions for utilities and coding style Syntax details of a subprogram body, a general view
ARCHITECTURE structural OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := 4; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE; END structural;
Using the functional bit_comparator Structural architecture of a nibble_comparator
CHAPTER 6

ARCHITECTURE procedural OF nibble_comparator_test_bench IS
TYPE integers IS ARRAY (0 TO 12) OF INTEGER; PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME) IS VARIABLE j : INTEGER; VARIABLE tmp, pos : INTEGER := 0; VARIABLE buf : BIT_VECTOR (3 DOWNTO 0); BEGIN FOR i IN 0 TO 12 LOOP tmp := values (i); j := 0; WHILE j <= 3 LOOP IF (tmp MOD 2 = 1) THEN buf (j) := '1'; ELSE buf (j) := '0'; END IF; tmp := tmp / 2; j := j + 1; END LOOP; target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;
COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural); SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);
apply_data (a, 00&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS); apply_data (b, 00&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);
END procedural;
Defining and using a procedure Procedural architecture of nibble_comparator INTEGERS type is an array of 13 integers
CHAPTER 6
TIME (NS) 0 48 500 548 1500 1548 2500 2536 3500 3524 4000 4500 4548 5000 5012 5500 5548 6000 6012
a(3:0) "0000" ...... "1111" ...... "1110" ...... ...... ...... "1010" ...... "0000" "1111" ...... "0000" ...... ...... ...... "1111" ......
SIGNALS b(3:0) gtr "0000" ...... "1110" ...... "1111" ...... "1100" ...... ...... ...... "1111" ...... ...... ...... ...... "0000" ...... ...... ...... '0' ... ... '1' ... '0' ... '1' ... '0' ... ... ... ... ... ... ... ... '1'
eql '0' '1' ... '0' ... ... ... ... ... ... ... ... '1' ... '0' ... '1' ... '0'
lss '0' ... ... ... ... '1' ... '0' ... '1' ... ... '0' ... '1' ... '0' ... ...
Simulation report resulting from the procedural test bench All events are observed Shows increments of 12 NS only
PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME ) IS VARIABLE j : INTEGER; VARIABLE tmp : INTEGER := 0; VARIABLE buf: BIT_VECTOR (3 DOWNTO 0); BEGIN; FOR i IN 0 TO 12 LOOP . . . END LOOP; END apply_data;
subprogram specification formal parameter list
subprogram declarative part
subprogram body
loop statement
sequential statement
subprogram statement part

CHAPTER 6
Details of a subprogram body Function or procedure subprogram specification Subprograms are procedural bodies Nested procedural statements
FOR i IN 0 TO 12 LOOP . . . END LOOP;
loop parameter specification
iteration scheme
loop_statement
sequence_of_statement

CHAPTER 6
Loops are procedural Loop statement with FOR iteration scheme Can nest procedural statements Sequence_of_statements is the sequential construct
IF (tmp MOD 2 = 1) THEN buf (j) := 1; ELSE buf (j) := 0; END IF;
condition if_statement sequence_of_statements sequence_of_statements
Details of the If statement of apply_data procedure This is a procedural statement Sequence_of_statements is the sequential construct
CHAPTER 6
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int;
Can do utility procedures RANGE attribute makes this a generic procedure Procedure for binary to integer conversion
CHAPTER 6
10
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin;
Another utility procedure Procedure for integer to binary conversion LENGTH attribute is used here
CHAPTER 6
11
PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0); BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;

CHAPTER 6
Can use procedures within procedure Another version of apply_data procedure This version takes advantage of the int2bin procedure TRASPORT delay schedules all transactions at time 0
FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END to_integer;
Functions can serve as utilities Binary to integer conversion function Assumes lower bound of 0, otherwise it is a generic function
Packaging Parts and Utilities
-- Packaging components PACKAGE simple_gates IS COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 PORT (i1: i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; END simple_gates;
Demonstrating specification and usage of packages
Component declarations as well as utilities can be packaged A package declaration containing component declarations of simple gates Eliminates the need for individual declarations
USE WORK.simple_gates.ALL; ARCHITECTURE gate_level OF bit_comparator IS FOR ALL : n1 USE ENTITY WORK.inv (single_delay); FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay); FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay); -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN -- a_gt_b output g0 : n1 PORT MAP (a, im1); g1 : n1 PORT MAP (b, im2); g2 : n2 PORT MAP (a, im2, im3); g3 : n2 PORT MAP (a, gt, im4); g4 : n2 PORT MAP (im2, gt, im5); g5 : n3 PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : n3 PORT MAP (im1, im2, eq, im6); g7 : n3 PORT MAP (a, b, eq, im7); g8 : n2 PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : n2 PORT MAP (im1, b, im8); g10 : n2 PORT MAP (im1, lt, im9); g11 : n2 PORT MAP (b, lt, im10); g12 : n3 PORT MAP (im8, im9, im10, a_lt_b); END gate_level;
Using package of simple gates in gate_level of bit_comparator This becomes our local declarations Same naming rules as before, same configuration
USE WORK.simple_gates.n1, WORK.simple_gates.n2, WORK.simple_gates.n3; . -- n1, n2 and n3 component declarations are visible .
An alternative application of the use clause Can select only those needed
CHAPTER 6
16
PACKAGE basic_utilities IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME); FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; END basic_utilities;
The basic_utilities package declaration Packaging subprograms replaces their declaration Types and declarations become visible to architectures
CHAPTER 6
17

PACKAGE BODY basic_utilities IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; VARIABLE buf : BIT_VECTOR (bin'RANGE); BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin;
Package body includes body of procedures The basic_utilities package body Will use this package in all our examples
PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0); CONSTANT values : IN integers; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0); BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END to_integer; END basic_utilities;
Continuation of the basic_utilities package body New declarations in this body are visible to this body only
CHAPTER 6
19
USE WORK.basic_utilities.ALL; ARCHITECTURE functional OF bit_comparator IS BEGIN a_gt_b <= fgl (a, b, gt) AFTER 12 NS; a_eq_b <= feq (a, b, eq) AFTER 12 NS; a_lt_b <= fgl (b, a, lt) AFTER 12 NS; END functional;
Using functions of the basic_utilities package Architecture need not include function body The USE statement handles visibility
CHAPTER 6
20
USE WORK.basic_utilities.ALL; ARCHITECTUR procedural OF nibble_comparator_test_bench IS COMPONENT comp4 PORT ( a, b : IN bit_vector (3 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural); SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); apply_data (a, 0&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS); apply_data (b, 0&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS); END procedural;
ALTERNATIVELY: apply_data (a, (00,15,15,14,14,14,14,10,00,15,00,00,15), 500 NS); apply_data (b, (00,14,14,15,15,12,12,12,15,15,15,00,00), 500 NS);

CHAPTER 6
Using procedures of the basic_utilities package Concatenate to form 13 integers Can also use aggregate operation Aggregate for elements of the array only
Design Parametrization
ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN BIT; o1 : OUT BIT); END inv_t; -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2; END average_delay;
Architecture for demonstrating specification and definition of parameters
Start design parameterization examples with same simple structures
CHAPTER 6
22
ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS); PORT (i1, i2 : IN BIT; o1 : OUT BIT); END nand2_t; -ARCHITECTURE average_delay OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2; END average_delay;
ENTITY nand3_t IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT); END nand3_t; -ARCHITECTURE average_delay OF nand3_t IS BEGIN o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2; END average_delay;
Parametrized gate models GENERIC is used, declares objects of type constant

CHAPTER 6
23
ENTITY inv_t IS GENERIC ( tplh : TIME := 5 NS ; tphl : TIME := 3 NS ); PORT (i1 : IN BIT; o1 : OUT BIT); END inv_t;
interface constant declaration
entity declaration
interface constant declaration
(generic) interface list
(formal) generic clause entity header
(formal) port clause
Details of the entity declaration of inverter with generics Using a default value is helpful but not required Generic clause comes before port clause
inv_t i1 tplh o1 tphl
nand2_t i1 o1 i2 tphl tplh
i1 nand3_t o1 i2 i3tplh tphl
Interface aspects of inv_t, nand2_t, and nand3_t Graphical representation with generics Port association and generic association must be done when used
CHAPTER 6
25
ARCHITECTURE default_delay OF bit_comparator IS

COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT;
FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay); FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay); FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay); -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN -- a_gt_b output g0 : n1 PORT MAP (a, im1); g1 : n1 PORT MAP (b, im2); g2 : n2 PORT MAP (a, im2, im3); g3 : n2 PORT MAP (a, gt, im4); g4 : n2 PORT MAP (im2, gt, im5); g5 : n3 PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : n3 PORT MAP (im1, im2, eq, im6); g7 : n3 PORT MAP (a, b, eq, im7); g8 : n2 PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : n2 PORT MAP (im1, b, im8); g10 : n2 PORT MAP (im1, lt, im9); g11 : n2 PORT MAP (b, lt, im10); g12 : n3 PORT MAP (im8, im9, im10, a_lt_b); END default_delay;
Many alternatives for specifying generics Using default values for the generics of logic gates No need to declare and specify generics if they are to use default values
CHAPTER 6
26
ARCHITECTURE fixed_delay OF bit_comparator IS COMPONENT n1 GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 GENERIC (tplh, tphl : TIME); PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay); FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay); FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay); SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN -- a_gt_b output g0 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (a, im1); g1 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (b, im2); g2 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, im2, im3); g3 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, gt, im4); g4 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im2, gt, im5); g5 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im1, im2, eq, im6); g7 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (a, b, eq, im7); g8 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, b, im8); g10 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, lt, im9); g11 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (b, lt, im10); g12 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im8, im9, im10, a_lt_b); END fixed_delay;
If generics are declared without default values, they have to be specified Associating fixed values with the generics of logic gates Generic map is shown here
g1 : n1 GENERIC MAP ( 2 NS, 4 NS ) PORT MAP ( b, im2 ) ;
instantiation_label component_name generic map aspect port map aspect
association_list
component instantiation statement
association_list
Syntax details Component instantiation statement with generic map aspect Generic map aspect comes first
ENTITY bit_comparator_t IS GENERIC (tplh1, tplh2, tplh3, tphl1, tphl2, tphl3 : TIME); PORT (a, b, -- data inputs gt, -- previous greater than eq, -- previous equal lt : IN BIT; -- previous less than a_gt_b, -- greater a_eq_b, -- equal a_lt_b : OUT BIT); -- less than END bit_comparator_t; (a) ARCHITECTURE passed_delay OF bit_comparator_t IS COMPONENT n1 GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n2 GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n3 GENERIC (tplh, tphl : TIME); PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT; FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay); FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay); FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay); -- Intermediate signals SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT; BEGIN ...
A bit comparator with timing parameters Passing generics of bit comparator to its components Bit comparator has generic parameters that must be passed to it
... -- a_gt_b output g0 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (a, im1); g1 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (b, im2); g2 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, im2, im3); g3 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, gt, im4); g4 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im2, gt, im5); g5 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im3, im4, im5, a_gt_b); -- a_eq_b output g6 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im1, im2, eq, im6); g7 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (a, b, eq, im7); g8 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im6, im7, a_eq_b); -- a_lt_b output g9 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, b, im8); g10 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, lt, im9); g11 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (b, lt, im10); g12 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im8, im9, im10, a_lt_b); END passed_delay;
A bit comparator with timing parameters Gates require generic specification These override the gate generics
bit_comparator_t (passed_delay) a nand2_t i1 (average_delay) o1 i2 im3
tplh
tphl
nand2_t i1 i2
(average_delay)
o1
im4
tplh
tphl
nand3_t i1 (average_delay) o1 i2 i3 tplh tphl
a_gt_b
inv_t im2 i1 (average_delay)o1
nand2_t i1 i2
(average_delay)
tplh
tphl
o1
tplh
tphl
im5
gt nand3_t i1 (average_delay) o1 i2 i3 tplh tphl nand3_t i1 (average_delay) i2 o1 i3tplh tphl im6 nand2_t i1 i2 im7
(average_delay)
eq lt
o1
a_eq_b
tplh
tphl
nand2_t i1 i2 inv_t i1 (average_delay)o1

(average_delay)
im8
o1
tplh
tphl
nand3_t i1 (average_delay) o1 i2 i3 tplh tphl a_lt_b
im1 i1 i2
nand2_t
(average_delay)
tplh
tphl
o1
im9
tplh
tphl
nand2_t i1 i2
(average_delay)
o1
tplh tplh2
tphl
im10
tplh1
tphl1
tphl2
tplh3
tphl3
Composition aspect of bit_comparator_t Dotted lines with arrows indicate generics
CHAPTER 6
31
ARCHITECTURE iterative OF nibble_comparator IS COMPONENT comp1 GENERIC (
tplh1 : TIME := 2 NS; tplh2 :TIME := 3 NS; tplh3 : TIME := 4 ns; tplh1 : TIME := 4 NS; tplh2 :TIME := 5 NS; tplh3 : TIME := 6 ns;
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator_t (passed_delay); SIGNAL im : BIT_VECTOR ( 0 TO 8); BEGIN c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP
(a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE; c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b, a_lt_b); END iterative;
Comp1 is declared with default values Passing default values of local generics to the generics of bit_comparator_t These values override at the lower levels
ARCHITECTURE iterative OF nibble_comparator IS ... BEGIN c0: comp1 GENERIC MAP (OPEN, OPEN, 8 NS, OPEN, OPEN, 10 NS) PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); ... END iterative;
Some are associated with OPEN Associating constants with some of generics of bit_comparator_t, and using defaults for others Association by position, correspond in the order they are listed
ARCHITECTURE iterative OF nibble_comparator IS ... BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS) PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); ... END iterative;
SAME FORMAT FOR THE PORTS: PORT AS DECLARED: PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); ARCHITECTURE BECOMES: ARCHITECTURE iterative OF nibble_comparator IS ... BEGIN c0: comp1 GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS) PORT MAP (a => a(0), b => b(0), gt => gt, eq => eq, lt => lt, a_gt_b => im(0), a_eq_b => im(1), a_lt_b => im(2)); ... END iterative;

CHAPTER 6
Using named association, same mapping as before It must be: as_in_declaration => local_value Order is not significant Leave open or use a_gt_b => OPEN Outputs can be left open, inputs only if default
Design Configuration
USE WORK.basic_utilities.ALL; ARCHITECTURE customizable OF nibble_comarator_test_bench IS COMPONENT comp4 PORT ( a, b : IN BIT_VECTOR (3 DOWNTO 0); gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); apply_data (a, (0,15,15,14,14,14,14,10,00,15,00,00,15), 500 NS); apply_data (b, (0,14,14,15,15,12,12,12,15,15,15,00,00), 500 NS); END customizable;
Customizable architecture for demonstrating configuration declarations
A customizable test bench Configuration specification is not included Comp4 is not in our work library
CHAPTER 6
35
USE WORK.ALL; CONFIGURATION functional OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 2 3 USE ENTITY WORK.nibble_comparator(structural); END FOR; END FOR; END functional;
Configuring customizable for testing structural architecture of nibble_comparator Hierarchically enter the architecture, perform binding
CHAPTER 6
36
functional nibble_comparator (structural) nibble_comparator_test_bench (customizable) a1: comp4 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b
Graphical representation Composition aspect for functional configuration declaration, configuring customizable test bench Pass through hierarchies with arrows
USE WORK.ALL; CONFIGURATION average_delay OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(iterative); END FOR; END FOR; END average_delay;
Another configuration on top of the test bench Configuring customizable for testing iterative architecture of nibble_comparator No need to recompile the test bench
CONFIGURATION average_delay OF nibble_ comparator_ test_bench IS FOR customizable FOR al : comp4 USE ENTITY WORK. nibble_comparator (iterative) ; END FOR; END FOR; END average_delay;
identifier
entity_name
configuration declaration
binding indication
component configuration
block configuration
Details of configuration declaration Configuration declaration replaces or adds to a configuration specification Includes component configuration and block configuration
ARCHITECTURE flexible OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL im : BIT_VECTOR ( 0 TO 8); BEGIN c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2)); c1to2: FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b, a_lt_b); END flexible;
A general purpose nibble_comparator This 4-bit comparator does not use a specific bit comparator A top-level configuration configures comp1 instantiations
default_bit_level bit_comparator(default_delay) nibble_comparator(flexible)
nibble_comparator_test_bench (customizable)
a(3:0) b(3:0)
a(3) b(3)
c3: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b a_gt_b a_eq_b a_lt_b
a1: comp4
a(2) b(2)
c2: comp1 a(3:0) b(3:0) gt a_gt_b a_eq_b a_lt_b
c1to2:
im(6) im(7) im(8)
gt
eq lt
eq
lt a(1) b(1)
c1: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(3) im(4) im(5)
a(0) b(0)
c0: comp1 a(3:0) b(3:0) gt eq lt a_gt_b a_eq_b a_lt_b im(0) im(1) im(2)
Composition aspect for configuring customizable test bench for testing default_delay bit_comparator Graphical representation of hierarchies
CHAPTER 6
41
USE WORK.ALL; CONFIGURATION default_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(flexible); FOR flexible FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator (default_delay); END FOR; FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (default_delay); END FOR; END FOR; END FOR; END FOR; END FOR; END default_bit_level;
Configuration declaration for configuring customizable test bench for testing default_delay bit_comparator Binding to the default_delay architecture
CHAPTER 6
42
USE WORK.ALL; CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(flexible); FOR flexible FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator (fixed_delay); END FOR; FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator (fixed_delay); END FOR; END FOR; END FOR; END FOR; END FOR; END fixed_bit_level;
Configuring customizable test bench for testing the fixed_delay architecture of bit_comparator Binding to the fixed_delay architecture Can use ALL or OTHERS
CHAPTER 6
43
passed_bit_level bit_comparator_t(passed_delay) nibble_comparator(flexible)
nibble_comparator_test_bench (customizable)
a(3:0) b(3:0)
a(3) b(3)
tplh1 c3: comp1 tplh2 tplh3 a(3:0)
b(3:0) gt eq lt
tphl1 tphl2 tphl3
a_gt_b a_eq_b a_lt_b
2NS 3NS 4NS 4NS 5NS 6NS
a1: comp4
a(2) b(2)
c2: comp1 tplh1 tplh2 tplh3 a(3:0) b(3:0) gt

tphl1 tphl2 tphl3
im(6) im(7) im(8)
gt
eq lt
eq
lt a(1) b(1)
c1: comp1 a(3:0) b(3:0) gt eq lt
tplh1 tplh2 tplh3 tphl1 tphl2 tphl3
im(3) im(4) im(5)
c1to2:
a(0) b(0)
c0: comp1 a(3:0) b(3:0) gt eq lt
tplh1 tplh2 tplh3 tphl1 tphl2 tphl3
im(0) im(1) im(2)
Composition aspect of the passed_bit_level Configuration for test bench for testing passed_delay architecture of bit_comparator_t
CHAPTER 6
44
USE WORK.ALL; CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS FOR customizable FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(flexible); FOR flexible FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, S tphl2 => 5 NS, tphl3 => 6 NS); Y END FOR; N FOR c1to2 T FOR c: comp1 A USE ENTITY WORK.bit_comparator_t (passed_delay) X GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; END FOR; END FOR; END FOR; END FOR; END passed_bit_level;
Using configuration declarations for component bindings, and specification of generic parameters Same format for generic map and port map aspects as configuration specification
FOR flexible FOR c0, c3: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay) GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; FOR c1to2 FOR c: comp1 USE ENTITY WORK.bit_comparator_t (passed_delay) GENERIC MAP (tphl1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; END FOR; END FOR;
entity aspect component configuration generic map aspect block configuration
component configuration
block configuration
Details of a block configuration enclosing component configurations and other block configurations Binding indication and generic map aspect
CHAPTER 6
46
ARCHITECTURE partially_flexible OF nibble_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator_t (passed_delay); SIGNAL im : BIT_VECTOR ( 0 TO 8 ); BEGIN c0: comp1 PORT MAP ( . . . ); c1to2 : FOR i IN 1 TO 2 GENERATE c: comp1 PORT MAP ( . . . ); END GENERATE; c3: comp1 PORT MAP ( . . . ); END partially_flexible;
Can do incremental binding Do some with configuration specification, and more with configuration declaration This is an illustration for the primary binding indication
USE WORK.ALL; CONFIGURATION incremental OF nibble_comparator_test_bench IS FOR customizable

FOR a1 : comp4 USE ENTITY WORK.nibble_comparator (partially_flexible);
FOR flexible FOR c0, c3: comp1 GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; FOR c1to2 FOR c: comp1 GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS); END FOR; END FOR; END FOR; END FOR; END FOR; END incremental;
Incremental binding indication illustration Add generic map aspect to the existing binding Can use different mappings
CHAPTER 6
48
ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT); END sr_latch; -ARCHITECTURE gate_level OF sr_latch IS COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; SIGNAL im1, im2, im3, im4 : BIT; BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3; END gate_level;
Customizable architecture, using a sequential example, several levels of hierarchy
A new example, illustrating configurations at several levels of depth Unbound VHDL description of set-reset latch Uses the same basic components
ENTITY d_latch IS PORT (d, c : IN BIT; q : OUT BIT); END d_latch; -ARCHITECTURE sr_based OF d_latch IS COMPONENT sr PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT; COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; SIGNAL dbar : BIT; BEGIN c1 : sr PORT MAP (d, dbar, c, q); c2 : n1 PORT MAP (d, dbar); END sr_based;
Building a D-latch Add an inverter to the SR-latch Unbound VHDL description of a D-latch All gate level components are unbound
CHAPTER 6
50
ENTITY d_register IS PORT (d : IN BIT_VECTOR; c : IN BIT; q : OUT BIT_VECTOR); END d_register; -ARCHITECTURE latch_based OF d_register IS COMPONENT dl PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT; BEGIN dr : FOR i IN d'RANGE GENERATE di : dl PORT MAP (d(i), c, q(i)); END GENERATE; END latch_based;
Generically generate a register Unbound VHDL description for an n-bit latch Configuration specification is not included
average_gate_delay d_latch(sr_based)
inv_ t(average_delay)
2 NS
di:
i1 g1: i2 c1:
o1
i1 g3: i2 i1 i2
o1
i1 c2:
o1
i1 g2: i2
o1
g4:
o1
3 NS 5 NS
di:
i1 g1: i2 c1:
o1
i1 g3: i2 i1 g4: i2
o1
i1 c2:
o1
i1 g2: i2
o1
o1
3 NS 5 NS 5 NS 6 NS
di:
i1 g1: i2 c1:
o1
i1 g3: i2 i1 i2
o1
i1 c2:
o1
i1 g2: i2
o1
g4:
o1
3 NS 5 NS 5 NS 6 NS
nand2_t(average_delay)
di:
i1 i2
g1: c1:
o1
i1 g3: i2 i1 i2
o1
i1 c2:
o1
i1 g2: i2
o1
g4:
o1
3 NS 5 NS
Composition aspect for configuring the latch_based architecture of d_register Hierarchical configuration
Sr_latch (gate_level)
4 NS
5 NS 6 NS
2 NS 4 NS
2 NS 4 NS
2 NS 4 NS
5 NS 6 NS
USE WORK.ALL; CONFIGURATION average_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.d_latch(sr_based); FOR sr_based FOR c1 : sr USE ENTITY WORK.sr_latch(gate_level); FOR gate_level FOR g2, g4 : n2 USE ENTITY WORK.nand2_t(average_delay) 9 GENERIC MAP (5 NS, 6 NS); END FOR; FOR g1, g3 : n2 2 3 4 5 6 8 USE ENTITY WORK.nand2_t(average_delay) 10 GENERIC MAP (2 NS, 4 NS); END FOR; END FOR; END FOR; FOR c2 : n1 USE ENTITY WORK.inv_t(average_delay) 7 GENERIC MAP (3 NS, 5 NS); END FOR; END FOR; END FOR; END FOR; END FOR; END average_gate_delay;
Configuring d_register for using average_delay gates
CHAPTER 6
53
Block No. 1
Configuration Type Configuration Declaration Block Configuration Block Configuration Component Configuration Block Configuration Component Configuration Component Configuration Block Configuration Component Configuration Component Configuration
PURPOSE Visibility or Binding to: Main latch_based ARCHITECTURE Figure 6.46 dr GENERATE STATEMENT Figure 6.46 di instance of dl Figure 6.46 sr_based ARCHITECTURE Figure 6.45 c1 instance of sr Figure 6.45 c2 instance of sr Figure 6.45 gate_level ARCHITECTURE Figure 6.44 instances g2, g4 of n2 Figure 6.44 instances g1, g3 of n2 Figure 6.44
Becomes Visible by: -
Visibility
Visibility
1, 2
Binding
1, 2, 3
Visibility
1, 2, 3, 4
Binding
1, 2, 3, 4, 5
Binding
1, 2, 3, 4, 5
Visibility
1, 2, 3, 4, 5, 6
Binding
1, 2, 3, 4, 5, 6, 8
10
Binding
1, 2, 3, 4, 5, 6, 8
Analyzing configuration constructs of the average_gate_delay configuration of d_register Configuration declaration includes component configurations and block configurations
USE WORK.ALL; CONFIGURATION single_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.d_latch(sr_based); FOR sr_based FOR c1 : sr USE ENTITY WORK.sr_latch(gate_level); FOR gate_level FOR g2, g4 : n2 USE ENTITY WORK.nand3(single_delay) PORT MAP (i1, i1, i2, o1); END FOR; FOR g1, g3 : n2 USE ENTITY WORK.nand2(single_delay); END FOR; END FOR; END FOR; FOR c2 : n1 USE ENTITY WORK.inv(single_delay); END FOR; END FOR; END FOR; END FOR; END FOR; END single_gate_delay;
Configuring d_register for using single_delay architectures of inv and nand2 Deep inside to reach basic gates and their generic parameters
ARCHITECTURE single OF d_register_test_bench IS COMPONENT reg PORT (d : IN BIT_VECTOR (7 DOWNTO 0); c : IN BIT; q : OUT BIT_VECTOR (7 DOWNTO 0) ); END COMPONENT; FOR r8 : reg USE CONFIGURATION WORK.single_gate_delay; SIGNAL data, outdata : BIT_VECTOR (7 DOWNTO 0); SIGNAL clk : BIT; BEGIN r8: reg PORT MAP (data, clk, outdata); data <= X"00", X"AA" AFTER 0500 NS, X"55" AFTER 1500 NS; clk <= '0', '1' AFTER 0200 NS, '0' AFTER 0300 NS, '1' AFTER 0700 NS, '0' AFTER 0800 NS, '1' AFTER 1700 NS, '0' AFTER 1800 NS; END single;
Demonstrating the use of configurations in configuration specifications Test bench for the single_delay architecture of d_register
a(0) im(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) im(1) im(2) im(3) im(4) im(5) im(6) odd even
One more configuration declaration example, iterative hardware
The final example Will illustrate indexing for alternative binding Parity generator/checker circuit
CHAPTER 6
57
ENTITY xor2_t IS GENERIC (tplh : TIME := 9 NS; tphl : TIME := 7 NS); PORT (i1, i2 : IN BIT; o1 : OUT BIT); END xor2_t; -ARCHITECTURE average_delay OF xor2_t IS BEGIN o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2; END average_delay; ---ENTITY inv_t IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN BIT; o1 : OUT BIT); END inv_t; -ARCHITECTURE average_delay OF inv_t IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2; END average_delay;
Components needed for this design Timed XOR and INV gates needed for the design of the parity circuit
CHAPTER 6
58
ENTITY parity IS PORT (a : IN BIT_VECTOR (7 DOWNTO 0); odd, even : OUT BIT); END parity; -ARCHITECTURE iterative OF parity IS COMPONENT x2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT; COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT; SIGNAL im : BIT_VECTOR ( 0 TO 6 ); BEGIN first: x2 PORT MAP (a(0), a(1), im(0)); middle: FOR i IN 1 TO 6 GENERATE m: x2 PORT MAP (im(i-1), a(i+1), im(i)); END GENERATE; last: odd <= im(6); inv: n1 PORT MAP (im(6), even); END iterative;
Parity circuit description No configuration specification for the inverter and the exclusive OR gate
CHAPTER 6
59
CONFIGURATION parity_binding OF parity IS FOR iterative FOR first : x2 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (5 NS, 5 NS); END FOR; FOR middle (1 TO 5) FOR m : x2 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (5 NS, 5 NS); END FOR; END FOR; FOR middle ( 6) FOR m : x2 USE ENTITY WORK.xor2_t (average_delay) GENERIC MAP (6 NS, 7 NS); END FOR; END FOR; FOR inv : n1 USE ENTITY WORK.inv_t (average_delay) GENERIC MAP (5 NS, 5 NS); END FOR; END FOR; END parity_binding;
Parity circuit configuration declaration Index label of the generate statement Can use OTHERS, pick some, and OTHERS the rest
CHAPTER 6
60
Use of Libraries
Value 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-'
Representing Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 Don't care
Standard and user libraries, start with the nine-value standard logic
None standard values Std_logic logic value system Satisfies most hardware design needs
CHAPTER 6
61
Use of Libraries
. U X 0 1 Z W L H -
U 'U' 'U' '0' 'U' 'U' 'U' '0' 'U' 'U'
X 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X'
0 '0' '0' '0' '0' '0' '0' '0' '0' '0'
1 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X'
Z 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X'
W 'U' 'X' '0' 'X' 'X' 'X' '0' 'X' 'X'
L '0' '0' '0' '0' '0' '0' '0' '0' '0'
H 'U' 'X' '0' '1' 'X' 'X' '0' '1' 'X'
'U 'X' '0' 'X 'X' 'X' '0' 'X' 'X'
AND table for std_logic type All logic tables are defined and available Changing BIT to std_logic works in most cases
Use of Libraries
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -ENTITY nand2_t IS GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS); PORT (i1, i2 : IN std_logic; o1 : OUT std_logic); END nand2_t; -ARCHITECTURE average_delay_mvla OF nand2_t IS BEGIN o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2; END average_delay_mvla;
A two-input NAND gate in std_logic value system Specify library and package All basic functions are available in this package
Use of Libraries
LIBRARY ls7400 simple_gates inv inv(single_delay) nand2 nand2(single_delay) nand3 nand3(single_delay)
User: John Designer PACKAGE DECLARATION ENTITY ARCHITECTURE ENTITY ARCHITECTURE ENTITY ARCHITECTURE
Date June 9, 1997 June 8, 1997 June 8, 1997 June 6, 1997 June 6, 1997 June 6, 1997 June 6, 1997
Other libraries Can define our own Directory of ls7400 library containing package declarations, entities and architectures
Use of Libraries
WORK is the default library, STD is the standard library that includes the STANDARD and TEXTIO packages All other libraries and packages must be explicitly specified Use ls7400 as a user defined library
LIBRARY ls7400; USE ls7400.simple_gates.ALL;
Visibility of user libraries and packages Making all declarations of simple_gates package of ls7400 library available
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65
Use of Libraries
LIBRARY ls7400; USE ls7400.simple_gates.ALL; -ARCHITECTURE gate_level OF sr_latch IS SIGNAL im1, im2, im3, im4 : BIT; BEGIN g1 : n2 PORT MAP (s, c, im1); g2 : n2 PORT MAP (r, c, im2); g3 : n2 PORT MAP (im1, im4, im3); g4 : n2 PORT MAP (im3, im2, im4); q <= im3; END gate_level;
Using user libraries Using component declarations of simple_gates package of ls7400 library for description of set-reset latch
Use of Libraries
LIBRARY ls7400; USE ls7400.ALL;
Visibility into libraries Making all entities and architectures of the ls7400 library available
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67
Use of Libraries
LIBRARY ls7400; USE ls7400.ALL; . . FOR g1, g3 : n2 USE ENTITY ls7400.nand2 (single_delay); END FOR;
Binding indication needs library name Using a component configuration for associating g1 and g3 instances of n2 of Figure 661 with nand2 of ls7400
Summary
This chapter provides tools for better hardware
descriptions and design organization. We began with the definition of subprograms and emphasized on the use of functions and procedures for simplifying descriptions. Next, the subject of packaging utilities and components was addressed. As stated earlier, this topic is used mainly for the organization of a design. Design parameterization and configuration of designs were also discussed in great detail. Although simple examples and college level exercises can avoid some of these language issues, a large design environment with many logic families and technologies to choose from requires a great deal of library management and parameter specification. We believe VHDL is very
strong in this area and serious designers should learn to take advantage of such capabilities of the language. For small circuits and experimental models, design
parameterization methods save many compilation runs.
End Of Chapter 6
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69
CHAPTER 7 UTILITIES FOR HIGH LEVEL DESCRIPTIONS

7.1 TYPE DECLARATIONS AND USAGE 7.1.1 Enumeration Type for Multi-Value Logic 7.1.2 Using Real Numbers For Timing Calculations 7.1.3 Physical Types and RC Timing 7.1.4 Array Declarations 7.1.5 File Type and External File I/O 7.2 VHDL OPERATORS 7.2.1 Logical Operators 7.2.2 Relational Operators 7.2.3 Shift Operators 7.2.4 Adding Operators 7.2.5 Sign Operators 7.2.6 Multiplying Operators 7.2.7 Nota Operators 7.2.8 Aggregate Operation 7.3 SUBPROGRAM PARAMETER TYPES AND OVERLOADING 7.4 OTHER TYPES AND TYPE RELATED ISSUES 7.4.1 Subtypes 7.4.2 Record Types 7.4.3 Alias Declaration 7.4.4 Access Types 7.4.5. Global Objects 7.4.6 Type Conversions 7.5 PREDEFINED ATTRIBUTES 7.5.1 Array Attributes 7.5.2 Type Attributes 7.5.3 Signal Attributes 7.5.4 Entity Attributes 7.6 USER-DEFINED ATTRIBUTES 7.7 PACKAGING BASIC UTILITIES 7.8 SUMMARY
CHAPTER 7
TYPE DECLARATIONS AND USAGE
TYPE qit IS ('0', '1', 'Z', 'X');

initial
TYPE qit IS ( 0 , 1 , Z , X ) ;
identifier
enumeration element enumeration element enumeration element enumeration element enumeration type definition type definition type declaration
Will use an enumeration type for demonstrating type declarations
4-value qit type will be used Enumeration type declaration Initial value of objects of this type is the left-most enumeration element of the base type
CHAPTER 7
In:
0 1 Z X
1 0 0 X Out
Will develop basic logic gates based on this type Input-Output mapping of an inverter in qit logic value system
CHAPTER 7
USE WORK.basic_utilities.ALL; -- From PACKAGE USE : qit ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN qit; o1 : OUT qit); END inv_q; -ARCHITECTURE double_delay OF inv_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh; END double_delay;
VHDL description of an inverter in qit logic value system Inputs and outputs are of type qit Assumes out package contains this type definition
CHAPTER 7
Z <= a AFTER 5 NS WHEN d = 1 ELSE UNAFFECTED WHEN e = 1 ELSE b AFTER 5 NS WHEN f = 1 ELSE c AFTER 5 NS;
o1<= 1 AFTER tplh WHEN i1 = 0 ELSE 0 AFTER tphl WHEN i1 = 1 OR i1 = Z ELSE UNAFFECTED;
o1 <= a WHEN cond =1 ELSE o1; or o1 <= a WHEN cond =1 ELSE UNAFFECTED;
A new construct is presented This is conditional signal assignment Several alternatives exist in its usage Can use unaffected for assignments to outputs
CHAPTER 7
o1 <= 1 AFTER tplh WHEN i1 = 0 ELSE 0 AFTER tphl WHEN i1 = 1 OR i1 = Z ELSE X AFTER tplh ;
target waveform condition waveform condition waveform condition waveform conditional signal assignment
Syntax details of a conditional signal assignment Condition waveform has a series of waveforms with or without condition
CHAPTER 7
In1: In2: 0 1 Z X
0 1 1 1 1
1 1 0 0 X Out
Z 1 0 0 X 1
X X X
We will develop more basic structures in this 4-value logic system Input-Output mapping of a NAND gate in qit logic value system Here we assume 1 for high impedance
CHAPTER 7
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE : qit ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2 : IN qit; o1 : OUT qit); END nand2_q; -ARCHITECTURE double_delay OF nand2_q IS BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' OR i2 = '0' ELSE '0' AFTER tphl WHEN (i1 = '1' AND i2 = '1') OR (i1 = '1' AND i2 = 'Z') OR (i1 = 'Z' AND i2 = '1') OR (i1 = 'Z' AND i2 = 'Z') ELSE 'X' AFTER tplh; -- Can Use: UNAFFECTED; END double_delay;
VHDL description of a NAND gate in qit logic system A conditional signal assignment is used This is a concurrent statement Conditions are checked sequentially from left to right
CHAPTER 7
inv_rc(double_delay) c_load 25K
i1 15K
o1
A CMOS inverter example for demonstrating floating point and physical types
Composition aspect of an inverter with RC timing Timing depends on the R and C values Exponential timing is 3RC Will first demonstrate floating point numbers
CHAPTER 7
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY inv_rc IS GENERIC (c_load : REAL := 0.066E-12); -- Farads PORT (i1 : IN qit; o1 : OUT qit); CONSTANT rpu : REAL := 25000.0; -- Ohms CONSTANT rpd : REAL := 15000.0; -- Ohms END inv_rc; -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := INTEGER ( rpu * c_load * 1.0E15) * 3 FS; CONSTANT tphl : TIME := INTEGER ( rpd * c_load * 1.0E15) * 3 FS; BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh; END double_delay;
An inverter model with RC timing parameters Delay cannot be a fraction of FS Delay values are calculated based on pull-up, oull-down and load capacitance Constant values are used in the conditional signal assignment
TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS;
Type definition for defining the capacitance physical type Use physical types instead of floating point Base unit must be there All others are then defined
CHAPTER 7
11
TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS;
Type definition for defining the resistance physical type Another physical type RANGE specifies the largest value in terms of base units that an object of this type can get Intermediate values can take larger values
CHAPTER 7
12
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, resistance, capacitance ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr); PORT (i1 : IN qit; o1 : OUT qit); CONSTANT rpu : resistance := 25000 ohms; CONSTANT rpd : resistance := 15000 ohms; END inv_rc; -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := (rpu / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000; CONSTANT tphl : TIME := (rpd / 1 l_o) * (c_load / 1 ffr) * 3 FS / 1000; BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh; END double_delay;
Using resistance and capacitance physical types in the description of an inverter Resolutions of Millie-ohms and Femto-farads are taken into account Divide by 1000 adjusts the time units to FS Will do it with a better style later

TYPE qit_nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit;
TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit;
TYPE qit_word IS ARRAY ( 15 DOWNTO 0 ) OF qit;
TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0, 0 TO 7 ) OF qit;
TYPE qit_nibble_by_8 IS ARRAY ( 0 TO 7 ) OF qit_nibble;
Demonstrating array definition and object declaration
Declaring array types Arrays may be ascending or descending Objects can be indexed as declared n-dimensional arrays may be declared
CHAPTER 7
14
TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit ;
identifier
range
discrete range
index constrained
constraint array definition
type declaration
element_subtype_indication
Syntax details of an array type declaration This is a type declaration Contains constraint array definition
CHAPTER 7
15
SIGNAL sq8 : qit_byte := "ZZZZZZZZ";
SIGNAL sq8 : qit_byte := (Z, Z, Z, Z, 1, 1, 1, 1);
SIGNAL sq8 : qit_byte := (5 => Z, OTHERS => 1);
SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => Z, OTHERS => 1);
SIGNAL sq8 : qit_byte := (1 DOWN TO 0 => Z, 3 TO 4 => X, OTHERS => 1);
Objects of array type may be initialized when declared If explicit initialization is missing, all elements are initialized to left-most of array element Can form a vector of initial values Can use aggregate operation, association by position Can use aggregate operation, association by name
Signal Declarations:
SIGNAL sq1 : qit; SIGNAL sq4 : qit_nibble; SIGNAL sq8 : qit_byte; SIGNAL sq16 : qit_word; SIGNAL sq_4_8 : qit_4by_8; SIGNAL sq_nibble_8 : qit_nibble_by_8;
Valid Operations:
sq8 <= sq16 (11 DOWNTO 4); -- middle 8 bit slice of sq16 to sq8; sq16 (15 DOWNTO 12) <= sq4; -- sq4 into left 4 bit slice of sq16; sq1 <= sq_4_8 (0, 7); -- lower right bit of sq_4_8 into sq1; sq4 <= sq_nibble_8 (2); -- third nibble (number 2) of sq_nibble_8 into sq4; sq1 <= sq_nibble_8(2)(3); -- nibble 2, bit 3 of sq_nibble_8 into sq1; sq8 <= sq8(0) & sq8 (7 DOWNTO 1); -- right rotate sq8; sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5); -- reversing sq8 into sq4; sq4 <= (sq8(2), sq8(3), sq8(4), sq8(5)); -- reversing sq8 into sq4; (sq4(0), sq4(1), sq4(2), sq4(3)) <= sq8 (5 DOWNTO 2);-- reversing sq8 into sq4;
Signal declarations and signal assignments Arrays may be sliced and used on RHS or LHS Aggregate may be used on RHS and LHS Can concatenate any length or slice size Aggregates operation works with array elements only
CHAPTER 7
17
Concatenation example:
sq4: 3 2 1 0
sq8: 7 6 5 4 3 2 1 0
sq4 <= sq8(2) & sq8(3) & sq8(4) & sq8(5);
Slice example:
sq_nibble_8(2)(3 DOWN To 2)
Referencing bits of a vector; reversing bits of sq8 and assigning them to sq4 Cannot index opposite to what the type is defined as. Nice try! An slicing example is also shown here
CHAPTER 7
18
SIGNAL sq_4_8 : qit_4by8 := ( ( '0', '0', '1', '1', 'Z', 'Z', 'X', 'X' ), ( 'X', 'X', '0', '0', '1', '1', 'Z', 'Z' ), ( 'Z', 'Z', 'X', 'X', '0', '0', '1', '1' ), ( '1', '1', 'Z', 'Z', 'X', 'X', '0', '0' ) ); SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := SIGNAL sq_4_8 : qit_4by8 := (OTHERS => 11000000); (OTHERS => (OTHERS => Z)); (OTHERS => (0 TO 1 => 1, OTHERS =>0)); (OTHERS => (0 TO 1 => 1, OTHERS =>0));
:= (OTHERS => (OTHERS => 0))
sq_4_8 <= ( 3 => (OTHERS => X), 0 => (OTHERS => X), OTHERS => (0 => X, 7 => X, OTHERS =>1);
Initializing or assignment to a two dimensional array Right most index applies to deepest set of parenthesis Can initialize the same way as signal and variable assignment Constants must have static values
TYPE qit_2d IS ARRAY (qit, qit) OF qit;
CONSTANT qit_nand2_table : qit_2d := ( 0 => (OTHERS => 1), X => (0 => 1, OTHERS => X), OTHERS => (0 => 1, X => 1, OTHERS =>0));
Demonstrating non-integer RANGE and index specification
Instead of integers, can use other types for array range specification Then an object of this type may be indexed by enumeration elements of the type in the array range specification
CHAPTER 7
20
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, qit_2d ENTITY nand2_q IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2 : IN qit; o1 : OUT qit); END nand2_q; -ARCHITECTURE average_delay OF nand2_q IS CONSTANT qit_nand2_table : qit_2d := ( ('1','1','1','1'), ('1','0','0','X'), ('1','0','0','X'), ('1','X','X','X')); BEGIN o1 <= qit_nand2_table (i1, i2) AFTER (tplh + tphl) / 2; END average_delay;
Using qit enumeration type for the discrete range of a two-dimensional array The constant table is an array qit qit if qit elements
CHAPTER 7
21
TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT; TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF CHARACTER;
TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
Unconstrained array declarations, usage and definition
BIT_VECTOR is a predefined unconstrained array of BITs STRING is that of CHARACTERS Can define our own This is read as RANGE Box
TYPE integer_vector IS ARRAY ( NATURAL RANGE <> ) OF INTEGER ;
identifier
type_mark index_subtype definition unconstrained array definition
type declaration
element_subtype_indication
Syntax details of an unconstrained array declaration We will use this array in our basic utilities Cannot have unconstrained array of an unconstrained array; Nice try!
CHAPTER 7
23
PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;
A generic version of the apply_data procedure Uses our own integer_vector from basic_utilities Procedure output, target, is also unconstrained All will be known when procedure is called
CHAPTER 7
24
ENTITY n_bit_comparator IS PORT (a, b : IN BIT_VECTOR; gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END n_bit_comparator; -ARCHITECTURE structural OF n_bit_comparator IS COMPONENT comp1 PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional); CONSTANT n : INTEGER := a'LENGTH; SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1); BEGIN
c_all: FOR i IN 0 TO n-1 GENERATE l: IF i = 0 GENERATE least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) ); END GENERATE; m: IF i = n-1 GENERATE most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b); END GENERATE; r: IF i > 0 AND i < n-1 GENERATE rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) ); END GENERATE; END GENERATE;
END structural;
Keeping our promise of a better n-bit comparator An n-bit comparator Wiring n number of one-bit comparators The integer n depends on the size of a
CHAPTER 7
25
ENTITY n_bit_comparator_test_bench IS END n_bit_comparator_test_bench ; -USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: apply_data which uses integer_vector ARCHITECTURE procedural OF n_bit_comparator_test_bench IS COMPONENT comp_n PORT (a, b : IN bit_vector; gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT); END COMPONENT; FOR a1 : comp_n USE ENTITY WORK.n_bit_comparator(structural); SIGNAL a, b : BIT_VECTOR (5 DOWNTO 0); SIGNAL eql, lss, gtr : BIT; SIGNAL vdd : BIT := '1'; SIGNAL gnd : BIT := '0'; BEGIN a1: comp_n PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss); apply_data (a, 00&15&57&17, 500 NS); apply_data (b, 00&43&14&45&11&21&44&11, 500 NS); END procedural;
Using generic apply_data procedure for testing n_bit_comparator All unconstrained arrays are fixed according to the parameters passed to them Can use different size integer vectors
CHAPTER 7
26
First, the file has to be declared as what goes into a file

TYPE logic_data IS FILE OF CHARACTER;
Then a logical file name must be declared

FILE input_logic_value_file1: logic_data; --Just declare a logical file
FILE input_logic_value_file2: logic_data IS input.dat; --Declare a logical file and open in READ_MODE
FILE input_logic_value_file3: logic_data OPEN READ_MODE IS input.dat; --Declare a logical file and open with the specified mode
Primitive utilities for file declaration and file specification
input_logic_value_file: logical name for file of logic_data type An explicit OPEN statement must be used for opening Can open a file in READ_MODE, WRITE_MODE or APPEND_MODE
CHAPTER 7
27
First, the file has to be declared as what goes into a file

TYPE logic_data IS FILE OF CHARACTER;
Then a logical file name must be declared

FILE output_logic_value_file1: logic_data; --Just declare a logical file, open later
FILE output_logic_value_file2: logic_data OPEN WRITE_MODE IS input.dat; --Declare a logical file and open with the specified mode
OUPUT FILE : WRITE_MODE or APPEND MODE
An explicit OPEN statement must be used for opening the file in the first alternative Can open a file in READ_MODE, WRITE_MODE or APPEND_MODE
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An explicit OPEN is needed if file is not implicitly opened

FILE_OPEN (input_logic_value_file, input.dat, READ_MODE); FILE_OPEN (output_logic_value_file, output.dat, WRITE_MODE); FILE_OPEN (parameter_of_type_FILE_OPEN_STATUS, output_logic_value_file, output.dat, WRITE_MODE);
The standard package includes:

TYPE FILE_OPEN_STATUS IS (OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR)
Closing a file:
FILE_CLOSE (input_logic_value_file); FILE_CLOSE (output_logic_value_file);
File open alternatives Status parameter must be declared first Close a file using its logical name
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PROCEDURE assign_bits (
SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS
VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP; END assign_bits;
Calling this procedure: assign_bits (a_signal, "unix_file.bit", 1500 NS);
file_name is a string input containing physical file name A procedure for reading characters from a file and assigning them to a BIT type File type is declared in the procedure En explicit open statement is used
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Declare in an architecture: FILE input_value_file: logic_data IS my_file.bit;
Call the pocedure: read_from_file (SIGNAL target : OUT BIT, this_file : IN FILE);
In the previous example, when assign_bits is called, it reads the entire unix_file.bit Each time reading begins from the top of the file, because a new file object is declared each time it is called To avoid, declare a file object outside of the procedure
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VHDL OPERATORS
Logical Operators: AND, OR, NAND, NOR, XOR, XNOR, NOT
Examples of use: x <= a XNOR b; x_vector <= a_vector AND b_vector;
x <= XOR (a, b); x_vector <= AND (a_vector, b_vector);
Outlining VHDL operators and their format of use
Logical operators Order of operand must remain the same The second format makes operands appear as functions
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VHDL OPERATORS
Relational operators: =, /=, <, <=, >, >=
Examples of use: a_boolean <= i1 > i2; b_boolean <= i1 /= i2;
--if a_bit_vector is 00011 and b_bit_vector is 00100 a_bit_vector < b_bit_vector returns TRUE
--for qitt: 0 is less than 1, and X is larger all the rest --for BIT: 1 is greater than 0
= and /= operate on operands of any type (<, <=, >, and >=) when used with array operands perform ordering operations These return TRUE or FALSE based on values of array elements starting from the left
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VHDL OPERATORS
SLL SLA SRL SRA ROL ROR
Shift/Rotate Shift Shift Shift Shift Rotate Rotate
Left/Right Left Left Right Right Left Right
Logical/Arithmetic Logical Arithmetic Logical Arithmetic Logical Logical
VHDL operators are formally presented in the next few slides
Shift operators operand SIFT_OPERATOR number_of_shifts fill value is the left-most enumeration element
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VHDL OPERATORS
Start with aq aq SLL 1 aq SLA 1 aq SRL 1 aq SRA 1 aq ROL 1 aq ROR 1
Z 0 0 0 Z 0 X
0 1 1 Z Z 1 Z
1 X X 0 0 X 0
X Z Z 1 1 Z 1
Z 1 1 X X 1 X
1 0 0 Z Z 0 Z
0 X X 1 1 X 1
X 0 X 0 0 Z 0
Application of shift operators The result must be placed in a LHS Left operand remains unchanged
CHAPTER 7
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VHDL OPERATORS
Adding operators: +, -, & Multiplying operators: *, /, MOD, REM Other operators: (), **, ABS
Examples of use: a+b + (a, b) a_int MOD b_int -- both integers a_int REM b_int -- returns remainder of absolute value division (a, b, c) aggregate, like concatenation, but allows only elements
Adding, multiplying, aggregate and other operators Format of use is shown for each operator
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36
SUBPROGRAM PARAMETER TYPES AND OVERLOADING

a: b: 0 1 Z X 0 0 0 0 0 1 0 1 1 X z = a.b (a) a: b: 0 1 Z X 0 0 1 1 X 1 1 1 1 1 Z 1 1 1 1 X X 1 1 X Z 0 1 1 X 0 X X X X
z=a+b (b)
a:
0 1 Z X
1 0 0 X z = a'
Demonstrating overloading VHDL operators and subprograms
(c)
Want to use AND, OR, and NOT for qit as easily as for BIT Tables for the basic logic functions in the qit four value logic system
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TYPE qit IS ('0', '1', 'Z', 'X'); TYPE qit_2d IS ARRAY (qit, qit) OF qit; TYPE qit_1d IS ARRAY (qit) OF qit; --
FUNCTION "AND" (a, b : qit) RETURN qit; FUNCTION "OR" (a, b : qit) RETURN qit; FUNCTION "NOT" (a : qit) RETURN qit;
In a package declare qit and arrays based on this type Declare functions to be overloaded Overloading: identify a function with its operands and name
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FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND";
FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR";
FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT";
Overloading basic logical functions for the qit four value logic system Definition of functions
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USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "NOT" ENTITY inv_q IS GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS); PORT (i1 : IN qit; o1 : OUT qit); END inv_q; -ARCHITECTURE average_delay OF inv_q IS BEGIN o1 <= NOT i1 AFTER (tplh + tphl) / 2; END average_delay;
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand2_q IS GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS); PORT (i1, i2 : IN qit; o1 : OUT qit); END nand2_q; -ARCHITECTURE average_delay OF nand2_q IS BEGIN o1 <= NOT ( i1 AND i2 ) AFTER (tplh + tphl) / 2; END average_delay;
Using overloaded operators Cannot use NAND since it is only defined for BIT
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USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand3_q IS GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS); PORT (i1, i2, i3 : IN qit; o1 : OUT qit); END nand3_q; -ARCHITECTURE average_delay OF nand3_q IS BEGIN o1 <= NOT ( i1 AND i2 AND i3) AFTER (tplh + tphl) / 2; END average_delay;
Basic gates in the qit logic value system using overloaded AND operators Can also overload NAND and other operators Std_logic has done this for its types
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In the declaration: FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME;
In a package body: FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*";
Overloading the multiplication operator Returns TIME when multiplying resistance capacitance physical types Function declaration, the "*" subprogram body
and
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USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, capacitance, resistance, "*" ENTITY inv_rc IS GENERIC (c_load : capacitance := 66 ffr); PORT (i1 : IN qit; o1 : OUT qit); CONSTANT rpu : resistance := 25 k_o; CONSTANT rpd : resistance := 15 k_o; END inv_rc; -ARCHITECTURE double_delay OF inv_rc IS CONSTANT tplh : TIME := rpu * c_load * 3; CONSTANT tphl : TIME := rpd * c_load * 3; BEGIN o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE '0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE 'X' AFTER tplh; END double_delay;
Using the overloaded multiplication operator The double_delay architecture of inv_rc
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TYPE qit IS ('0', '1', 'Z', 'X'); TYPE logic_data IS FILE OF CHARACTER; PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME);
PROCEDURE assign_bits (
SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS
VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits;
Overloading the assign_bits procedure for accepting and producing qit data Procedure and other necessary declarations Subprogram body uses a case statement
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CASE char IS WHEN 0 => target <= TRANSPORT 0 AFTER current; WHEN 1 => target <= TRANSPORT 1 AFTER current; WHEN Z z => target <= TRANSPORT Z AFTER current; WHEN X x => target <= TRANSPORT X AFTER current; WHEN OTHERS => current := current period; END CASE; sequence_of statements case_statement alternative expression
choice case_statement alternative sequence_of statements
sequence_of statements choices
case_statement alternative
case_statement alternative sequence_of statements
choice sequence_of statements
case_statement alternative
Syntax details of a sequential case statement Consists of several case alternatives All choices must be filled
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USE WORK.basic_utilities.ALL; -- FROM PACKAGE: qit, capacitance, resistance, assign_bits ENTITY tester IS END tester; -ARCHITECTURE input_output OF tester IS COMPONENT inv GENERIC (c_load : capacitance := 11 ffr); PORT (i1 : IN qit; o1 : OUT qit); END COMPONENT; FOR ALL : inv USE ENTITY WORK.inv_rc(double_delay); SIGNAL a, z : qit; BEGIN assign_bits (a, "data.qit", 500 NS); i1 : inv PORT MAP (a, z); END input_output;
Calling the overloaded assign_bits for testing an inverter The inverter with RC delay is being tested Type qit operand of the procedure causes the new assign_bits to be called
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OTHER TYPES AND RELATED ISSUES
SUBTYPE compatible_nibble_bits IS BIT_VECTOR ( 3 DOWNTO 0);
TYPE nibble_bits IS ARRAY ( 3 DOWNTO 0 ) OF BIT;
SUBTYPE ten_value_logic IS INTEGER RANGE 0 TO 9;
SUBTYPE rit IS qit RANGE '0' TO 'Z'; SUBTYPE bin IS qit RANGE '0' TO '1';
Other type related issues, subtypes, records, and aliases are discussed
Subtypes are used for compatibility Base type of a subtype is the original type nibble_bits is not compatible with any BIT_VECTOR rit and bin are fully compatible with qit
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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
opcode
mode
address
Instruction format
TYPE opcode IS (sta, lda, add, sub, and, nop, jmp, jsr); TYPE mode IS RANGE 0 TO 3; TYPE address IS BIT_VECTOR (10 DOWNTO 0);
TYPE instruction_format IS RECORD opc : opcode; mde : mode; adr : address; END RECORD;
SIGNAL instr : instruction_format := (nop, 0, "00000000000");
instr.opc <= lda; instr.mde <= 2; instr.adr <= "00011110000";
instr <= (adr => (OTHERS => 1), mde => 2, opc => sub)
Record Type Three fields of an instruction Declaration of instruction format A signal of record type Referencing fields of a record type signal Record aggregate
48 1999, Z. Navabi and McGraw-Hill Inc.
CHAPTER 7
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
opcode
mode
page
address
offset
ALIAS page : BIT_VECTOR (2 DOWNTO 0) IS instr.adr (10 DOWNTO 8); ALIAS offset : BIT_VECTOR (7 DOWNTO 0) IS instr.adr (7 DOWNTO 0);
page <= "001"; offset <= X"F1";
Alias declaration, page and offset addresses Alias declaration for the page and offset parts of the address Assignments to page and offset parts of address
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head
link
node
data link
node
data link
node
data
NULL
data Integer Type
link Pointer Type
TYPE node; TYPE pointer IS ACCESS node; TYPE node IS RECORD data : INTEGER; link : pointer; END RECORD;
ACCESS type and implementation and usage of linked lists is demonstrated
Linked list graphical representation Definition in VHDL starts with an incomplete type definition
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Declaration of head as the head of a linked list to be created: VARIABLE head : pointer := NULL;
Assigning the first node to head. head := NEW node;
Linking the next node: head.link := NEW node;
Using the above linked list Declaring head and linking to it
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PROCEDURE lineup (VARIABLE head : INOUT pointer; int : integer_vector) IS VARIABLE t1 : pointer; BEGIN -- Insert data in the linked list head := NEW node; t1 := head; FOR i IN int'RANGE LOOP t1.data := int(i); IF i = int'RIGHT THEN t1.link := NULL; ELSE t1.link := NEW node; t1 := t1.link; END IF; END LOOP; END lineup;
Declare mem:
VARIABLE mem, cache : pointer := NULL;
Inserting integers into the mem linked list: lineup (mem, (25, 12, 17, 18, 19, 20));
Creating a linked list and entering data into it Head is returned as the first node of the linked list A new node of type node is obtained and assigned to head Fields of node are accessed and data is entered into them
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PROCEDURE remove (VARIABLE head : INOUT pointer; v : IN INTEGER) IS VARIABLE t1, t2 : pointer; BEGIN -- Remove node following that with value v t1 := head; WHILE t1 /= NULL LOOP IF t1.data = v THEN t2 := t1.link; t1.link := t2.link; DEALLOCATE (t2); END IF; t1 := t1.link; END LOOP; END remove;
Removing an item from a linked list The head of the linked list is passed Node that follows node with value v is removed
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PROCEDURE clear (VARIABLE head : INOUT pointer) IS VARIABLE t1, t2 : pointer; BEGIN -- Free all the linked list t1 := head; head := NULL; WHILE t1 /= NULL LOOP t2 := t1; t1 := t1.link; DEALLOCATE (t2); END LOOP; END clear; END ll_utilities;
Freeing a linked list Start with he head of a linked list and clear it All nodes must be deallocated
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PACKAGE ll_utilities IS TYPE node; TYPE pointer IS ACCESS node; TYPE node IS RECORD data : INTEGER; link : pointer; END RECORD; TYPE integer_vector IS ARRAY (INTEGER RANGE <>) OF INTEGER; PROCEDURE lineup (VARIABLE head : INOUT pointer; int : integer_vector); PROCEDURE remove (VARIABLE head : INOUT pointer; v : IN INTEGER); PROCEDURE clear (VARIABLE head : INOUT pointer); END ll_utilities; -PACKAGE BODY ll_utilities IS PROCEDURE lineup (VARIABLE head : INOUT pointer; int : integer_vector) IS
VARIABLE t1 : pointer; BEGIN -- Insert data in the linked list head := NEW node; t1 := head; FOR i IN int'RANGE LOOP t1.data := int(i); IF i = int'RIGHT THEN t1.link := NULL; ELSE t1.link := NEW node; t1 := t1.link; END IF; END LOOP;
END lineup; -PROCEDURE remove (VARIABLE head : INOUT pointer; v : IN INTEGER) IS

VARIABLE t1, t2 : pointer; BEGIN -- Remove node following that with value v t1 := head; WHILE t1 /= NULL LOOP IF t1.data = v THEN t2 := t1.link; t1.link := t2.link; DEALLOCATE (t2); END IF; t1 := t1.link; END LOOP;
END remove; -PROCEDURE clear (VARIABLE head : INOUT pointer) IS

VARIABLE t1, t2 : pointer; BEGIN -- Free all the linked list t1 := head; head := NULL; WHILE t1 /= NULL LOOP t2 := t1; t1 := t1.link; DEALLOCATE (t2); END LOOP;
END clear; END ll_utilities;
Linked list utilities
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SHARED VARIABLE dangerous : INTEGER := 0;
In the assignment: (sq4(0), sq4(1), sq4(2), sq4(3)) <= (OTHER => X); X can be interpreted as character X, requires a qualifier: (sq4(0), sq4(1), sq4(2), sq4(3)) <= qit_nibble (OTHERS => X); Now Xs are qualified for size and element type
Explicit type conversions for closely related types, e.g., INTEGER and REAL TYPE qit_byte IS ARRAY (7 DOWNTO 0) of qit; TYPE qit_octal IS ARRAY (7 DOWNTO 0) of qit; ... SIGNAL qb : qit_byte; SIGNAL qo : qit_octal; qb <= qo; -- CANNOT DO qb <= qit_byte (qo); -- Must do explicit type conversion
Share variables Using qualifiers Explicit type conversion between closely related types
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LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
std_logic is an enumeration type with nine logic values U is the default initial value std_logic_vector is an unconstraned array of std_logic All logical and shift operators are overloaded for std_logic and std_logic_vector Conversion functions for all subtypes and the BIT type to and from std_logic
std_logic, its overloading and its subtypes is a good example of the above topics
Provides types for most applications Overloading is done for all operators Includes conversion functions where needed
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TYPE X01 X01Z UX01 UX01Z
X, X, U, U,
0, 0, X, X,
1 1, 0, 0,
Z 1 1,
std_logic subtypes Enumeration elements are arranged for such subtypes Our qit is like UX01 or X01Z, different initial values
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PREDEFINED ATTRIBUTES
Attribute
LEFT RIGHT
Description
Left bound Right bound
Example
sq_4_8LEFT(1) sq_4_8RIGHT sq_4_8RIGHT(2) sq_4_8HIGH(2) sq_4_8LOW(2) sq_4_8RANGE(2) sq_4_8RANGE(1) sq_4_8REVERSE_RANGE(2) sq_4_8REVERSE_RANGE(1) sq_4_8LENGTH sq_4_8ASCENDING(2) sq_4_8ASCENDING(1) 3 0 7 7 0
Result
HIGH LOW RANGE
Upper bound Lower bound Range
0 TO 7 3 DOWNTO 0 7 DOWNTO 0 0 TO 3 4 TRUE FALSE
REVERSE_RANGE
Reverse range
LENGTH ASCENDING
Length TRUE If Ascending
Predefined attributes are demonstrated here. Array, Type, Signal, and Entity
Predefined Array Attributes Type of sq_4_8 is qit_4by8
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Attribute BASE LEFT RIGHT
Description Base of type Left bound of type or subtype Right bound of type or subtype Upper bound of type or subtype Lower bound of type or subtype Position of value V in base of type. Value at Position P in base of type. Value, after value V in base of type. Value, before value V in base of type. ...
Example ritBASE ritLEFT qitLEFT ritRIGHT qitRIGHT INTEGERHIGH ritHIGH POSITIVELOW qitLOW qitPOS(Z) ritPOS(X) qitVAL(3) ritVAL(3) ritSUCC(Z)
Result qit 0 0 Z X Large Z 1 0 2 3 X X X
HIGH
LOW
POS(V)
VAL(P)
SUCC(V)
PRED(V)
ritPRED(1)
...
...
...
Predefined type attributes The type of qit and rit are enumeration types More follows . . .
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Attribute ... LEFTOF(V) ...
Description ...
Example
Result ... 0 Error Z X TRUE TRUE Z qZ qZ
Value, left of value V in base of type. Value, right of value V in base of type. TRUE if range is ascending Converts value V of type to string. Converts string S to value of type.
ritLEFTOF(1) ritLEFTOF(0) ritRIGHTOF(1) ritRIGHTOF(Z) qitASCENDING qqitASCENDING qitIMAGE(Z) qqitIMAGE(qZ) qqitVALUE(qZ)
RIGHTOF(V)
ASCENDING IMAGE (V)
VALUE(S)
Predefined type attributes The type of qit and rit are enumeration types Note type versus base of type
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Attribute
T/E
Example
Kind
Type
Attribute description for the specified example DELAYED s1DELAYED (5 NS) SIGNAL As s1
A copy of s1, but delayed by 5 NS. If no parameter or 0, delayed by delta. Equivalent to TRANSPORT delay of s1. STABLE EV s1STABLE (5 NS) SIGNAL BOOLEAN
A signal that is TRUE if s1 has not changed in the last 5 NS. If no parameter or 0, the resulting signal is TRUE if s1 has not changed in the current simulation time. EVENT EV s1EVENT VALUE BOOLEAN
In a simulation cycle, if s1 changes, this attribute becomes TRUE. LAST_EVENT EV s1LAST_VALUE VALUE TIME
The amount of time since the last value change on s1. If s1EVENT is TRUE, the value of s1LAST_VALUE is 0. LAST_VALUE EV s1LAST_VALUE VALUE As s1
The value of s1 before the most recent event occurred on this signal. ...
Predefined signal attributes Signal s is assumed to be of type BIT More follows . . .
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Attribute
T/E
Example ...
Kind
Type
QUIET
TR
s1QUIET (5 NS)
SIGNAL
BOOLEAN
A signal that ir TRUE if no transaction has been placed on s1 in the last 5 NS. If no parameter or 0, the current simulation cycle is assumed. ACTIVE TR s1ACTIVE VALUE BOOLEAN
If s1 has had a transaction in the current simulation cycle, s1ACTIVE will be TRUE for this simulation cycle, for delta time. LAST_ACTIVE TR s1LAST_ACTIVE VALUE TIME
The amount of time since the last transaction occurred on s1. If s1ACTIVE is TRUE, s1LAST_ACTIVE is 0. TRANSACTION TR s1TRANACTION SIGNAL BIT
A signal that toggles each time a transaction occurs on s1. Initial value of this attribute is not defined. DRIVING s1DRIVING VALUE BOOLEAN
If s1is being driven in a process, s1DRIVING is TRUE in the same process. DRIVING_VALUE s1DRIVING_VALUE VALUE As s1
The driving value of s1 from within the process this attribute is being applied.
Predefined signal attributes Signal s is assumed to be of type BIT
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15 TIME (NS) 30 45 60
s1
s1'DELAYED (5NS) s1'STABLE
s1'EVENT 10 s1'LAST_EVENT s1'LAST_VALUE s1'QUIET (5NS) 15 20 25 0 5 10 0 5 10 15
s1'ACTIVE 10 s1'LAST_ACTIVE 0 5 10 0 5 10 0 5 10 0
s1'TRANSACTION
Results of signal attributes when applied to the BIT type signal, s1 Blocks show Boolean results
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ENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT); END brief_d_flip_flop; -ARCHITECTURE falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT; BEGIN tmp <= d WHEN (c = '0' AND NOT c'STABLE) ELSE tmp; q <= tmp AFTER 8 NS; END falling_edge;
A simple falling edge Flip-Flop using signal attributes Two events occur when c changes Cannot delay the first statement
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ENTITY brief_t_flip_flop IS PORT (t : IN BIT; q : OUT BIT); END brief_t_flip_flop; -ARCHITECTURE toggle OF brief_t_flip_flop IS SIGNAL tmp : BIT; BEGIN tmp <= NOT tmp WHEN ( (t = '0' AND NOT t'STABLE) AND (t'DELAYED'STABLE(20 NS)) ) ELSE tmp; q <= tmp AFTER 8 NS; END toggle;
A simple toggle Flip-Flop using signal attributes Combining several signal attributes Can only apply if result of an attribute is signal
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Entity Attributes generate a string corresponding to the name of an entity class
entity_class
entities, architectures, configurations, procedures, functions, packages, types, subtypes, constants, signals, variables, components, labels, literals, units, groups, and files
SIMPLE_NAME: Generates simple name of a named entity
PATH_NAME : Generates a string containing entity names and labels from the top of hierarchy leading to the named entity.
INSTANCE_NAME: Generates a name that contains entity, architecture, and instantiation labels leading to the design entity.
Entity attributes Generate a string for the name for an entity class
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ENTITY nand2 IS PORT (i1, i2 : IN BIT; o1 : OUT BIT); END ENTITY; -ARCHITECTURE single_delay OF nand2 IS SIGNAL simple : STRING (1 TO nand2'SIMPLE_NAME'LENGTH) := (OTHERS => '.'); SIGNAL path : STRING (1 TO nand2'PATH_NAME'LENGTH) := (OTHERS => '.'); SIGNAL instance : STRING (1 TO and2'INSTANCE_NAME'LENGTH) := (OTHERS => '.'); BEGIN o1 <= i1 NAND i2 AFTER 3 NS; simple <= nand2'SIMPLE_NAME; instance <= nand2'INSTANCE_NAME; path <= nand2'PATH_NAME; END single_delay; -ENTITY xoring IS PORT (i1, i2 : IN BIT; o1 : OUT BIT); END ENTITY; -ARCHITECTURE gate_level OF xoring IS SIGNAL a, b, c : BIT; BEGIN u1 : ENTITY WORK.nand2 PORT MAP (i1, i2, a); u2 : ENTITY WORK.nand2 PORT MAP (i1, a, b); u3 : ENTITY WORK.nand2 PORT MAP (a, i2, c); u4 : ENTITY WORK.nand2 PORT MAP (b, c, o1); END gate_level;
Examples for entity attributes Simple, path, and instance attributes
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Simple: Path: Instance:
nand2 :xoring:u1: xoring(gate_level):u1@nand2(single_delay):
Simple, path, and instance strings Results from simulation of the above nand2
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USER-DEFINED ATTRIBUTES
User-defined attributes may be applied to the elements of an entity class
Must declare first: ATTRIBUTE sub_dir : STRING;
Then attribute specification: ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS /user/vhdl;
brief_d_flip_flopsub_dir evaluates to /user/vhdl.
User-defined attributes are demonstrated here.
User defined attributes No simulation semantics
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USER-DEFINED ATTRIBUTES
PACKAGE utility_attributes IS TYPE timing IS RECORD rise, fall : TIME; END RECORD; ATTRIBUTE delay : timing; ATTRIBUTE sub_dir : STRING; END utility_attributes; -USE WORK.utility_attributes.ALL; -- FROM PACKAGE USE: delay, sub_dir ENTITY brief_d_flip_flop IS PORT (d, c : IN BIT; q : OUT BIT); ATTRIBUTE sub_dir OF brief_d_flip_flop : ENTITY IS "/user/vhdl"; ATTRIBUTE delay OF q : SIGNAL IS (8 NS, 10 NS); END brief_d_flip_flop; -ARCHITECTURE attributed_falling_edge OF brief_d_flip_flop IS SIGNAL tmp : BIT; BEGIN tmp <= d WHEN ( c= '0' AND NOT c'STABLE ) ELSE tmp; q <= '1' AFTER q'delay.rise WHEN tmp = '1' ELSE '0' AFTER q'delay.fall; END attributed_falling_edge;
Associating attributes to entities and signals A package declares attributes An entity defines An architecture uses attributes
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71
PACKAGING BASIC UTILITIES
PACKAGE basic_utilities IS ... TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE natural_vector IS ARRAY (NATURAL RANGE <>) OF NATURAL; ... FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; FUNCTION to_integer (qin : qit_vector) RETURN INTEGER; FUNCTION to_bitvector (qin : qit_vector) RETURN bit_vector; ... FUNCTION "+" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "+" (a : qit_vector; b : INTEGER) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : qit_vector) RETURN qit_vector; FUNCTION "-" (a : qit_vector; b : INTEGER) RETURN qit_vector; ... END basic_utilities;
Adding what was done to our basic utilities package Will use this package for homeworks and in other chapters
CHAPTER 7
72

PACKAGE basic_utilities IS TYPE qit IS ('0', '1', 'Z', 'X'); TYPE qit_2d IS ARRAY (qit, qit) OF qit; TYPE qit_1d IS ARRAY (qit) OF qit; TYPE qit_vector IS ARRAY (NATURAL RANGE <>) OF qit; SUBTYPE rit IS qit RANGE '0' TO 'Z'; TYPE rit_vector IS ARRAY (NATURAL RANGE <>) OF rit; TYPE integer_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; TYPE logic_data IS FILE OF CHARACTER; TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; -- Femto Farads (base unit) pfr = 1000 ffr; nfr = 1000 pfr; ufr = 1000 nfr; mfr = 1000 ufr; far = 1000 mfr; kfr = 1000 far; END UNITS; TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o; -- Milli-Ohms (base unit) ohms = 1000 l_o; k_o = 1000 ohms; m_o = 1000 k_o; g_o = 1000 m_o; END UNITS; FUNCTION fgl (w, x, gl : BIT) RETURN BIT; FUNCTION feq (w, x, eq : BIT) RETURN BIT; FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER; PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER); PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR); PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME); PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME); FUNCTION "AND" (a, b : qit) RETURN qit; FUNCTION "OR" (a, b : qit) RETURN qit; FUNCTION "NOT" (a : qit) RETURN qit; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME; END basic_utilities;
Complete package declaration
CHAPTER 7
73

PACKAGE BODY basic_utilities IS FUNCTION "AND" (a, b : qit) RETURN qit IS CONSTANT qit_and_table : qit_2d := ( ('0','0','0','0'), ('0','1','1','X'), ('0','1','1','X'), ('0','X','X','X')); BEGIN RETURN qit_and_table (a, b); END "AND"; FUNCTION "OR" (a, b : qit) RETURN qit IS CONSTANT qit_or_table : qit_2d := ( ('0','1','1','X'), ('1','1','1','1'), ('1','1','1','1'), ('X','1','1','X')); BEGIN RETURN qit_or_table (a, b); END "OR"; FUNCTION "NOT" (a : qit) RETURN qit IS CONSTANT qit_not_table : qit_1d := ('1','0','0','X'); BEGIN RETURN qit_not_table (a); END "NOT"; FUNCTION "*" (a : resistance; b : capacitance) RETURN TIME IS BEGIN RETURN ( ( a / 1 l_o) * ( b / 1 ffr ) * 1 FS ) / 1000; END "*"; FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; FUNCTION to_integer (bin : BIT_VECTOR) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; RETURN result; END;
Package body

PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i; END IF; END LOOP; int := result; END bin2int; PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER; BEGIN tmp := int; FOR i IN 0 TO (bin'LENGTH - 1) LOOP IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF; tmp := tmp / 2; END LOOP; END int2bin; PROCEDURE apply_data ( SIGNAL target : OUT BIT_VECTOR; CONSTANT values : IN integer_vector; CONSTANT period : IN TIME) IS VARIABLE buf : BIT_VECTOR (target'RANGE); BEGIN FOR i IN values'RANGE LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period; END LOOP; END apply_data;BB
Package body
CHAPTER 7
75

PROCEDURE assign_bits ( SIGNAL s : OUT BIT; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); IF char = '0' OR char = '1' THEN current := current + period; IF char = '0' THEN s <= TRANSPORT '0' AFTER current; ELSIF char = '1' THEN s <= TRANSPORT '1' AFTER current; END IF; END IF; END LOOP; END assign_bits; PROCEDURE assign_bits ( SIGNAL s : OUT qit; file_name : IN STRING; period : IN TIME) IS VARIABLE char : CHARACTER; VARIABLE current : TIME := 0 NS; FILE input_value_file : logic_data; BEGIN FILE_OPEN (input_value_file, file_name, READ_MODE); WHILE NOT ENDFILE (input_value_file) LOOP READ (input_value_file, char); current := current + period; CASE char IS WHEN '0' => s <= TRANSPORT '0' AFTER current; WHEN '1' => s <= TRANSPORT '1' AFTER current; WHEN 'Z' | 'z' => s <= TRANSPORT 'Z' AFTER current; WHEN 'X' | 'x' => s <= TRANSPORT 'X' AFTER current; WHEN OTHERS => current := current - period; END CASE; END LOOP; END assign_bits; END basic_utilities;
The basic_utilities package as will be used in the examples in the chapters that follow
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76
Summary This chapter presented tools for high level descriptions. Declaration of types and the usage of objects of various types were covered in the first part of the chapter. In the context of describing type-related issues, we introduced the unconstrained array and file type. The basic I/O presented in this chapter showed a simple way to read or write from files. The overloading which is related to types was discussed next. Predefined attributes in VHDL can be looked upon as operators or predefined functions. In modeling, hardware behavior attributes are very useful, as we will see in the following, chapters. Finally in this chapter, we presented the Elements of this package are
basic_utilities package.
useful for hardware modeling and the creation of the package demonstrates the importance of packaging capability in VHDL.
End Of Chapter 7
CHAPTER 7
77
CHAPTER 8 DATAFLOW DESCRIPTIONS IN VHDL
8.1 MULTIPLEXING AND DATA SELECTION 8.1.1 General Multiplexing 8.1.2 Guarded Signal Assignments 8.1.3 Block Declarative Part 8.1.4 Nesting Guarded Blocks 8.1.5 Disconnecting From Driver 8.1.6 Resolving Between Several Driving Values 8.1.7 MOS Implementation of Multiplexer 8.1.8 A General Multiplexer 8.1.9 Resolving INOUT Signals 8.2 STATE MACHINE DESCRIPTION 8.2.1 A Sequence Detector 8.2.2 Allowing Multiple Active States 8.2.3 Outputs of Mealy and Moore Machines 8.2.4 A Generic State Machine 8.3 OPEN COLLECTOR GATES 8.4 THREE STATE BUSSING 8.4.1 Std_logic Bussing 8.5 A GENERAL DATAFLOW CIRCUIT 8.6 UPDATING BASIC UTILITIES 8.7 SUMMARY
Constructs for dataflow descriptions Multiplexing and clocking, selection constructs; guarded assignments Multiple assignments; Resolutions: anding, oring, wiring Guarded signals State machines, simple sequence detector, multiple active states Open collectors using resolution functions A complete dataflow example
CHAPTER 8
MULTIPLEXING AND DATA SELECTION

select1
data1
out select2
data2
(a)
1D 2D y S1 S2
D1
Y D2
S1 S2
Will use VHDL for modeling various selection logic implementations
Basic data selection hardware, logic diagram, symbols Multiplexers are used for data selection
CHAPTER 8
enable
data
1D C1
clk
Flip flop clocking selects data Various forms of data selection may be combined Will show language constructs for such selections
CHAPTER 8
data1 data2
1D 2D Y 1D
select1 select2
S1 S2
C1
enable
clk
Multiplexing and clock enabling.
CHAPTER 8
G0 G1 select lines G2 G3 G4 G5 G6 G7
MUX
Z 0 1 2 data inputs 3 4 5 6 7
An eight-to-one multiplexer.
CHAPTER 8
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, qit_vector ENTITY mux_8_to_1 IS PORT ( i7, i6, i5, i4, i3, i2, i1, i0 : IN qit; s7, s6, s5, s4, s3, s2, s1, s0 : IN qit; z : OUT qit ); END mux_8_to_1; -ARCHITECTURE dataflow OF mux_8_to_1 IS BEGIN WITH qit_vector(s7, s6, s5, s4, s3, s2, s1, s0) SELECT z <= '0' AFTER 3 NS WHEN "00000000", i7 AFTER 3 NS WHEN "10000000" | "Z0000000", i6 AFTER 3 NS WHEN "01000000" | "0Z000000", i5 AFTER 3 NS WHEN "00100000" | "00Z00000", i4 AFTER 3 NS WHEN "00010000" | "000Z0000", i3 AFTER 3 NS WHEN "00001000" | "0000Z000", i2 AFTER 3 NS WHEN "00000100" | "00000Z00", i1 AFTER 3 NS WHEN "00000010" | "000000Z0", i0 AFTER 3 NS WHEN "00000001" | "0000000Z", 'X' WHEN OTHERS; END dataflow;
Description of a simple multiplexer Selected signal assignment is used Dataflow multiplexing Selected waveforms use choice or choices
CHAPTER 8
Syntax details of a selected signal assignment.
CHAPTER 8
A0 A1 A2
DCD S0 S1 S2 S3 S4 S5 S6 S7
Another form of selection is a decoder, which we will model in VHDL
Decoder description uses selected signal assignment A three-to-eight decoder.
CHAPTER 8
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit_vector ENTITY dcd_3_to_8 IS PORT (adr : IN qit_vector (2 DOWNTO 0); so : OUT qit_vector (7 DOWNTO 0)); END dcd_3_to_8; -ARCHITECTURE dataflow OF dcd_3_to_8 IS BEGIN WITH adr SELECT so <= "00000001" AFTER 2 NS WHEN "000", "00000010" AFTER 2 NS WHEN "00Z" | "001", "00000100" AFTER 2 NS WHEN "0Z0" | "010", "00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011", "00010000" AFTER 2 NS WHEN "100" | "Z00", "00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101" , "01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110", "10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" | "1ZZ" | "1Z1" | "11Z" | "111", "XXXXXXXX" WHEN OTHERS; END dataflow;
VHDL description for the three-to-eight decoder. All possibilities must be considered
CHAPTER 8
ENTITY d_flipflop IS GENERIC (delay1 : TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d, c : IN BIT; q, qb : OUT BIT); END d_flipflop; -ARCHITECTURE assigning OF d_flipflop IS SIGNAL internal_state : BIT; BEGIN internal_state <= d WHEN (c ='1' AND NOT c'STABLE) ELSE internal_state; q <= internal_state AFTER delay1; qb <= NOT internal_state AFTER delay2; END assigning;
1D
Q C1
A simple flip-flop uses internal_state On clock edge d is transferred to internal_state Events on internal_state cause assignments to q and qb
CHAPTER 8
10
target <= GUARDED waveforms__or__conditional_waveforms__or__selected_waveforms;
ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN q <= GUARDED d AFTER delay1; qb <= GUARDED NOT d AFTER delay2; END BLOCK ff; END guarding;
1D
Q C1
Several examples will demonstrate guarded blocks and assignments
The guarding architecture for the d_flipflop entity. Better representation of clocking disconnects d from q Disconnection is specified by GUARDED GUARDED assignments are guarded by guard expression Can also guard selected and conditional signal assignments
CHAPTER 8
11
ff : BLOCK (
block_label
Concurrent statement
c = 1 AND NOT cSTABLE ) BEGIN q <= GUARDED d AFTER delay1; qb <= GUARDED NOT d AFTER delay2; END BLOCK ff;
guard_expression
concurrent statement block statement part
block statement
concurrent statement
Syntax details of a guarded block statement with guarded signal assignments Label is mandatory Use GUARDED for guard to apply
CHAPTER 8
12
ENTITY flipflop_test IS END flipflop_test; -ARCHITECTURE input_output OF flipflop_test IS COMPONENT flop PORT (d, c : IN BIT; q, qb : OUT BIT); END COMPONENT; FOR c1 : flop USE ENTITY WORK.d_flipflop (assigning); FOR c2 : flop USE ENTITY WORK.d_flipflop (guarding); SIGNAL dd, cc, q1, q2, qb1, qb2 : BIT; BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 2 US ELSE cc; dd <= NOT dd AFTER 1000 NS WHEN NOW < 2 US ELSE dd; c1: flop PORT MAP (dd, cc, q1, qb1); c2: flop PORT MAP (dd, cc, q2, qb2); END input_output;
A test bench for testing assigning and guarding architectures of d_flipflop Testbench tests and verifies both descriptions A simple method for generation of periodic signals
CHAPTER 8
13
TIME (ns) 0000 +1 0004 0005 0400 +1 +2 0404 0405 0800 +1 +2 1000 +1 1200 +1 +2 1204 1205 1600 +1 +2 2000 +1 +2 2004 2005
cc '0' ... ... ... '1' ... ... ... ... '0' ... ... ... ... '1' ... ... ... ... '0' ... ... '1' '1' ... ... ...
dd '0' ... ... ... ... ... ... ... ... ... ... ... '1' ... ... ... ... ... ... ... ... ... '0' '0' ... ... ...
q1 '0' ... '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '1' ... ... ... ... ... ... ... '0' ...
q2 '0' ... ... ... ... ... ... '0' ... ... ... ... ... ... ... ... ... '1' ... ... ... ... ... ... ... '0' ...
qb1 '0' ... ... '1' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '0' ... ... ... ... ... ... ... '1'
qb2 '0' ... ... ... ... ... ... ... '1' ... ... ... ... ... ... ... ... ... '0' ... ... ... ... ... ... ... '1'
c1: state '0' '0' ... ... ... '0' '0' ... ... ... '0' '0' ... '0' ... '1' '1' ... ... ... '1' '1' ... '0' '0' ... ...
c2:ff GUARD FALSE ..... ..... ..... TRUE FALSE ..... ..... ..... FALSE FALSE ..... ..... ..... TRUE FALSE ..... ..... ..... FALSE FALSE ..... TRUE FALSE ..... ..... .....
Simulation results of the input_output architecture of the flipflop_test All transactions are observed In assigning:Two transactions on internal_state for every clock edge Transaction on q1 at time 0004, is due to initialization In guarding:c2.ff : GUARD sees GUARD inside guarding Guard expression is only TRUE for 1 delta
CHAPTER 8
14
s <= d WHEN (c= 1 AND NOT cSTABLE) ELSE UNAFFECTED; c

Scheduling on S
(d, 0) UNAFFECTED (a) Value = d
Value = s
s <= d WHEN (c= 1 AND cEVENT) ELSE UNAFFECTED; c

Scheduling on S
(d, 0) (b) Value = d
Value = s
s <= d AFTER 6 NS WHEN (c= 1 AND NOT cSTABLE) ELSE s; c

Scheduling on S
(d, 6) (s, 0) (c) Value = s
Value = s
s <= d AFTER 6 NS WHEN (c= 1 AND cEVENT) ELSE s; c

Scheduling on S
(d, 6) (d) Value = s Value = d
Events on edge detection expression Demonstrating difference between EVENT and NOT STABLE
ENTITY d_flipflop IS GENERIC (delay1: TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d, c : IN BIT; q, qb : OUT BIT); END ENTITY; -ARCHITECTURE guarding OF d_flipflop IS BEGIN ff: BLOCK (c= '1' AND NOT c'STABLE) PORT (din : IN BIT; qout, qbar : OUT BIT); PORT MAP (din => d, qout => q, qbar => qb); BEGIN qout <= GUARDED din AFTER delay1; qbar <= GUARDED NOT din AFTER delay2; END BLOCK ff; END guarding;
Using declarative part of a block statement PORT specifies signals on the outside PORT MAP maps outside signals with those inside Association format is used as expected
CHAPTER 8
16
ff : BLOCK ( . . . ) PORT ( . . . ); PORT MAP ( . . . ); BEGIN qout <= . . .; qbar <= . . .; END BLOCK ff;
block_statement
port_clause port_map_aspect
block_header
block_statement_part
Syntax details for block statement with header Uses this to draw a dashed line around a section of your hardware
CHAPTER 8
17
1, 2D
E2 C1
A positive edge trigger flip-flop with enable input Can nest block statements Combining guard expressions must be done explicitly
CHAPTER 8
18
ENTITY de_flipflop IS GENERIC (delay1 : TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d, e, c : IN BIT; q, qb : OUT BIT); END de_flipflop; -ARCHITECTURE guarding OF de_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate: BLOCK ( e = '1' AND GUARD ) BEGIN q <= GUARDED d AFTER delay1; qb <= GUARDED NOT d AFTER delay2; END BLOCK gate; END BLOCK edge; END guarding;
VHDL description for the positive edge trigger flip-flop with enable input Implicit GUARD signals in each block Useful if different second conditions were used
CHAPTER 8
19

ENTITY dee_flipflop IS GENERIC (delay1 : TIME := 4 NS; delay2 : TIME := 5 NS); PORT (d2, d3, e2, e3, c : IN BIT; q, qb : OUT BIT); END dee_flipflop; -ARCHITECTURE guarding OF dee_flipflop IS BEGIN edge: BLOCK ( c = '1' AND NOT c'STABLE ) BEGIN gate2: BLOCK ( e2 = '1' AND GUARD ) BEGIN q <= GUARDED d2 AFTER delay1; qb <= GUARDED NOT d2 AFTER delay2; END BLOCK gate2; gate3: BLOCK ( e3 = '1' AND GUARD ) BEGIN q <= GUARDED d3 AFTER delay1; qb <= GUARDED NOT d3 AFTER delay2; END BLOCK gate3; END BLOCK edge; END guarding;
1, 2D 1, 3D
E2 E3 C1
A positive edge trigger, double d flip-flop with independent enable inputs Clock expression is specified only once
CHAPTER 8
20
ENTITY flipflop_test IS END flipflop_test; -ARCHITECTURE input_output OF flipflop_test IS COMPONENT ff1 PORT (d, e, c : IN BIT; q, qb : OUT BIT); END COMPONENT; FOR c1 : ff1 USE ENTITY WORK.de_flipflop (guarding); SIGNAL dd, ee, cc, q1, qb1 : BIT; BEGIN cc <= NOT cc AFTER 400 NS WHEN NOW < 3 US ELSE cc; dd <= NOT dd AFTER 1000 NS WHEN NOW < 3 US ELSE dd; ee <= '1', '0' AFTER 2200 NS; c1: ff1 PORT MAP (dd, ee, cc, q1, qb1); END input_output;
A test bench for testing the guarding architectures of de_flipflop Testbench verifies operation of de_flipflop After 2200 q1 is disconnected from d
CHAPTER 8
21
TIME (ns) 0000 +1 0400 0404 0405 0800 1000 1200 1204 1205 1600 2000 2004 2005 2200 2400 2800 3000 +1 3200 +1
cc '0' ... '1' ... ... '0' ... '1' ... ... '0' '1' ... ... ... '0' '1' ... ... '0' '0'
ee '0' '1' ... ... ... ... ... ... ... ... ... ... ... ... '0' ... ... ... ... ... ...
dd '0' ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ... ... '1' '1' ... ...
q1 '0' ... ... '0' ... ... ... ... '1' ... ... ... '0' ... ... ... ... ... ... ... ...
qb1 '0' ... ... ... '1' ... ... ... ... '0' ... ... ... '1' ... ... ... ... ... ... ...
Simulation results of the input_output architecture of the flipflop_test All transactions are observed No transactions on the outputs after 2200 NS
CHAPTER 8
22
RHS Activation
GUARD
0 Driving Value Projected Output Waveform
Symbolizing guarded signal assignments Disconnection in a guarded signal assignment Driving value continues to be updated even if the guard expression is false
CHAPTER 8
23
What follows concentrates on definition & applications of resolution functions
Normally several sources cannot drive a signal Real circuits smoke, So does VHDL
CHAPTER 8
24
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY y_circuit IS PORT (a, b, c, d : IN qit; z : OUT qit); END y_circuit; -ARCHITECTURE smoke_generator OF y_circuit IS SIGNAL circuit_node : qit; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; circuit_node <= d; z <= circuit_node; END smoke_generator;
Multiple sources for a simple signal This results in an error message
CHAPTER 8
25
A happy circuit, a happy VHDL simulator
Multiple drivers is possible only if a resolution exists Example in hardware is "open collector" Pull_up provides resolution
CHAPTER 8
26
-- USE qit, qit_vector, AND from basic_utilities FUNCTION anding ( drivers : qit_VECTOR) RETURN qit IS VARIABLE accumulate : qit := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding;
a b anding c d circuit_node
The anding resolution function, ANDs all its drivers Performs the AND function two operand at a time Collect all ANDs and return A notation that we will use
CHAPTER 8
27
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ARCHITECTURE wired_and OF y_circuit IS FUNCTION anding (drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding; SIGNAL circuit_node : anding qit; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; circuit_node <= d; z <= circuit_node; END wired_and;
Multiple sources for a simple signal The difference is in the declaration of the left-hand-side This results in ANDing all sources Specify anding for the resolution on circuit_node Type of circuit_node is a subtype of qit ANDing simultaneously receives all drivers
CHAPTER 8
t4 v4 t4 v4 t4 v4
t3 v3 t3 v3 t3 t3
t2 v2 t2 v2 t2 t2
t1 v1 t1 v1 t1 t1
0 lhs_signal
Projected output waveforms and resolution functions Every assignment in a concurrent body creates a driver All assignments is a sequential body create only one driver Resolution functions act on expired values
CHAPTER 8
29
RHS Activation
GUARD
t4 v4 Driver 1
t3 v3
t2 v2
t1 v1
RHS Activation
lhs_signal GUARD
t4 v4 Driver 2
t3 v3
t2 v2
t1 v1
Guarded signal assignments into resolved signals Drivers continue to perform normal in spite of disconnection Resolution function cannot tell the difference, it only sees the driving value
CHAPTER 8
30
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ARCHITECTURE multiple_assignments OF mux_8_to_1 IS FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; SIGNAL t : oring qit; BEGIN t <= i7 AND s7; t <= i6 AND s6; t <= i5 AND s5; t <= i4 AND s4; t <= i3 AND s3; t <= i2 AND s2; t <= i1 AND s1; t <= i0 AND s0; z <= t; END multiple_assignments;
Implementing the eight-to-one multiplexer using eight concurrent assignments ORing resolution function is used
CHAPTER 8
31
FUNCTION wire (a, b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0','X','0','X'), ('X','1','1','X'), ('0','1','Z','X'), ('X','X','X','X')); BEGIN RETURN qit_wire_table (a, b); END wire;
In1: In2: 0 1 Z X
0 0 X 0 X
1 X 1 1 X Out
Z 0 1 Z X
X X In1 X Out X In2 X
The wire function for modeling wiring two qit type nodes. Input-output mapping Circuit notation
CHAPTER 8
32
FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate, drivers(i)); END LOOP; RETURN accumulate; END wiring;
FUNCTION wiring ( drivers : qit_vector) RETURN qit; SUBTYPE wired_qit IS wiring qit; TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit;
The wiring resolution function for qit type operands Necessary declarations for visibility of the wiring resolution function and its related types and subtypes If no drivers exist, Z will be returned To declare an array of this resolution
CHAPTER 8
33
FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit;
FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring;
SIGNAL t_byte : ored_qit_vector ( 7 DOWNTO 0 );
Another complete example The oring resolution function for the BIT type operands OR for BIT is already defined If no drivers, '0' is returned Necessary type and subtype definitions for the basic_utilities package Example signal declaration
CHAPTER 8
34
Will now model this circuit An NMOS eight-to-one multiplexer The CMOS version uses transmission gates instead of pass transistors
CHAPTER 8
35
si
ii
bi: BLOCK ( si = '1' OR si = 'Z') BEGIN t <= GUARDED ii; END BLOCK;
A block statement modeling a transmission gate
Disconnection is realized by block statements If all drivers are disconnected actual hardware returns to 'Z'
CHAPTER 8
36
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: wired_qit ARCHITECTURE multiple_guarded_assignments OF mux_8_to_1 IS
SIGNAL t : wired_qit BUS;

BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK; b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK; b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK; b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK; b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK; b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK; b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK; b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK; z <= t; END multiple_guarded_assignments; t <= GUARDED i7; t <= GUARDED i6; t <= GUARDED i5; t <= GUARDED i4; t <= GUARDED i3; t <= GUARDED i2; t <= GUARDED i1; t <= GUARDED i0;
Each ii connects to t if si is '1'; ii is disconnected from t if si is '0' Use BUS to implement this behavior Default in wire function is specified as 'Z' This default is used if wiring is called with Null Last disconnection causes call to wiring with Null
CHAPTER 8
37
An NMOS half-register with multiplexed input Modeling this circuit must take inverter input capacitance into account t holds charge if all are disconnected Circuit shows a register effect
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, wired_qit ENTITY multiplexed_half_register IS PORT (i7, i6, i5, i4, i3, i2, i1, i0 : IN qit; s7, s6, s5, s4, s3, s2, s1, s0 : IN qit; z : OUT qit ); END multiplexed_half_register; -ARCHITECTURE guarded_assignments OF multiplexed_half_register IS
SIGNAL t : wired_qit REGISTER;

BEGIN b7: BLOCK (s7 = '1' OR s7 = 'Z') BEGIN END BLOCK; b6: BLOCK (s6 = '1' OR s6 = 'Z') BEGIN END BLOCK; b5: BLOCK (s5 = '1' OR s5 = 'Z') BEGIN END BLOCK; b4: BLOCK (s4 = '1' OR s4 = 'Z') BEGIN END BLOCK; b3: BLOCK (s3 = '1' OR s3 = 'Z') BEGIN END BLOCK; b2: BLOCK (s2 = '1' OR s2 = 'Z') BEGIN END BLOCK; b1: BLOCK (s1 = '1' OR s1 = 'Z') BEGIN END BLOCK; b0: BLOCK (s0 = '1' OR s0 = 'Z') BEGIN END BLOCK; z <= NOT t AFTER 8 NS; END guarded_assignments; t <= GUARDED i7; t <= GUARDED i6; t <= GUARDED i5; t <= GUARDED i4; t <= GUARDED i3; t <= GUARDED i2; t <= GUARDED i1; t <= GUARDED i0;
Use REGISTER to model retaining of last value No call is made to wiring upon last disconnection BUS and REGISTER are kind specification Signals with kind are guarded signals Guarded signals must be used on LHS of guarded assignments Ok to use unguarded signals on LHS of guarded assignments
CHAPTER 8
BLOCK (guard_expression) BEGIN Guarded_lhs <= GUARDED rls_values; END;

---------------------------------------------------------------------------------------------
BLOCK (guard_expression) BEGIN Unguarded_resolved_signal <= GUARDED rls_values; END;
RHS Activation guard_expression
t4 v4 Driver i
t3 v3
t2 v2
t1 v1
guarded_lhs_signal
Turning off drivers from guarded signals Guard expression controls driver contribution to the resolution function Continuous contribution stops, even if a static value remains (if unguarded LHS)
CHAPTER 8
40
Before Last Disconnection
After Last Disconnection
f(v)
null v
f(null)
(a) BUS Kind
f(v)
null
f(v)
(b) REGISTER Kind
f(v)
f(v)
(c) Not Guarded
Last disconnections: BUS kind, REGISTER kind, unguarded
Disconnection disconnects if guarded BUS kind, last disconnection calls resolution function with Null REGISTER, last disconnection does not call the resolution function Unguarded, disconnection disconnects, but holds static value at the time of disconnection For unguarded, last disconnection is no different than others
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, qit_vector, wired_qit ENTITY mux_n_to_1 IS PORT (i, s : IN qit_vector; z : OUT wired_qit BUS); END mux_n_to_1; -ARCHITECTURE multiple_guarded_assignments OF mux_n_to_1 IS BEGIN bi: FOR j IN i'RANGE GENERATE bj: BLOCK (s(j) = '1' OR s(j) = 'Z') BEGIN z <= GUARDED i(j); END BLOCK; END GENERATE; END multiple_guarded_assignments;
mutliple_guarded_assignments architecture of the mux_n_to_1 A general n-bit multiplexer Ports can be resolved signals BUS kind can also be specified, not REGISTER
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42
USE WORK.basic_utilities.ALL; ENTITY mux_tester IS END mux_tester; -ARCHITECTURE input_output OF mux_tester IS COMPONENT mux PORT (i, s : IN qit_vector; z : OUT wired_qit BUS); END COMPONENT; FOR ALL : mux USE ENTITY WORK.mux_n_to_1 (multiple_guarded_assignments); SIGNAL ii, ss : qit_vector (3 DOWNTO 0) := "0000"; SIGNAL zz : qit; BEGIN ii <= "1010" AFTER 10 US, "Z100" AFTER 20 US, "0011" AFTER 30 US; ss <= "0010" AFTER 05 US, "1100" AFTER 15 US, "000Z" AFTER 25 US; mm : mux PORT MAP (ii, ss, zz); END input_output;
A test bench for the generic multiple_guarded_assignments architecture of mux_n_to_1 This entity is used as a four bit multiplexer
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43
TIME (ns) 00000 +1 05000 +1 10000 +1 15000 +1 20000 +1 25000 +1 30000 +1
ii(3:0) "0000" ...... ...... ...... "1010" ...... ...... ...... "Z100" ...... ...... ...... "0011" ......
ss(3:0) "0000" ...... "0010" ...... ...... ...... "1100" ...... ...... ...... "000Z" ...... ...... ......
zz '0' 'Z' ... '0' ... '1' ... 'X' ... '1' ... '0' ... '1'
Simulation results of the input_output architecture of the mux_tester Simulation produces 'X' for two conflicting enabled inputs Produces 'Z' when no inputs are enabled
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44
Remaining issues:
Disconnection Right and left INOUT
More issues on resolutions, guarded signals & resolved signals will de discussed
Will discuss other issues, then will start using resolved, guarded, and other signal types Several examples will follow
CHAPTER 8
45

si
ii ARCHITECTURE . . . SIGNAL t : wired_qit; BEGIN ... t <= GUARDED ii AFTER n NS; ... END ARCHITECTURE;
Connection is timed: After connection, it takes n NS for t to get ii
ARCHITECTURE . . . SIGNAL t : wired_qit; DISCONNECT t : wired_qit AFTER 6 NS; BEGIN ... t <= GUARDED ii AFTER n NS; ... END ARCHITECTURE;
Time disconnection by DISCONNECT statement: Disconnection from t occurs m NS after GUARD becomes FALSE
Specify disconnection in the declaration Use ALL for all signals of that type Use OTHERS if some specified otherwise
CHAPTER 8
46
Value used on the right hand side Value placed on driver of a
t4 v4
t3 v3
t2 v2
t1 v1
Other Drivers
a <= a AND b AFTER delay;
Resolved signals on right and left hand sides What you get is not what you put in Others contribute to a resolved signal
CHAPTER 8
47
ENTITY one (a : IN BIT; x : INOUT BIT) ENTITY two (b : IN BIT; y : INOUT BIT) -ENTITY three IS END three; ARCHITECTURE connecting OF three IS SIGNAL z : oring BIT; . . . BEGIN c1 : ENTITY WORK.one PORT MAP (a, z); c2 : ENTITY WORK.two PORT MAP (b, z); . . END connecting;
x a
oring y b
Connecting INOUT ports require resolved signals There are two drivers for each interconnection
CHAPTER 8
48
STATE MACHINE DESCRIPTION
Will use resolutions and guarded assignments in several examples
State names indicate detected sequences Use resolutions & guarded blocks A simple 1011 Mealy detector A block statement for each state
CHAPTER 8
49

ENTITY detector IS PORT (x, clk : IN BIT; z : OUT BIT); END detector; ARCHITECTURE singular_state_machine OF detector IS TYPE state IS (reset, got1, got10, got101); TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state; FUNCTION one_of (sources : state_vector) RETURN state IS BEGIN RETURN sources(sources'LEFT); END one_of; SIGNAL current : one_of state REGISTER := reset; BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK ( current = reset AND GUARD ) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE reset; END BLOCK s1; s2: BLOCK ( current = got1 AND GUARD ) BEGIN current <= GUARDED got10 WHEN x = '0' ELSE got1; END BLOCK s2; s3: BLOCK ( current = got10 AND GUARD ) BEGIN current <= GUARDED got101 WHEN x = '1' ELSE reset; END BLOCK s3; s4: BLOCK ( current = got101 AND GUARD) BEGIN current <= GUARDED got1 WHEN x = '1' ELSE got10; z <= '1' WHEN ( current = got101 AND x = '1') ELSE '0'; END BLOCK s4; END BLOCK clocking; END singular_state_machine;
VHDL description of 1011 detector Only one simultaneous active state Current receives four concurrent assignments Current must be resolved; use one_of
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50

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000"; BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN s1: BLOCK (s(1) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s1; s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s2; s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s3; s4: BLOCK (s(4) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; z <= '1' WHEN (s(4) = '1' AND x = '1') ELSE '0'; END BLOCK s4;
s <= GUARDED "0000";

END BLOCK clocking; END multiple_state_machine;
VHDL description of 1011 detector More than one state can simultaneously be active The last description does not allows multiple active states To remedy: use a signal for each state State 3 : goes to 1 when x = '0'; goes to 4 when x = '1'
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51

USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: ored_bit_vector ARCHITECTURE multiple_state_machine OF detector IS SIGNAL s : ored_bit_vector (1 TO 4) REGISTER := "1000"; BEGIN clocking : BLOCK (clk = '1' AND NOT clk'STABLE) BEGIN ... s2: BLOCK (s(2) = '1' AND GUARD) BEGIN s(3) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(2) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s2; s3: BLOCK (s(3) = '1' AND GUARD) BEGIN s(1) <= GUARDED '1' WHEN x = '0' ELSE '0'; s(4) <= GUARDED '1' WHEN x = '1' ELSE '0'; END BLOCK s3; ...
s <= GUARDED "0000";

END BLOCK clocking; END multiple_state_machine;
State 3 : goes to 1 when x = '0'; goes to 4 when x = '1' S must be resolved vector REGISTER kind S <= GUARDED "0000"; Causes removal of retained value upon last disconnection
CHAPTER 8
52

ENTITY detector_m IS PORT (x,clk : IN BIT; z : OUT BIT); GENERIC (n : INTEGER); END detector_m; -ARCHITECTURE multiple_moore_machine_1 OF detector_m IS FUNCTION oring( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit; TYPE next_table IS ARRAY (1 TO n, BIT) OF INTEGER; TYPE out_table IS ARRAY (1 TO n, BIT) OF BIT; -- Fill in next_val, out_val, and s arrays SIGNAL o : ored_bit REGISTER; BEGIN clocking : BLOCK (clk = '1' AND (NOT clk'STABLE)) BEGIN g: FOR i IN s'RANGE GENERATE si: BLOCK (s(i) = '1' AND GUARD) BEGIN s(next_val(i,'0')) <= GUARDED '1' WHEN x='0' ELSE '0'; s(next_val(i,'1')) <= GUARDED '1' WHEN x='1' ELSE '0';
o <= GUARDED out_val(i, x);
END BLOCK si; s (i) <= GUARDED '0'; END GENERATE; END BLOCK clocking; z <= o; END multiple_moore_machine_1;
A generic state machine A Moore sequence detector Specify transitions & outputting in constant tables Allows multiple machines in one
CHAPTER 8
53
------------------------------------------------------------------Tables for programming the configurable Moore description -------------------------------------------------------------------- Next States: ----x=0, x=1 -CONSTANT next_val : next_table := ( (1 , 2), --S1: -> S1, S2 -(1 , 3), --S2: -> S1, S3 -(1 , 4), --S3: -> S1, S4 -(1 , 1), --S4: -> S1, S1 -(5 , 6), --S5: -> S5, S6 -(5 , 6) );--S6: -> S5, S6 ------ Output Values: ----x=0, x=1 -CONSTANT out_val : out_table := ( ('0' , '0'), --S1: == z=0, 0 -('0' , '0'), --S2: == z=0, 0 -('0' , '0'), --S3: == z=0, 0 -('1' , '1'), --S4: == z=1, 1 -('0' , '0'), --S5: == z=0, 0 -('1' , '1') );--S6: == z=1, 1 ----- Initial Active States: -SIGNAL s : ored_bit_vector (1 TO 6) REGISTER := "100010"; ----------------------------------------------------------------------------------------------------------------------------------
Next state and output tables The next_val constant holds next state values The out_val constant holds the output values on the z output Initial starting states are set to '1' in the s vector
CHAPTER 8
54
OPEN COLLECTOR GATES
VCC
a y b
GND
Open collector NAND gate A two-input NAND gate, TTL 74LS03 SSI package Resolution functions are used in bussing Will use open collector to illustrate
CHAPTER 8
55
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, "AND" ENTITY nand2 IS PORT (a, b : IN qit; y : OUT qit); CONSTANT tplh : TIME := 10 NS; CONSTANT tphl : TIME := 12 NS; END nand2; -ARCHITECTURE open_output OF nand2 IS BEGIN y <= '0' AFTER tphl WHEN (a AND b) = '1' ELSE 'Z' AFTER tplh WHEN (a AND b) = '0' ELSE 'X' AFTER tphl; END open_output;
VHDL description of a NAND gate with open collector output Use qit type Output is Z and not 1
CHAPTER 8
56

ENTITY test_nand2 IS END test_nand2; -USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, assign_bits ARCHITECTURE input_output OF test_nand2 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); SIGNAL aa, bb, yy : qit; TIME BEGIN (ns) aa bb assign_bits (aa, "qit_data", 500 NS); 0000 '0' '0' assign_bits (bb, "qit_data", 750 NS); 0010 ... ... c1: nand2 PORT MAP (aa, bb, yy); 1000 '1' ... 1500 ... '1' END input_output;
1512 2500 2510 3000 3012 3750 3760 4000 4500 4512 5000 5010 5500 5512 6000 6010 6750 6762 7500 7510 8250 8262 ... '0' ... 'Z' ... ... ... '0' '1' ... '0' ... 'Z' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '0' ... ... 'Z' ... ... ... ... ... '0' ... '1' ... '0' ... 'Z' ...
yy '0' 'Z' ... ... '0 ... 'Z' ... '0' ... 'Z' ... ... '0' ... 'Z' ... '0' ... 'Z' ... '0' ... 'Z' ... '0'
Testing the open-collector NAND gate Test bench uses external data file Output is either 0 or Z, never 1
CHAPTER 8
57
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit ENTITY sn7403 IS PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END sn7403; -ARCHITECTURE structural OF sn7403 IS COMPONENT nand2 PORT (a, b : IN qit; y : OUT qit); END COMPONENT; FOR ALL : nand2 USE ENTITY WORK.nand2 (open_output); BEGIN g1: nand2 PORT MAP ( a1, b1, y1 ); g2: nand2 PORT MAP ( a2, b2, y2 ); g3: nand2 PORT MAP ( a3, b3, y3 ); g4: nand2 PORT MAP ( a4, b4, y4 ); END structural;
VHDL description of TTL 74LS03 Contains four open collector NAND gates Will use in a design
CHAPTER 8
58
a1 b1
a4 aa pull_up_1 y1 g4 a2 bb b2 pull_up_3 y4 yy g2 pull_up_2 y2 g3 a3 b3 g1 b4
y3
yy = (aa' . bb) . (bb' . aa)' = ( aa bb )'
Implementing XNOR logic using open collector NAND gates Using 74LS03 for implementing an XNOR pull_up3 has two drivers pull_up1 and pull_up2 must be turned to 0, 1 logic
CHAPTER 8
59
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: qit, anded_qit ENTITY test_xnor IS END test_xnor; -ARCHITECTURE input_output OF test_xnor IS COMPONENT sn7403 PORT (a1, a2, a3, a4, b1, b2, b3, b4 : IN qit; y1, y2, y3, y4 : OUT qit); END COMPONENT; FOR ALL : sn7403 USE ENTITY WORK.sn7403 (structural); SIGNAL aa, bb : qit; SIGNAL pull_up_1, pull_up_2, pull_up_3 : anded_qit := 'Z'; BEGIN aa <= '1', '0' AFTER 10US, '1' AFTER 30US, '0' AFTER 50US, 'Z' AFTER 60US; bb <= '0', '1' AFTER 20US, '0' AFTER 40US, 'Z' AFTER 70US; c1: sn7403 PORT MAP ( aa, bb, pull_up_1, pull_up_2, aa, bb, bb, aa, pull_up_1, pull_up_2, pull_up_3, pull_up_3); END input_output;
Wiring and testing XNOR function implemented by four open collector AND gates pull_up_1 and pull_up_2 turn 0,Z to 0,1 anded_qit resolution function implements wired logic
CHAPTER 8
60

TIME (us) 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 aa '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' 'Z' 'Z' 'Z' 'Z' 'Z' 'Z' bb '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' 'Z' pull_up_1 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' pull_up_2 '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' '1' pull_up_3 '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '1' '0' '0' '0' '0' '0'
Results are observed at 2 us intervals Simulation shows XNOR implementation Pull up resolutions turn gate output 'Z' values to '1'
CHAPTER 8
61
THREE STATE BUSSING
u1 :
alu
u2 :
reg1
u3 : bus1 8
8 8
bus a
u4 :
unit1
u5 :
unit2
A bussing system (bus_sys) Will use resolution functions for describing it A very common hardware for RT level descriptions Some components have three-state outputs some do not
CHAPTER 8
62
THREE STATE BUSSING
ENTITY alu IS PORT ( ; zout : out qit_vector (7 DOWNTO 0)); END alu; -ENTITY reg1 IS PORT ( ; zout : out wired_qit_vector (7 DOWNTO 0)); END reg1; -SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); -ENTITY unit1 IS PORT (zin : IN qit_vector (7 DOWNTO 0); ); END unit1; -ENTITY unit2 IS PORT (zin : IN wired_qit_vector (7 DOWNTO 0); ); END unit2;
Interface of bus sources and destinations Wired_qit_vector is used for those with three-state outputs Connection of others must be through three-state constructs
CHAPTER 8
63
THREE STATE BUSSING
ARCHITECTURE partial OF bus_sys IS SIGNAL busa : wired_qit_vector (7 DOWNTO 0); SIGNAL bus1 : wired_qit_vector (7 DOWNTO 0); SIGNAL aluout, unit1in : qit_vector (7 DOWNTO 0); BEGIN . . . u1 : ENTITY WORK.alu PORT MAP (; aluout); busa <= wired_qit_vector (aluout); ... u2 : ENTITY WORK.reg1 PORT MAP (; busa); u3 : busa <= bus1; unit1in <= qit_vector (busa); u4 : ENTITY WORK.unit1 PORT MAP (unit1in;); u5 : ENTITY WORK.unit2 PORT MAP (busa;); END partial;
Partial VHDL description for bussing system example reg1 with three-state output directly drives the bus aluout goes through three-state constructs All required hardware structures are explicitly coded
CHAPTER 8
64
Std_logic BUSSING
std_ulogic for standard unresolved logic A resolution function: resolution std_logic is defined as resolution subtype of std_logic Vectorized std_logic and std_ulogic are defined, e.g., std_logic_vector Conversions from one type to another are provided Logic operators are overloaded for both types and their vectorized forms
Std_logic provides multi-value logic for most applications No need for new user types Most designers use the resolved type
CHAPTER 8
65
A GENERAL DATAFLOW CIRCUIT
8-bit Parallel data
Count equal sequential data on parallel input lines.

4-bit Count output
Reset input
Seen dataflow primitives Use dataflow for system description A sequential comparator example
CHAPTER 8
66
USE WORK.basic_utilities.ALL; -- FROM PACKAGE USE: bin2int, int2bin ENTITY sequential_comparator IS PORT (data : IN BIT_VECTOR (7 DOWNTO 0); clk, reset : IN BIT; matches : OUT BIT_VECTOR (3 DOWNTO 0)); END sequential_comparator; -ARCHITECTURE dataflow OF sequential_comparator IS FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER; VARIABLE t : BIT_VECTOR (x'RANGE); BEGIN bin2int (x, i); i := i + 1; IF i >= 2**x'LENGTH THEN i := 0; END IF; int2bin (i, t); RETURN t; END inc; SIGNAL buff : BIT_VECTOR (7 DOWNTO 0); SIGNAL count : BIT_VECTOR (3 DOWNTO 0); BEGIN edge: BLOCK (clk = '0' AND NOT clk'STABLE) BEGIN buff <= GUARDED data; count <= GUARDED "0000" WHEN reset = '1' ELSE inc (count) WHEN data = buff ELSE count; END BLOCK; matches <= count; END dataflow;
Dataflow description of the sequential comparator circuit inc function is unconstrained Save old data in buff Compares old and new
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67

TIME (ns) 0000 +1 0200 0500 1000 +1 1200 1500 1700 2000 +1 2500 3000 +1 +2 3200 3500 3700 4000 +1 4200 4500 5000 +1 5500 6000 +1 +2 6500 7000 +1 +2 7500 8000 +1 +2 8500
reset '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
clk '0' ... ... '1' '0' ... ... '1' ... '0' ... '1' '0' ... ... ... '1' ... '0' ... ... '1' '0' ... '1' '0' ... ... '1' '0' ... ... '1' '0' ... ... '1'
data(7:0) "00000000" .......... "11110101" .......... .......... .......... "01010110" .......... "11111110" .......... .......... .......... .......... .......... .......... "01010100" .......... "00010001" .......... .......... "10010110" .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
buff(7:0) "00000000" .......... .......... .......... .......... "11110101" .......... .......... .......... .......... "11111110" .......... .......... "11111110" .......... .......... .......... .......... .......... "00010001" .......... .......... .......... "10010110" .......... .......... "10010110" .......... .......... .......... "10010110" .......... .......... .......... "10010110" .......... ..........
count(3:0) "0000" ...... ...... ...... ...... "0000" ...... ...... ...... ...... "0000" ...... ...... "0001" ...... ...... ...... ...... ...... "0001" ...... ...... ...... "0001" ...... ...... "0010" ...... ...... ...... "0011" ...... ...... ...... "0100" ...... ......
matches "0000" "0000" ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... "0001" ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... "0010" ...... ...... ...... "0011" ...... ...... ...... "0100" ......
matches shows count of matching data
CHAPTER 8
68
UPDATING BASIC UTILITIES

PACKAGE basic_utilities IS . . FUNCTION wire (a, b : qit) RETURN qit; -FUNCTION oring ( drivers : qit_vector) RETURN qit; SUBTYPE ored_qit IS oring qit; TYPE ored_qit_vector IS ARRAY (NATURAL RANGE <>) OF ored_qit; -FUNCTION anding ( drivers : qit_vector) RETURN qit; SUBTYPE anded_qit IS anding qit; TYPE anded_qit_vector IS ARRAY (NATURAL RANGE <>) OF anded_qit; -FUNCTION wiring ( drivers : qit_vector) RETURN qit; SUBTYPE wired_qit IS wiring qit; TYPE wired_qit_vector IS ARRAY (NATURAL RANGE <>) OF wired_qit; -FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS ARRAY (NATURAL RANGE <>) OF ored_bit; -FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT; SUBTYPE anded_bit IS anding bit; TYPE anded_bit_vector IS ARRAY (NATURAL RANGE <>) OF anded_bit; -FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR; END basic_utilities;
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69
PACKAGE BODY basic_utilities IS . . . FUNCTION wire (a, b : qit) RETURN qit IS CONSTANT qit_wire_table : qit_2d := ( ('0','X','0','X'), ('X','1','1','X'), ('0','1','Z','X'), ('X','X','X','X')); BEGIN RETURN qit_wire_table (a, b); END wire; FUNCTION oring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; FUNCTION anding ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding; FUNCTION wiring ( drivers : qit_vector) RETURN qit IS VARIABLE accumulate : qit := 'Z'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := wire (accumulate, drivers(i)); END LOOP; RETURN accumulate; END wiring;
CHAPTER 8
70
FUNCTION oring ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '0'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate OR drivers(i); END LOOP; RETURN accumulate; END oring; FUNCTION anding ( drivers : BIT_VECTOR) RETURN BIT IS VARIABLE accumulate : BIT := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END anding; FUNCTION inc (x : BIT_VECTOR) RETURN BIT_VECTOR IS VARIABLE i : INTEGER; VARIABLE t : BIT_VECTOR (x'RANGE); BEGIN bin2int (x, i); i := i + 1; IF i >= 2**x'LENGTH THEN i := 0; END IF; int2bin (i, t); RETURN t; END inc; END basic_utilities;
Resolution functions and inc function added to basic_utilities
CHAPTER 8
71
SUMMARY This chapter presented signal assignment, guarded assignments, and resolution functions, which are considered to be among the most important hardware related constructs in the VHDL language. Guarded signal assignment and the concept of disconnection, or turning off a source, were presented. This prepared the way for describing resolution functions, multiple drivers of signals, and guarded signals. Although VHDL only requires resolution of
signals with multiple concurrent sources, in general a resolved signal is a better representation of a circuit node. A resolution function for a node can be written to match its technology-dependent behavior. The
resolution functions developed in this chapter are typical of the way buses function in a digital system.
End Of Chapter 8
CHAPTER 8
72
CHAPTER 9 BEHAVIORAL DESCRIPTION OF HARDWARE

9.1 PROCESS STATEMENT 9.1.1 Declarative Part of a Process 9.1.2 Statement Part of a Process 9.1.3 Sensitivity List 9.1.4 A First Process Example 9.1.5 Syntax Details of Process Statements 9.1.6 Postponed Processes 9.1.7 Passive Processes 9.1.8 Behavioral Flow Control Constructs 9.2 ASSERTION STATEMENT 9.2.1 Sequential Use of Assertion Statements 9.2.2 Concurrent Assertion Statements 9.3 SEQUENTIAL WAIT STATEMENTS 9.3.1 A Behavioral State Machine 9.3.2 Two Phase Clocking 9.3.3 Implementing Handshaking 9.3.4 Interface Handshaking 9.4 FORMATTED ASCII I/O OPERATIONS 9.4.1 Basic Screen Output 9.4.2 A Display Procedure 9.4.3 Simulation Report 9.5 MSI BASED DESIGN 9.5.1 Top Level Partitioning 9.5.2 Description of Components 9.5.3 Design Implementation 9.6 SUMMARY
Constructs for sequential descriptions Process statement is a key construct Assertion for behavioral checks Handshaking constructs Timing control Formatted I/O
CHAPTER 9
PROCESS STATEMENT
Concurrent process statement PROCESS Always alive process declarative_part (non-signal) ...
BEGIN
Always active process statement_part (sequential) ...
END PROCESS;
Process statements describe hardware without much hardware details
PROCESS: A concurrent statement, enclosing sequential statements Declarative part contains only variables and constants Use only sequential constructs
CHAPTER 9
PROCESS STATEMENT
PROCESS BEGIN Reapets forever,

S e q u e n t i a l
In zero time,
Unless suspended
END PROCESS;
Unless a sequential body is suspended It executes in zero real and delta time It repeats itself forever
CHAPTER 9
PROCESS STATEMENT
ARCHITECTURE sequentiality_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a; y <= b; ... END PROCESS; END sequentiality_demo;
First: a is scheduled for x Next: b is scheduled for y x and y receive values at the same time Both assignments occur a delta later Zero time between both scheduling
CHAPTER 9
PROCESS STATEMENT
ARCHITECTURE execution_time_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= a AFTER 10 NS; y <= b AFTER 6 NS; ... END PROCESS; END execution_time_demo;
First: a is scheduled for x Next: b is scheduled for y y receives b sooner than x receiving a
CHAPTER 9
PROCESS STATEMENT
ARCHITECTURE data_availability_demo OF partial_process IS BEGIN PROCESS BEGIN ... x <= '1'; IF x = '1' THEN Perform_action_1 ELSE Perform_action_2 END IF; ... END PROCESS; END data_availability_demo;
Assume x_sig is initially '0' Assignment of '1' to x_sig takes a delta Action_2 will be taken Variable x_var had to be declared inside the Process statement If x_var was used instead of x_sig, action_1 would be taken
CHAPTER 9
PROCESS STATEMENT
ARCHITECTURE BEGIN a <= b; c <= d; END ;
ARCHITECTURE BEGIN PROCESS (b) a <= b; END PROCESS; c <= d; END ;
Process is a concurrent statement Signal assignment is a concurrent statement Process sensitivity plays the role of RHS activation Any signal assignment can be expressed by a process statement
Can use a signal assignment in a sequential body On the left: events on b cause assignment Process is executed when an event occurs on b On the right: (b) is sensitivity list of process Process statement executes only once for every event on b Process suspends till next event on b occurs
CHAPTER 9
PROCESS STATEMENT
R 1D Q
C1 S
A flip-flop will demonstrate assignments and flow in process statements
Have modeled flip-flops with concurrent statements A process statement is a powerful construct for such descriptions
CHAPTER 9
PROCESS STATEMENT
ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END d_sr_flipflop; -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;
Three concurrent processes dff process is sensitive to (rst, set, clk) Internal state receives proper value Events on state cause events on q and qb
CHAPTER 9
PROCESS STATEMENT
ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) VARIABLE state : BIT := '0'; BEGIN IF set = '1' THEN state := '1'; ELSIF rst = '1' THEN state := '0'; ELSIF clk = '1' AND clk'EVENT THEN state := d; END IF; q <= state AFTER (sq_delay + rq_delay + cq_delay) /3; qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay) /3; END PROCESS dff; END average_delay_behavioral;
Single process assigns values to q and qb This description eliminates the delay of the last description Less precise timing
CHAPTER 9
10
PROCESS STATEMENT
TIME (NS) 0 +1 6 200 206 +1 500 1000 1200 1400 1406 +1 1500 2000 2200 2400 2500 2506 +1 3000 3300 3500 3506 +1 4000
ss '0' ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
rr '0' ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ... ... ... ... ... ... ...
cc '0' ... ... ... ... ... '1' '0' ... ... ... ... '1' '0' ... ... '1' ... ... '0' ... '1' ... ... '0'
dd '0' ... ... ... ... ... ... ... ... ... ... ... ... ... ... '1' ... ... ... ... '0' ... ... ... ...
q1 '0' ... ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ...
q2 '0' ... ... ... '1' ... ... ... ... ... '0' ... ... ... ... ... ... '1' ... ... ... ... '0' ... ...
qb1 '0' '1' ... ... ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ...
qb2 '0' ... '1' ... '0' ... ... ... ... ... '1' ... ... ... ... ... ... '0' ... ... ... ... '1' ... ...
Simulation run compares flip-flop descriptions The 3 process description has a delay However, potential of more precise timing
CHAPTER 9
11
PROCESS STATEMENT
ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); END ENTITY; -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff: PROCESS (rst, set, clk) TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; VARIABLE sd : bit_time := ('0', 0 NS); BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff; END behavioral;
This example uses a record for delay and flip-flop values Logic value and delay are assigned to variables Assignment to variables are done in zero time without the delay
CHAPTER 9
12
PROCESS STATEMENT
dff: PROCESS (rst, set, clk) VARIABLE state : BIT := 0 BEGIN IF set = 1 THEN state := 1;
sensitivity_list variable declaration process declarative part
process statement
ELSEIF rst = 1 THEN state := 0; ELSEIF clk = -1 AND clkEVENT THEN state := d; END IF; q <= state AFTER (sq_delay + rq_delay + cq_delay)/3; qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay)/3; END PROCESS dff;
sequential statement
process statement part
sequential statement sequential statement
Syntax details include sensitivity list
CHAPTER 9
13
PROCESS STATEMENT
dff : PROCESS(rst, set, clk) BEGIN . . . END;
dff : POSTPONED PROCESS(rst, set, clk) BEGIN . . . END;
becomes active
becomes active
clk
set
rst t1+1 t1+2 t1+3
Postponed process Wait until the last event in a real time increment Signal assignments can become postponed
CHAPTER 9
14
PROCESS STATEMENT
PACKAGE bt IS TYPE bit_time IS RECORD state : BIT; delay : TIME; END RECORD; SHARED VARIABLE sd : bit_time := ('0', 0 NS); END PACKAGE bt; -USE WORK.bt.ALL; ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); BEGIN dff: PROCESS (rst, set, clk) BEGIN IF set = '1' THEN sd := ('1', sq_delay); ELSIF rst = '1' THEN sd := ('0', rq_delay); ELSIF clk = '1' AND clk'EVENT THEN sd := (d, cq_delay); END IF; END PROCESS dff; END ENTITY; -ARCHITECTURE behavioral OF d_sr_flipflop IS BEGIN dff_arch: PROCESS (rst, set, clk) BEGIN q <= sd.state AFTER sd.delay; qb <= NOT sd.state AFTER sd.delay; END PROCESS dff_arch; END behavioral;
A passive process statement may appear in the entity statement part Cannot make assignments to signals This models the same flip-flop
CHAPTER 9
15
PROCESS STATEMENT
long_runing : LOOP ... IF x = 25 THEN EXIT; END IF; ... END LOOP long_runing;
NEXT loop_label WHEN condition;
EXIT WHEN condition;
Loop is a sequential statement Example runs forever unless exited EXIT & NEXT control flow of loops EXIT & NEXT can be conditioned
CHAPTER 9
16
PROCESS STATEMENT
loop_1 : FOR i IN 5 TO 25 LOOP ... sequential_statement_1; ... sequential_statement_2; ... loop_2 : WHILE j <= 90 LOOP ... sequential_statement_3; sequential_statement_4; ...
NEXT loop_1 WHEN condition_1;

... sequential_statement_5; sequential_statement_6; ... END LOOP loop_2; ... END LOOP loop_1;
Conditional Next Statements in a Loop FOR, WHILE are controlled forms of loop Can still use NEXT and EXIT The above NEXT statement causes looping to continue with statements 1
CHAPTER 9
ASSERTION STATEMENT
ASSERT assertion_condition REPORT "reporting_message" SEVERITY severity_level;
MAKE SURE THAT assertion_condition IS TRUE, OTHERWISE REPORT "reporting_message" AND TAKE THE ACTION AT THIS severity_level;
MAKE SURE THAT false IS TRUE, OTHERWISE REPORT "reporting_message";
REPORT reporting_message SEVERITY severity_level;
Use assert to flag violations Use assert to report events Can be sequential or concurrent Severity: FAILURE ERROR WARNING NOTE
CHAPTER 9
18
ASSERTION STATEMENT
ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE; IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;
Conditions are checked only when process is activated Make sure that set='1' AND rst='1' does not happen Severity NOTE issues message
CHAPTER 9
19
ASSERTION STATEMENT
ASSERT Good conditions
REPORT Violation of good conditions
SEVERITY Level;
ASSERT NOT things_that_should_not_happen REPORT a_message_that_bad_things_have_happened SEVIRITY action_to_take;
Good conditions may be too many to list Good conditions = NOT (Bad conditions) Easier to use NOT of unwanted cases
CHAPTER 9
20
ASSERTION STATEMENT
clock setup time data hold time
Setup and Hold time checks use assert statement and signal attributes
Use ASSERT to check setup and hold ASSERT set_up_violation check REPORT... ASSERT hold_violation check REPORT...
CHAPTER 9
21
ASSERTION STATEMENT
Setup Check in English When (clock changes from zero to 1), if (data input has not been stable at least for the amount of the setup time), then a setup time violation has occurred.
Setup Check in VHDL (clock = '1' AND NOT clock'STABLE) AND (NOT data'STABLE (setup_time))
When the clock changes, check for stable data Check is placed after clock changes
CHAPTER 9
22
ASSERTION STATEMENT
Hold Check in English When (there is a change on the data input) if the (logic value on the clock is '1') and the (clock has got a new value more recent than the amount of hold time), then hold time violation has occurred.
Hold Check in VHDL (data'EVENT) AND (clock = '1') AND (NOT clock'STABLE (hold_time))
When data changes while clock is '1', check for stable clock Check is placed after data changes
CHAPTER 9
23
ASSERTION STATEMENT
ENTITY d_sr_flipflop IS GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS; setup, hold : TIME := 4 NS); PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT); BEGIN ASSERT (NOT (clk = '1' AND clk'EVENT AND NOT d'STABLE(setup) )) REPORT "setup time violation" SEVERITY WARNING; ASSERT (NOT (d'EVENT AND clk = '1' AND NOT clk'STABLE(hold) )) REPORT "Hold time violation" SEVERITY WARNING; END d_sr_flipflop; -ARCHITECTURE behavioral OF d_sr_flipflop IS SIGNAL state : BIT := '0'; BEGIN dff: PROCESS (rst, set, clk) BEGIN ASSERT (NOT (set = '1' AND rst = '1')) REPORT "set and rst are both 1" SEVERITY NOTE; IF set = '1' THEN state <= '1' AFTER sq_delay; ELSIF rst = '1' THEN state <= '0' AFTER rq_delay; ELSIF clk = '1' AND clk'EVENT THEN state <= d AFTER cq_delay; END IF; END PROCESS dff; q <= state; qb <= NOT state; END behavioral;
Using assertion statements for illegal Set-Reset combinations Setup and Hold time violations Concurrent and sequential assertion statements
CHAPTER 9
24
SEQUENTIAL WAIT STATEMENTS
WAIT FOR waiting_time; WAIT ON waiting_sensitivity_list; WAIT UNTIL waiting_condition; WAIT; WAIT FOR 0 NS; WAIT ON some_event UNTIL a_condition FOR some_time; WAIT UNTIL a_signal_is_true; Is the same as WAIT ON a_signal UNTIL signal_is_true; WAIT UNTIL expression_with_signal_and_variable_is_true; Is the same as WAIT ON the_signal UNTIL expression_is_true;
WAIT statements for flow control of sequential statements
Sequential statements; Used for handshaking and delay modeling WAIT FOR real_time; WAIT FOR; --"a long time" WAIT ON (event on a signal); WAIT UNTIL event makes condition true; WAIT; --"forever"
CHAPTER 9
25
ARCHITECTURE BEGIN PROCESS ... BEGIN WAIT ON (a, b, c); END PROCESS; END ARCHITECTURE;
ARCHITECTURE BEGIN PROCESS (a, b, c) ... BEGIN END PROCESS; END ARCHITECTURE;
A process with sensitivity behaves as A process with WAIT ON at the end
WAIT ON at the end is equivalent to using sensitivity list Cannot use WAIT in a process with sensitivity list WAIT suspends a Process
CHAPTER 9
26
Several examples will demonstrate WAIT statements in processes
A Moore 1011 detector Can use WAIT in a Process statement
CHAPTER 9
27

ENTITY moore_detector IS PORT (x, clk : IN BIT; z : OUT BIT); END moore_detector; -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset, got1, got10, got101, got1011); SIGNAL current : state := reset; BEGIN PROCESS BEGIN CASE current IS WHEN reset => WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got1; ELSE current <= reset; END IF; WHEN got1 => WAIT UNTIL clk = '1'; IF x = '0' THEN current <= got10; ELSE current <= got1; END IF; WHEN got10 => WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got101; ELSE current <= reset; END IF; WHEN got101 => WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got1011; ELSE current <= got10; END IF; WHEN got1011 => z <= '1'; WAIT UNTIL clk = '1'; IF x = '1' THEN current <= got1; ELSE current <= got10; END IF; END CASE; WAIT FOR 1 NS; z <= '0'; END PROCESS; END behavioral_state_machine;
VHDL Description of the 1011 Sequence Detector Using Process and Wait Statements Each choice corresponds to a state Each state can be independently timed, and clocked
CHAPTER 9
28
ENTITY moore_detector IS PORT (x, clk : IN BIT; z : OUT BIT); END moore_detector; -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset, got1, got10, got101, got1011); SIGNAL current : state := reset; BEGIN PROCESS BEGIN CASE current IS ... WHEN got1 => WAIT UNTIL clk = '1'; IF x = '0' THEN current <= got10; ELSE current <= got1; END IF; ...
WAIT FOR 1 NS;

z <= '0'; END PROCESS; END behavioral_state_machine;
END CASE;
WAIT for rising edge of clk Assign new state to current Wait for transaction on current Can use WAIT ON current 'TRANSACTION instead Timing check flexibility in each state
CHAPTER 9
29

ENTITY moore_detector IS PORT (x, clk : IN BIT; z : OUT BIT); END moore_detector; -ARCHITECTURE behavioral_state_machine OF moore_detector IS TYPE state IS (reset, got1, got10, got101, got1011); SIGNAL current : state := reset; BEGIN PROCESS (clk) BEGIN IF clk = '1' THEN CASE current IS WHEN reset => IF x = '1' THEN current <= got1; ELSE current <= reset; END IF; WHEN got1 => IF x = '0' THEN current <= got10; ELSE current <= got1; END IF; WHEN got10 => IF x = '1' THEN current <= got101; ELSE current <= reset; END IF; WHEN got101 => IF x = '1' THEN current <= got1011; ELSE current <= got10; END IF; WHEN got1011 => IF x = '1' THEN current <= got1; ELSE current <= got10; END IF; END CASE; END IF; END PROCESS; z <= '1' WHEN current = got1011 ELSE '0'; END behavioral_state_machine;
A simple state machine description Not much timing flexibility Allows a single clock But easy and covers most cases
CHAPTER 9
30
outputs next state Logic REG present state
Mealy machine detecting 101 Use a style that separates logic and register parts Also use an asynchronous reset
CHAPTER 9
31
ENTITY asynch_reset_detector IS PORT (x, r, clk : IN BIT; z : OUT BIT); END ENTITY; -ARCHITECTURE behavioral OF asynch_reset_detector IS TYPE state IS (a, b, c); SIGNAL nxt, present : state; BEGIN reg : PROCESS (clk, r) BEGIN IF r = '1' THEN present <= a; ELSIF (clk'EVENT AND clk = '1') THEN present <= nxt; END IF; END PROCESS; -logic : PROCESS (present, x) BEGIN z <= '0'; CASE present IS WHEN a => IF x = '0' THEN nxt <= a; ELSE nxt <= b; END IF; WHEN b => IF x = '0' THEN nxt <= c; ELSE nxt <= b; END IF; WHEN c => IF x = '0' THEN nxt <= a; ELSE nxt <= b; END IF; END CASE; IF present = c AND x = '1' THEN z <= '1'; END IF; END PROCESS; END behavioral;
VHDL description for a state machine with asynchronous reset Most synthesis tools accept this style Flexible in register part control
CHAPTER 9
32
... phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'; WAIT FOR 10 NS; c2 <= '1'; WAIT FOR 480 NS; c2 <= '0'; END PROCESS phase2; ...
Time
0.5
1.0
1.5
2.0
US
c1
c2 10NS 10NS
Generation of the second phase of a two phase non-overlapping clocking c2 is generated by phase2 process
CHAPTER 9
33

data_lines system A data_ready
valid data
accepted system B Process Data

System A: -- start the following when ready to send data_lines <= newly_prepared_data; data_ready <= '1'; WAIT UNTIL accepted = '1'; data_ready <= '0'; --can use data_lines for other purposes System B: -- start the following when ready to accept data WAIT UNTIL data_ready = '1'; accepted <= '1'; -- start processing the newly received data WAIT UNTIL data_ready = '0'; accepted <= '0';
Systems A & B talk A prepares data, B accepts data B releases A when data is picked
CHAPTER 9
34
SYSTEM I in_data
in_ready
16
out_data
in_received out_ready out_received
Use handshaking mechanism in an interface A prepares 4 bit data, B needs 16 bit data Create interface system I Talk to A to get data, talk to B to put data
CHAPTER 9
35
ENTITY system_i IS PORT (in_data : IN BIT_VECTOR (3 DOWNTO 0); out_data : OUT BIT_VECTOR (15 DOWNTO 0); in_ready, out_received : IN BIT; in_received, out_ready : OUT BIT); END system_i; -ARCHITECTURE waiting OF system_i IS SIGNAL buffer_full, buffer_picked : BIT := '0'; SIGNAL word_buffer : BIT_VECTOR (15 DOWNTO 0); BEGIN a_talk: PROCESS BEGIN ... -- Talk to A, collect 4 4-bit data, keep a count -- When ready, pass 16-bit data to b_talk ... END PROCESS a_talk; b_talk: PROCESS BEGIN ... -- Wait for 16-bit data from a_talk -- When data is received, send to B using proper handshaking ... END PROCESS b_talk; END waiting;
a_talk process & b_talk process also talk to each other Use buffer_full, buffer_picked, and word_buffer for a_talk and b_talk communication
CHAPTER 9
36

a_talk: PROCESS VARIABLE count : INTEGER RANGE 0 TO 4 := 0; BEGIN WAIT UNTIL in_ready = '1'; count := count + 1; CASE count IS WHEN 0 => NULL; WHEN 1 => word_buffer (03 DOWNTO 00) <= in_data; WHEN 2 => word_buffer (07 DOWNTO 04) <= in_data; WHEN 3 => word_buffer (11 DOWNTO 08) <= in_data; WHEN 4 => word_buffer (15 DOWNTO 12) <= in_data; buffer_full <= '1'; WAIT UNTIL buffer_picked = '1'; buffer_full <= '0'; count := 0; END CASE; in_received <= '1'; WAIT UNTIL in_ready = '0'; in_received <= '0'; END PROCESS a_talk; b_talk: PROCESS BEGIN IF buffer_full = '0' THEN WAIT UNTIL buffer_full = '1'; END IF; out_data <= word_buffer; buffer_picked <= '1'; WAIT UNTIL buffer_full = '0'; buffer_picked <= '0'; out_ready <= '1'; WAIT UNTIL out_received = '1'; out_ready <= '0'; END PROCESS b_talk;
a_talk gets data from A and talks to b_talk b_talk talks to a_talk and sends data to B
CHAPTER 9
37
clock
Arbiter
req ues t1 gra nt1 req ues t2 gra nt2
38
req ues t0 gra nt0
Bus arbiter interface Simplified for this first example Synchronized arbitration A request input stays asserted until granted A request input is granted only one clock cycle of bus use
CHAPTER 9
req ues t3 gra nt3
ENTITY arbiter IS PORT (request : IN BIT_VECTOR (3 DOWNTO 0); grant : BUFFER BIT_VECTOR (3 DOWNTO 0); clock : IN BIT); END arbiter; -ARCHITECTURE behavioral OF arbiter IS BEGIN wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS; FOR i IN request'RANGE LOOP IF request(i) = '1' THEN grant <= "0000"; grant (i) <= '1'; ELSE grant (i) <= '0'; END IF; END LOOP; END IF; WAIT ON clock; END PROCESS wait_cycle; END behavioral;
Bus arbiter description Check all requests after the falling edge of the clock Because of the 20 NS wait, process sensitivity cannot be used
CHAPTER 9
39
ENTITY arbtest IS END arbtest; -ARCHITECTURE io OF arbtest IS SIGNAL clk : BIT; SIGNAL r, g : BIT_VECTOR (3 DOWNTO 0); CONSTANT t : TIME := 1 US; TYPE time_array IS ARRAY (3 DOWNTO 0) OF TIME; CONSTANT delays : time_array := (4 US, 3 US, 15 US, 8 US); BEGIN arb : ENTITY WORK.arbiter PORT MAP (r, g, clk); clk <= NOT clk AFTER t / 2 WHEN NOW < 40 US ELSE clk; sources : FOR i IN r'RANGE GENERATE PROCESS BEGIN WAIT FOR delays (i); r(i) <= '1'; WAIT UNTIL g(i) = '1'; WAIT UNTIL clk = '0'; r(i) <= '0'; END PROCESS; END GENERATE; END io;
Testing the arbiter Four processes for generating data are generated The time_array constant specifies timing requests coming from a source
CHAPTER 9
40
S2P
da tar ea dy ov err un fra me _e rro r pa ral lel _o ut
serial
rec eiv ed
A 10 bit frame reading begins
start bit
data bits
stop bit
Another example using WAIT statements Serial_to_parallel interface RS232 frame with one start bit and one stop bit Framing error, if stop bit is not seen Overrun error if start bit appears too soon
CHAPTER 9
41

ENTITY serial2parallel IS GENERIC (bps : INTEGER); PORT (serial, received : IN qit; dataready : BUFFER qit; overrun, frame_error : OUT qit; parallel_out : BUFFER qit_vector (7 DOWNTO 0)); END serial2parallel; -ARCHITECTURE waiting OF serial2parallel IS BEGIN collect : PROCESS --VARIABLE buff : qit_vector (7 DOWNTO 0); CONSTANT half_bit : TIME := (1E6/REAL(bps))/2.0 * 1 US; CONSTANT full_bit : TIME := (1E6/REAL(bps)) * 1 US; BEGIN WAIT UNTIL serial = '0'; WAIT FOR half_bit; FOR count IN 0 TO 7 LOOP WAIT FOR full_bit; buff (count) := serial; END LOOP; WAIT FOR full_bit; IF serial = '0' THEN too_fast : PROCESS frame_error <= '1'; BEGIN WAIT UNTIL serial = '1'; IF dataready = '1' THEN ELSE WAIT UNTIL serial = '0'; frame_error <= '0'; IF dataready = '1' THEN dataready <= '1'; overrun <= '1'; parallel_out <= buff; END IF; WAIT UNTIL received = '1'; ELSE WAIT UNTIL received = '0'; overrun <= '0'; dataready <= '0'; END IF; END IF; WAIT ON dataready; END PROCESS collect; END PROCESS too_fast; END waiting;
Serial2parallel VHDL description Two concurrent processes One waits for prepared data to be picked up (collect), while The other waits for untimely serial data to arrive (too_fast) WAIT statements are used in both processes
CHAPTER 9
FORMATTED ASCII I/O OPERATIONS
TEXTIO package is in the STD library TEXTIO contains: LINE type, a pointer to STRING TEXT file type, of CHARACTER type INPUT, OUTPUT files for standard device IO READLINE procedure, to read a line from file READ procedure, to read data from a line a line WRITE procedure, to write data into a WRITELINE procedure, to write line to file READ procedure, to read data from a line a line ENDFILE function, to check the end of a file
Examples will demonstrate TEXTIO package and its applications
Only CHARACTERS are handled All predefined standard types are converted to CHARACTERS Subprograms are overloaded for all standard types
CHAPTER 9
43
VARIALE I : LINE; FILE f : TEXT; FILE f : TEXT IS input.txt; FILE f : TEXT OPEN READ_MODE IS input.txt;
FILE_OPEN (f, input.txt, READ_MODE); FILE_OPEN (f, output.txt, WRITE_MODE); FILE_OPEN (f, output.txt, APPEND_MODE); FILE_CLOSE (f);
READLINE(f, l); -- read a line of file f into buffer l READ(l, v, ...); -- reads a value v of its type from l
WRITE(l, v, ...) -- writes the value v to LINE l WRITELINE(f, l) -- writes l to file f
ENDFILE(f) -- returns TRUE if the end of f
READ and WRITE procedures are valid for: BIT, BIT_VECTOR, BOOLEAN, CHARACTER, INTEGER, REAL, STRING, and TIME Other parameters of these procedures include orientation, size, and unit if v is of type TIME
CHAPTER 9
44
USE STD.TEXTIO.ALL; ... TYPE state IS (reset, got1, got10, got101); TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state; FUNCTION one_of (sources : state_vector) RETURN state IS
VARIABLE l : LINE; FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty";

BEGIN
FOR i IN sources'RANGE LOOP WRITE (l, state'IMAGE(sources(i)), LEFT, 7); END LOOP; WRITELINE (flush, l);
RETURN sources(sources'LEFT); END one_of;
A resolution function that writes its active drivers each time it is called New code is highlighted Unix device tty is the standard output Can use OUTPUT, defined in VHDL for the standard output INPUT and OUTPUT work in all operating systems
PROCEDURE display (SIGNAL value1, value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty"; VARIABLE filler : STRING (1 TO 3) := " .."; VARIABLE l : LINE; BEGIN WRITE (l, NOW, RIGHT, 8, NS); IF value1'EVENT AND value2'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, value2, RIGHT, 3); ELSIF value1'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, filler, LEFT, 0); ELSE WRITE (l, filler, LEFT, 0); WRITE (l, value2, RIGHT, 3); END IF; WRITELINE (flush, l); END display;
A display procedure for writing time and events New values are listed Filler is used for signal values that do not change
CHAPTER 9
46
PROCEDURE display (SIGNAL value1, value2 : BIT) IS FILE flush : TEXT OPEN WRITE_MODE IS "/dev/tty"; VARIABLE filler : STRING (1 TO 3) := " .."; VARIABLE l : LINE; BEGIN WRITE (l, NOW, RIGHT, 8, NS); IF value1'EVENT AND value2'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, value2, RIGHT, 3); ELSIF value1'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, filler, LEFT, 0); ELSE WRITE (l, filler, LEFT, 0); WRITE (l, value2, RIGHT, 3); END IF; WRITELINE (flush, l); END display; USE STD.TEXTIO.ALL; ENTITY two_phase_clock IS END two_phase_clock; -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'; BEGIN SIGNAL c2 : BIT := '0';
display (c1, c2);

END input_output;
c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1; phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'; WAIT FOR 10 NS; c2 <= '1'; WAIT FOR 480 NS; c2 <= '0'; END PROCESS phase2;
Call the display procedure anytime a clock phase changes This procedure is also called once at the beginning of simulation
CHAPTER 9
47
PACKAGE displaying IS
PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT);

END displaying; -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT) IS VARIABLE filler : STRING (1 TO 3) := " .."; VARIABLE l : LINE; BEGIN WRITE (l, NOW, RIGHT, 8, NS); IF value1'EVENT AND value2'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, value2, RIGHT, 3); ELSIF value1'EVENT THEN WRITE (l, value1, RIGHT, 3); WRITE (l, filler, LEFT, 0); ELSE WRITE (l, filler, LEFT, 0); WRITE (l, value2, RIGHT, 3); END IF; WRITELINE (flush, l); END display; END displaying;
A procedure for writing in an already open file A file of type TEXT is passed to this procedure This goes in our new displaying package
CHAPTER 9
48
USE STD.TEXTIO.ALL; PACKAGE displaying IS PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT); END displaying; -PACKAGE BODY displaying IS PROCEDURE display (SIGNAL value1, value2 : BIT; FILE flush : TEXT) IS ... END display; END displaying;
USE STD.TEXTIO.ALL; USE WORK.displaying.ALL; ENTITY two_phase_clock IS END two_phase_clock; -ARCHITECTURE input_output OF two_phase_clock IS SIGNAL c1 : BIT := '1'; SIGNAL c2 : BIT := '0';
FILE data : TEXT OPEN WRITE_MODE IS "clock.out";

BEGIN
display (c1, c2, data);

END input_output;
c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1; phase2: PROCESS BEGIN WAIT UNTIL c1 = '0'; WAIT FOR 10 NS; c2 <= '1'; WAIT FOR 480 NS; c2 <= '0'; END PROCESS phase2;
Passing an open file to a procedure File declaration takes place in the declarative part of an architecture File remains open after being written into Writing can continue elsewhere
CHAPTER 9
49
0 500 510 990 1000 1500 1510 1990 2000 2500 2510 2990 3000 3500 3510 3990 4000
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
.. 0 .. .. 1 0 .. .. 1 0 .. .. 1 0 .. .. 1
0 .. 1 0 .. .. 1 0 .. .. 1 0 .. .. 1 0 ..
Output file generated by the input_output architecture File closes at the end of simulation
CHAPTER 9
50

c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US USE STD.TEXTIO.ALL; ELSE ENTITY two_phase_clock IS END two_phase_clock; c1; phase2: PROCESS -BEGIN ARCHITECTURE input_output OF two_phase_clock WAIT UNTIL c1 = '0'; IS WAIT FOR 10 NS; SIGNAL c1 : BIT := '1'; SIGNAL c2 : BIT := '0'; c2 <= '1'; SIGNAL print_tick : BIT := '0'; WAIT FOR 480 NS; CONSTANT print_resolution : TIME := 5 NS; c2 <= '0'; BEGIN END PROCESS phase2; print_tick <= NOT print_tick AFTER print_resolution WHEN NOW <= 2 US ELSE UNAFFECTED;
FILE flush : TEXT OPEN WRITE_MODE IS "clock4.out"; VARIABLE header : STRING (1 TO 18) := " c1 c2 "; VARIABLE l : LINE; PROCEDURE append_wave_slice (SIGNAL s : BIT) IS VARIABLE lo_value : STRING (1 TO 3) := "| "; BEGIN VARIABLE hi_value : STRING (1 TO 3) := " |"; IF NOW = 0 US THEN VARIABLE lo_to_hi : STRING (1 TO 3) := ".-+"; WRITE (l, header, LEFT, 0); VARIABLE hi_to_lo : STRING (1 TO 3) := "+-."; WRITELINE (flush, l); BEGIN END IF; WRITE (l, NOW, RIGHT, 8, NS); IF s'LAST_EVENT < print_resolution AND s'LAST_VALUE /= s THEN append_wave_slice (c1); IF s = '1' THEN WRITE (l, lo_to_hi, RIGHT, 5); append_wave_slice (c2); ELSE WRITE (l, hi_to_lo, RIGHT, 5); WRITELINE (flush, l); END IF; END PROCESS writing; ELSE END input_output; IF s = '1' THEN WRITE (l, hi_value, RIGHT, 5); ELSE WRITE (l, lo_value, RIGHT, 5); END IF; END IF; END PROCEDURE append_wave_slice;
writing: PROCESS (print_tick, c1, c2)
Generating an ASCII plot file 5 NS print resolution reports of the two-phase clock description Process wakes up, calls the append_wave_slice procedure Buffer l is visible in the procedure, appending is done to this line
CHAPTER 9
51
c1 480 485 490 495 500 505 510 510 515 520 525 ... ns ns ns ns ns ns ns ns ns ns ns | | | | +-. | | | | | |
c2 | | | | | | | .-+ | | |
Plot generated by the ploting process Plotting is activated every 5 NS Write " |" for '1'; "| " for '0' Write "+-." for 1 to 0 Write ".-+" for 0 to 1
CHAPTER 9
52
MSI BASED DESIGN
8 data_in clk clear_bar load_bar count_in 4 sequential comparator
4 count
Produces modulo-16 count of consecutive matching data
Closing the chapter, will present a top-down design with MSI parts
Sequential comparator circuit Design based on MSI parts 74LS377, 74LS85, 74LS163 Assume these parts are available
CHAPTER 9
53
MSI BASED DESIGN
sequential comparator
8-bit register
8-bit comparator
4-bit counter
4-bit comparator
4-bit comparator
Partition the circuit into smaller components Partition until library components or synthesizable parts are reached Will use top-down technique in designing a CPU in Chapter 10
CHAPTER 9
54
MSI BASED DESIGN
74LS377
74LS85
74LS163 5CT=0 CTRDIV16 M1 M2 3CT=15 G3 G4 C5/2,3,4+
GI 1C2 < = >
P P<Q P=Q P>Q Q
2D
1, 5D
[1] [2] [4] [8]
Standard MSI parts Register, comparator, counter
CHAPTER 9
55
MSI BASED DESIGN
USE WORK.basic_utilities.ALL; ENTITY ls85_comparator IS GENERIC (prop_delay : TIME := 10 NS); PORT (a, b : IN qit_vector (3 DOWNTO 0); gt, eq, lt : IN qit; a_gt_b, a_eq_b, a_lt_b : OUT qit); END ls85_comparator; -ARCHITECTURE behavioral OF ls85_comparator IS BEGIN PROCESS (a, b, gt, eq, lt) BEGIN IF a > b THEN a_gt_b <= '1' AFTER prop_delay; a_eq_b <= '0' AFTER prop_delay; a_lt_b <= '0' AFTER prop_delay; ELSIF a < b THEN a_gt_b <= '0' AFTER prop_delay; a_eq_b <= '0' AFTER prop_delay; a_lt_b <= '1' AFTER prop_delay; ELSIF a = b THEN a_gt_b <= gt AFTER prop_delay; a_eq_b <= eq AFTER prop_delay; a_lt_b <= lt AFTER prop_delay; END IF; END PROCESS; END behavioral;
74LS85, four bit comparator Relational operators, ordering for array operands Default delays can be configured later
CHAPTER 9
56
MSI BASED DESIGN
USE WORK.basic_utilities.ALL; ENTITY ls377_register IS GENERIC (prop_delay : TIME := 7 NS); PORT (clk, g_bar : IN qit; d8 : IN qit_vector (7 DOWNTO 0); q8 : OUT qit_vector (7 DOWNTO 0)); END ls377_register; -ARCHITECTURE dataflow OF ls377_register IS SIGNAL GUARD : BOOLEAN; BEGIN GUARD <= NOT clk'STABLE AND clk = '1' AND (g_bar = '0'); q8 <= GUARDED d8 AFTER prop_delay; END dataflow;
74LS377, clocked register Default delays can be used or reconfigured
CHAPTER 9
57
MSI BASED DESIGN

USE WORK.basic_utilities.ALL; ENTITY ls163_counter IS GENERIC (prop_delay : TIME := 12 NS); PORT (clk, clr_bar, ld_bar, enp, ent : IN qit; abcd : IN qit_vector (3 DOWNTO 0); q_abcd : OUT qit_vector (3 DOWNTO 0); rco : OUT qit); END ls163_counter; -ARCHITECTURE behavioral OF ls163_counter IS BEGIN counting : PROCESS (clk) VARIABLE internal_count : qit_vector (3 DOWNTO 0) := "0000"; BEGIN IF (clk = '1') THEN IF (clr_bar = '0') THEN internal_count := "0000"; ELSIF (ld_bar = '0') THEN internal_count := abcd; ELSIF (enp = '1' AND ent = '1') THEN internal_count := inc (internal_count); END IF; IF (internal_count = "1111" AND ent = 1) THEN rco <= '1' AFTER prop_delay; ELSE rco <= '0'; END IF; q_abcd <= internal_count AFTER prop_delay; END IF; END PROCESS counting; END behavioral;
74LS163, four bit synchronous counter Default delays can be overwritten
CHAPTER 9
58
MSI BASED DESIGN
LS377_register(behavioral) clk clear_bar load_bar data_in 8 4 8 clk d8 reg: d_register 4 q8 4
standard sequential comparator(structural)
LS163_counter(behavioral)
a b gt eq lt
cmp_hi: comparator a_gt_b a_eq_b a_lt_b clk clr_bar load_bar enp ent abcd cnt: counter rco 4 q_abcd count
g_bar prop_delay
prop_delay
4 a b count_in gt eq lt 4
cmp_lo: comparator a_gt_b a_eq_b prop_delay a_lt_b
prop_delay
15NS
18NS
LS85_comparator(behavioral)
22NS
Design is based on available parts Configure to use LS library, specify delay
CHAPTER 9
59
MSI BASED DESIGN

USE WORK.basic_utilities.ALL; ENTITY sequential_comparator IS PORT (data_in : IN qit_vector (7 DOWNTO 0); clk, clear_bar, load_bar : IN qit; count_in : IN qit_vector (3 DOWNTO 0); count : OUT qit_vector (3 DOWNTO 0) ); BEGIN ASSERT NOT ((clk='0' AND NOT clk'STABLE) AND NOT clk'DELAYED'STABLE (1 US)) REPORT "Minimum Clock Width Violation" SEVERITY WARNING; END sequential_comparator; -ARCHITECTURE structural OF sequential_comparator IS COMPONENT d_register PORT (clk, g_bar : IN qit; d8 : IN qit_vector (7 DOWNTO 0); q8 : OUT qit_vector (7 DOWNTO 0)); END COMPONENT; COMPONENT comparator PORT (a, b : IN qit_vector (3 DOWNTO 0); gt, eq, lt : IN qit; a_gt_b, a_eq_b, a_lt_b : OUT qit); END COMPONENT; COMPONENT counter PORT (clk, clr_bar, ld_bar, enp, ent : IN qit; abcd : IN qit_vector (3 DOWNTO 0); q_abcd : OUT qit_vector (3 DOWNTO 0); rco : OUT qit); END COMPONENT; SIGNAL gnd : qit := '0'; SIGNAL vdd : qit := '1'; SIGNAL old_data : qit_vector (7 DOWNTO 0); SIGNAL compare_out : qit; SIGNAL gt_i, eq_i, lt_i : qit; BEGIN reg: d_register PORT MAP (clk, gnd, data_in, old_data); cmp_lo: comparator PORT MAP (data_in (3 DOWNTO 0), old_data (3 DOWNTO 0), gnd, vdd, gnd, gt_i, eq_i, lt_i); cmp_hi: comparator PORT MAP (data_in (7 DOWNTO 4), old_data (7 DOWNTO 4), gt_i, eq_i, lt_i, OPEN, compare_out, OPEN); cnt: counter PORT MAP (clk, clear_bar, load_bar, vdd, compare_out, count_in, count, OPEN); END structural;
Design is based on available parts Assert statement in the entity declaration Configure to use LS library, specify delay
CHAPTER 9
60
MSI BASED DESIGN
USE WORK.ALL; CONFIGURATION standard OF sequential_comparator IS FOR structural FOR reg : d_register USE ENTITY WORK.ls377_register (dataflow) GENERIC MAP (prop_delay => 15 NS); END FOR; FOR ALL : comparator USE ENTITY WORK.ls85_comparator (behavioral) GENERIC MAP (prop_delay => 18 NS); END FOR; FOR cnt : counter USE ENTITY WORK.ls163_counter (behavioral) GENERIC MAP (prop_delay => 22 NS); END FOR; END FOR; END standard;
Configuring the structural architecture of the sequential_comparator Configuration declaration binds to 74LS parts Generic values overwrite those of the 74LS parts
CHAPTER 9
61
MSI BASED DESIGN
USE WORK.basic_utilities.ALL; ENTITY test_sequential_comparator IS END test_sequential_comparator; -ARCHITECTURE input_output OF test_sequential_comparator IS COMPONENT seq_comp PORT (data_in : IN qit_vector (7 DOWNTO 0); clk, clear_bar, load_bar : IN qit; count_in : IN qit_vector (3 DOWNTO 0); count : OUT qit_vector (3 DOWNTO 0) ); END COMPONENT; FOR mfi : seq_comp USE CONFIGURATION WORK.standard; SIGNAL data : qit_vector (7 DOWNTO 0); SIGNAL ck, cl_bar, ld_bar : qit; SIGNAL cnt : qit_vector (3 DOWNTO 0); SIGNAL cnt_out : qit_vector (3 DOWNTO 0); BEGIN ck <= NOT ck AFTER 2 US WHEN NOW <= 70 US ELSE ck; cl_bar <= '1', '0' AFTER 60 US; ld_bar <= '1', '0' AFTER 50 US, '1' AFTER 55 US; cnt <= "1111", "1011" AFTER 40 US, "0111" AFTER 55 US;
data <= "00000000", "01110111" AFTER 3 US, "10101100" AFTER 5 US, "01010100" AFTER 25 US;
mfi : seq_comp PORT MAP (data, ck, cl_bar, ld_bar, cnt, cnt_out); END input_output;
Testbench verifies behavior Configuration specification associates mfi: seq_comp with the standard configuration declaration
CHAPTER 9
62
SUMMARY This chapter presented descriptions of hardware at the behavioral level and discussed how a process statement can be used to describe the main functionality of a module. In the first part of the chapter, syntax and
semantics for various forms of this construct were described. We then showed how process statements are used to describe controlling hardware, handshaking, and file I/O. Various forms of wait statements were
extensively used in these descriptions. Although behavioral level constructs of VHDL provide a convenient method of describing very complex hardware, a hardware designer can completely describe a digital circuit without having to use these constructs. Behavioral descriptions can be read and understood by non-technical managers and others who are not very familiar with VHDL.
End Of Chapter 9
CHAPTER 9
63
CHAPTER 10 CPU MODELING AND DESIGN

10.1 DEFINING A COMPREHENSIVE EXAMPLE 10.2 PARWAN CPU 10.2.1 Memory Organization of Parwan 10.2.2 Instruction Set 10.2.3 Instruction Format 10.2.4 Programming in Parwan Assembly 10.3 BEHAVIORAL DESCRIPTION OF PARWAN 10.3.1 Timing and Clocking 10.3.2 Packages 10.3.3 Interface Description of Parwan 10.3.4 Parwan Behavioral Architecture 10.4 PARWAN BUSSING STRUCTURE 10.4.1 Interconnection of Components 10.4.2 Global View of Parwan Components 10.4.3 Instruction Execution 10.5 DATAFLOW DESCRIPTION OF PARWAN 10.5.1 Data and Control Partitioning 10.5.2 Timing of Data and Control Events 10.5.3 General Description Methodology 10.5.4 Description of Components 10.5.5 Data Section of Parwan 10.5.6 Control Section of Parwan 10.5.7 Wiring Data and Control Sections 10.6 A TEST BENCH FOR THE PARWAN CPU 10.7 A MORE REALISTIC PARWAN 10.7.1 CPU Control Signals 10.7.2 Synthesizability 10.7.3 Hardware Modifications 10.8 SUMMARY
CHAPTER 10
DEFINING A COMPREHENSIVE EXAMPLE
MAR
PC IR SR AC ALU SHU Controller
Will define a CPU describe it in VHDL, and show its hardware details
General Layout of Parwan PARWAN; PAR_1; A Reduced Processor Simple 8-bit CPU; 8-bit Data; 12-bit Address Primarily designed for educational purposes Includes most common instructions
CHAPTER 10
PARWAN CPU
7 6 1 1 1 0 0 9 Page 0 8 0 0 7 6 0 5 0 4 0 0 3 2 0 1 0 0 0:00 - 0:FF 1:00 - 1:FF 2:00 - 2:FF
MEMORY: 5 4 3 2 page 0 . . page 1 . . page 2 . .
Offset
E:00 - E:FF F:00 - F:FF
page 14 . . page 15 . .
Page and Offset Parts of Parwan addresses Memory divided into pages Pages of 256 bytes Address has page and offset part Uses memory mapped IO
CHAPTER 10
PARWAN CPU
FULL Address; (12 bits) direct/indirect LDA, AND, ADD, SUB, JMP, STA
PAGE Address, (8 bit) JSR, BRA_V, BRA_C, BRA_Z, BRA_N
NO Address NOP, CLA, CMA, CMC, ASL, ASR
Three groups of instructions Full Address instructions include page and offset Page address instructions include offset No Address instructions occupy a single byte
CHAPTER 10
Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR
Brief Description Load AC w/(loc) AND AC w/(loc) Add (loc) to AC Sub (loc) from AC Jump to adr Store AC in loc Subroutine to tos Branch to adr if V Branch to adr if C Branch to adr if Z Branch to adr if N No operation Clear AC Complement AC Complement carry Arith shift left Arith shift right
Address Bits 12 12 12 12 12 12 8 8 8 8 8 -
Address Scheme FULL FULL FULL FULL FULL FULL PAGE PAGE PAGE PAGE PAGE NONE NONE NONE NONE NONE NONE
Indirect Address YES YES YES YES YES YES NO NO NO NO NO NO NO NO NO NO NO
Flags Use -------c--c----------v---c---z---n ----------c--------
Flags Set --zn --zn vczn vczn -----------------------------zn -c-vczn --zn
Summary of Parwan instructions. Load and store operations Arithmetic & logical operations jmp and branch instructions
CHAPTER 10
PARWAN CPU
Instruction Mnemonic LDA loc AND loc ADD loc SUB loc JMP adr STA loc JSR tos BRA_V adr BRA_C adr BRA_Z adr BRA_N adr NOP CLA CMA CMC ASL ASR
Opcode Bits 765 000 001 010 011 100 101 110 111 111 111 111 111 111 111 111 111 111
D/I Bit 4 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 0 0 0 0 0 0
Bits 3210 Page adr Page adr Page adr Page adr Page adr Page adr ---1000 0100 0010 0001 0000 0001 0010 0100 1000 1001
Parwan instruction opcodes CPU contains V C Z N flags Instructions use and/or influence these flags
CHAPTER 10
PARWAN CPU
influence
ADD, SUB, ASL ADD, SUB, ASL, CMC ADD, SUB, LDA, AND, CMA, ASL, ASR ADD, SUB, LDA, AND, CMA, ASL, ASR
use V C Z N
BRA_V BRA_C, ADD, SUB, CMC BRA_Z BRA_N
Arithmetic instructions influence all flags Branch instructions use corresponding flags Shift instructions influence all flags
CHAPTER 10
complete address pg: loc opc page
pg: loc+1
offset
Addressing in full-address instructions Full address instructions use two bytes Right hand side of first byte is page Second byte contains offset Bit 4 is direct/indirect [0/1] indicator
CHAPTER 10
PARWAN CPU
complete address pg: loc jsr or branch
pg: loc+1
offset
Addressing in page-address instructions Page address instructions use two bytes All of first byte is used by opcode Page part of address uses current page Second byte is the offset
CHAPTER 10
PARWAN CPU
MEMORY
...
BRA_C 6A
5:0D 5:0E 5:0F
11110100 6A
...
BRANCH TO 6A if carry is set
c=0 : Next instruction from 5:0f c=1 : Next instruction from 5:6A
Branching is done within current page only A branch instruction
CHAPTER 10
10
PARWAN CPU
MEMORY PC-> 5:11 5:12 5:13
MEMORY 5:11 5:12 5:13
...
JSR 3 3 INSTR AFTER JSR
...
JSR 3 3 INSTR AFTER JSR
... ...
5:33 5:34 00000000 SUBROUTINE CODE
... ...
5:33 PC-> 5:34
...
1 3 SUBROUTINE CODE
...
5:55 5:56 5:57
JMP Indirect 3 3 B E F O R E J S R
5:55 5:56 5:57
JMP Indirect 3 3
...
A F T E R J S R
An example for the execution of jsr Memory and pc, before and after jsr Store jsr return address at tos Begin subroutine at tos+1 Use indirect jmp to tos for return from subroutine
CHAPTER 10
11
PARWAN CPU
Indirect address
Actual address
Data
Any page and offset
Same page Indirecting effects offset
operand
0:25
opc
6 6:1F
1 8
0:26
3 5
6:35 1 F
An example for indirect addressing in Parwan. Indirect addressing affects offset only To obtain actual address full addressing is used To obtain data page addressing is used
CHAPTER 10
12
PARWAN CPU
0:15 0:16 0:17 0:19 0:1B 0:1D 0:1F 0:21 0:23 0:25 0:27 0:29 0:2B 0:2D
cla asl add, i sta 4:03 lda 4:00 add 4:02 sta 4:00 lda 4:01 sub 4:02 bra_z sta 4:01 lda 4:03 jmp 0:17 nop
-- load 25 in 4:00 -- load 10 in 4:01 -- load 01 in 4:02 -- clear accumulator -- clears carry 4:00 -- add bytes -- store partial sum -- load pointer -- increment pointer -- store pointer back -- load count -- decrement count :2D -- end if zero count -- store count back -- get partial sum -- go for next byte -- adding completed
An example program for Parwan CPU A program to add 10 bytes Use location 4:00 for data pointer Use location 4:01 for counter Constant 1 in 4:02 is used for +1 and -1
CHAPTER 10
13
BEHAVIORAL DESCRIPTION OF PARWAN
LIBRARY cmos; USE cmos.basic_utilities.ALL; -LIBRARY par_library; USE par_library.par_utilities.ALL; USE par_library.par_parameters.ALL; -ENTITY par_central_processing_unit IS ... END par_central_processing_unit; -ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN END behavioral;
Coding for the behavioral description of Parwan will be presented.
Packages used will be described A single component will describe all of Parwan
CHAPTER 10
14

LIBRARY cmos; USE cmos.basic_utilities.ALL; -PACKAGE par_utilities IS FUNCTION "XOR" (a, b : qit) RETURN qit ; FUNCTION "AND" (a, b : qit_vector) RETURN qit_vector; FUNCTION "OR" (a, b : qit_vector) RETURN qit_vector; FUNCTION "NOT" (a : qit_vector) RETURN qit_vector; -SUBTYPE nibble IS qit_vector (3 DOWNTO 0); SUBTYPE byte IS qit_vector (7 DOWNTO 0); SUBTYPE twelve IS qit_vector (11 DOWNTO 0); -SUBTYPE wired_nibble IS wired_qit_vector (3 DOWNTO 0); SUBTYPE wired_byte IS wired_qit_vector (7 DOWNTO 0); SUBTYPE wired_twelve IS wired_qit_vector (11 DOWNTO 0); -SUBTYPE ored_nibble IS ored_qit_vector (3 DOWNTO 0); SUBTYPE ored_byte IS ored_qit_vector (7 DOWNTO 0); SUBTYPE ored_twelve IS ored_qit_vector (11 DOWNTO 0); -CONSTANT zero_4 : nibble := "0000"; CONSTANT zero_8 : byte := "00000000"; CONSTANT zero_12 : twelve := "000000000000"; -FUNCTION add_cv (a, b : qit_vector; cin : qit) RETURN qit_vector; FUNCTION sub_cv (a, b : qit_vector; cin : qit) RETURN qit_vector; -FUNCTION set_if_zero (a : qit_vector) RETURN qit; -END par_utilities;
Declarations of par_utilities package of par_library Machine descriptions require utilities Use basic_utilities Additional utilities are included in par_utilities
CHAPTER 10
15

PACKAGE BODY par_utilities IS FUNCTION "XOR" (a, b : qit) RETURN qit IS CONSTANT qit_xor_table : qit_2d := ( ('0','1','1','X'), ('1','0','0','X'), ('1','0','0','X'), ('X','X','X','X')); BEGIN RETURN qit_xor_table (a, b); END "XOR"; FUNCTION "AND" (a,b : qit_vector) RETURN qit_vector IS VARIABLE r : qit_vector (a'RANGE); BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) AND b(i); END LOOP loop1; RETURN r; END "AND"; -FUNCTION "OR" (a,b: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE); BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := a(i) OR b(i); END LOOP loop1; RETURN r; END "OR"; -FUNCTION "NOT" (a: qit_vector) RETURN qit_vector IS VARIABLE r: qit_vector (a'RANGE); BEGIN loop1: FOR i IN a'RANGE LOOP r(i) := NOT a(i); END LOOP loop1; RETURN r; END "NOT";
Body of par_utilities package of par_library library Define XOR in qit Overload logical operators with qit_vector
CHAPTER 10
16

FUNCTION add_cv (a, b : qit_vector; cin : qit) RETURN qit_vector IS VARIABLE r, c: qit_vector (a'LEFT + 2 DOWNTO 0); -- extra r bits : msb: overflow, next to msb: carry VARIABLE a_sign, b_sign: qit; BEGIN a_sign := a(a'LEFT); b_sign := b(b'LEFT); r(0) := a(0) XOR b(0) XOR cin; c(0) := ((a(0) XOR b(0)) AND cin) OR (a(0) AND b(0)); FOR i IN 1 TO (a'LEFT) LOOP r(i) := a(i) XOR b(i) XOR c(i-1); c(i) := ((a(i) XOR b(i)) AND c(i-1)) OR (a(i) AND b(i)); END LOOP; r(a'LEFT+1) := c(a'LEFT); IF a_sign = b_sign AND r(a'LEFT) /= a_sign THEN r(a'LEFT+2) := '1'; --overflow ELSE r(a'LEFT+2) := '0'; END IF; RETURN r; END add_cv; FUNCTION sub_cv (a, b : qit_vector; cin : qit) RETURN qit_vector IS VARIABLE not_b : qit_vector (b'LEFT DOWNTO 0); VARIABLE not_c : qit; VARIABLE r : qit_vector (a'LEFT + 2 DOWNTO 0); BEGIN not_b := NOT b; not_c := NOT cin; r := add_cv (a, not_b, not_c); RETURN r; END sub_cv; FUNCTION set_if_zero (a : qit_vector) RETURN qit IS VARIABLE zero : qit := '1'; BEGIN FOR i IN a'RANGE LOOP IF a(i) /= '0' THEN zero := '0'; EXIT; END IF; END LOOP; RETURN zero; END set_if_zero; END par_utilities;
Body of the par_utilities package of par_library library add_cv adds its operands creates c and v bits Put overflow in leftmost result bit Put carry to the right of overflow
CHAPTER 10
17
LIBRARY cmos; USE cmos.basic_utilities.ALL; -PACKAGE par_parameters IS CONSTANT single_byte_instructions : qit_vector (3 DOWNTO 0) := "1110"; CONSTANT cla : qit_vector (3 DOWNTO 0) := "0001"; CONSTANT cma : qit_vector (3 DOWNTO 0) := "0010"; CONSTANT cmc : qit_vector (3 DOWNTO 0) := "0100"; CONSTANT asl : qit_vector (3 DOWNTO 0) := "1000"; CONSTANT asr : qit_vector (3 DOWNTO 0) := "1001"; CONSTANT jsr : qit_vector (2 DOWNTO 0) := "110"; CONSTANT bra : qit_vector (3 DOWNTO 0) := "1111"; CONSTANT indirect : qit := '1'; CONSTANT jmp : qit_vector (2 DOWNTO 0) := "100"; CONSTANT sta : qit_vector (2 DOWNTO 0) := "101"; CONSTANT lda : qit_vector (2 DOWNTO 0) := "000"; CONSTANT ann : qit_vector (2 DOWNTO 0) := "001"; CONSTANT add : qit_vector (2 DOWNTO 0) := "010"; CONSTANT sbb : qit_vector (2 DOWNTO 0) := "011"; CONSTANT jsr_or_bra : qit_vector (1 DOWNTO 0) := "11"; END par_parameters;
Declaration of par_parameters Package of par_library Assign appropriate names to opcodes par_parameters is used for readability
CHAPTER 10
18
LIBRARY cmos; USE cmos.basic_utilities.ALL; -LIBRARY par_library; USE par_library.par_utilities.ALL; USE par_library.par_parameters.ALL; -ENTITY par_central_processing_unit IS GENERIC (read_high_time, read_low_time, write_high_time, write_low_time : TIME := 2 US; cycle_time : TIME := 4 US); PORT (clk : IN qit; interrupt : IN qit; read_mem, write_mem : OUT qit; databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve ); END par_central_processing_unit;
Interface description of Parwan
CHAPTER 10
19

ARCHITECTURE behavioral OF par_central_processing_unit IS BEGIN PROCESS
Declare necessary variables; Figure 10.16.
BEGIN IF interrupt = '1' THEN
Handle interrupt; Figure 10.17.

ELSE -- no interrupt
Read first byte into byte1, increment pc; Figure 10.18.

IF byte1 (7 DOWNTO 4) = single_byte_instructions THEN
Execute single-byte instructions; Figure 10.19.

ELSE -- two-byte instructions
Read second byte into byte2, increment pc; Figure 10.20.

IF byte1 (7 DOWNTO 5) = jsr THEN
Execute jsr instruction, byte2 has address; Figure 10.21.

ELSIF byte1 (7 DOWNTO 4) = bra THEN
Execute bra instructions, address in byte2; Figure 10.22.

ELSE -- all other two-byte instructions IF byte1 (4) = indirect THEN
Use byte1 and byte2 to get address; Figure 10.23.

END IF; -- ends indirect IF byte1 (7 DOWNTO 5) = jmp THEN
Execute jmp instruction; Figure 10.24;

ELSIF byte1 (7 DOWNTO 5) = sta THEN
Execute sta instruction, write ac; Figure 10.25.

ELSE -- read operand for lda, and, add, sub
Read memory onto databus; Figure 10.26, top. Execute lda, and, add, and sub; Figure 10.26, middle. Remove memory from databus; Figure 10.26, bottom.
END IF; -- jmp / sta / lda, and, add, sub END IF; -- jsr / bra / other double-byte instructions END IF; -- single-byte / double-byte END IF; -- interrupt / otherwise END PROCESS; END behavioral;
Outline of the Behavioral Description of Parwan
CHAPTER 10
20
VARIABLE pc : twelve; VARIABLE ac, byte1, byte2 : byte; VARIABLE v, c, z, n : qit; VARIABLE temp : qit_vector (9 DOWNTO 0);
Variable declarations of Parwan behavioral model
pc := zero_12; WAIT FOR cycle_time;
Interrupt handling of Parwan behavioral model
adbus <= pc; read_mem <= '1'; WAIT FOR read_high_time; byte1 := byte (databus); read_mem <= '0'; WAIT FOR read_low_time; pc := inc (pc);
Reading the first byte from the memory, part of Parwan behavioral model
Filling the outline of the behavioral description of Parwan Declarations, Interrupt handling, Reading the first byte
CHAPTER 10
21
CASE byte1 (3 DOWNTO 0) IS WHEN cla => ac := zero_8; WHEN cma => ac := NOT ac; IF ac = zero_8 THEN z := '1'; END IF; n := ac (7); WHEN cmc => c := NOT c; WHEN asl => c := ac (7); ac := ac (6 DOWNTO 0) & '0'; IF ac = zero_8 THEN z := 1; END IF; n := ac (7); IF c /= n THEN v := '1'; END IF; WHEN asr => ac := ac (7) & ac (7 DOWNTO 1); IF ac = zero_8 THEN z := '1'; END IF; n := ac (7); WHEN OTHERS => NULL; END CASE;
Executing single-byte instructions in the behavioral model of Parwan Using the least significant nibble for decoding instructions Decoding instructions, cla, cma, cmc, asl, asr
CHAPTER 10
22
adbus <= pc; read_mem <= '1'; WAIT FOR read_high_time; byte2 := byte (databus); read_mem <= '0'; WAIT FOR read_low_time; pc := inc (pc);
Reading the second byte from the memory, part of Parwan behavioral model
databus <= wired_byte (pc (7 DOWNTO 0) ); adbus (7 DOWNTO 0) <= byte2; write_mem <= '1'; WAIT FOR write_high_time; write_mem <= '0'; WAIT FOR write_low_time; databus <= "ZZZZZZZZ"; pc (7 DOWNTO 0) := inc (byte2);
Execution of the jsr instruction in the behavioral model of Parwan
Filling the outline of the behavioral description of Parwan Reading the second byte, Executing jsr
CHAPTER 10
23
IF ( byte1 (3) = '1' AND v = '1' ) OR ( byte1 (2) = '1' AND c = '1' ) OR ( byte1 (1) = '1' AND z = '1' ) OR ( byte1 (0) = '1' AND n = '1' ) THEN pc (7 DOWNTO 0) := byte2; END IF;
Execution of branch instructions in the behavioral model of Parwan
adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0); adbus (7 DOWNTO 0) <= byte2; read_mem <= '1'; WAIT FOR read_high_time; byte2 := byte (databus); read_mem <= '0'; WAIT FOR read_low_time;
Handling indirect addressing by the behavioral model of Parwan
Filling the outline of the behavioral description of Parwan Branch instruction, Handling indirect addressing
CHAPTER 10
24
pc := byte1 (3 DOWNTO 0) & byte2;
Execution of jmp instruction in the behavioral model of Parwan
adbus <= byte1 (3 DOWNTO 0) & byte2; databus <= wired_byte (ac); write_mem <= '1'; WAIT FOR write_high_time; write_mem <= '0'; WAIT FOR write_low_time; databus <= "ZZZZZZZZ";
Execution of sta instruction in the behavioral model of Parwan
Filling the outline of the behavioral description of Parwan Handling jmp and sta instructions
CHAPTER 10
25
adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0); adbus (7 DOWNTO 0) <= byte2; read_mem <= '1'; WAIT FOR read_high_time; CASE byte1 (7 DOWNTO 5) IS WHEN lda => ac := byte (databus); WHEN ann => ac := ac AND byte (databus); WHEN add => temp := add_cv (ac, byte (databus), c); ac := temp (7 DOWNTO 0); c := temp (8); v := temp (9); WHEN sbb => temp := sub_cv (ac, byte (databus), c); ac := temp (7 DOWNTO 0); c := temp (8); v := temp (9); WHEN OTHERS => NULL; END CASE; IF ac = zero_8 THEN z := '1'; END IF; n := ac (7); read_mem <= '0'; WAIT FOR read_low_time;
Execution of lda, and, add, and sub instructions in the behavioral model of Parwan
CHAPTER 10
26
PARWAN BUSSING STRUCTURE
databus_on_dbus DATABUS dbus_on_databus DBUS

8
4096 byte memory ...
ADBUS
obus_on_dbus
8 4 8
AC ac_out a_side ALU b_side
IR ir_out PC_PAGE pc_out PC_OFFSET
CONTROLLER
alu_flags 4
mar_page_bus mar_inp MAR_PAGE OBUS

4
mar_offset_bus
alu_out SHU
4 8
MAR_OFFSET
8
mar_out
SR
read_mem write_mem interrupt
ADBUS
12
Bussing structure of Parwan
CHAPTER 10
27
Component AC IR PC MAR SR ALU SHU
Type Register Register Loadable Up Counter Register Register Arithmetic Unit Shifter Logic
Bits 8 8 12 12 4 8 8
Machine has 7 components Behavioral description helps partitioning the circuit Circuit components will be identified Bussing specifies interconnection of these components
CHAPTER 10
28

LDA Instruction: Cycle 1 Begin Fetch
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Pc_on_mar_page_bus, Pc_om_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ir Pc_on_mar_page_bus Get Address Pc_on_mar_offset_bus Load_mar_page Load_mar_offset Increment_pc Mar_on_adbus Read_memory Databus_on_dbus Dbus_on_mat_offset_bus Page_from_in_on_mar_page_bus Load_mar_page_bus Load_mar_offset_bus Get Operand, Load AC Mar_on_adbus Read_memory Databus_on_adbus Alu_a_side_on_alu_output No_shift Load_ac ... Next Fetch
Steps for execution of lda
CHAPTER 10
29
Data Signals DATA SECTION
Data Components and Buses
CONTROL SECTION
Control Signals
Data and control sections of Parwan CPU 31 control signals from the controller to the data unit
CHAPTER 10
30
DATAFLOW DESCRIPTION OF PARWAN
Applies To
AC IR PC
Category
Register Control Register Control Register Control
Signal Name
load_ac, zero_ac load_ir increment_pc, load_page_pc, load_offset_pc, reset_pc Loads ac Resets ac Loads ir Increments pc
Functionality
Loads page part of pc Loads offset part of pc Resets pc Loads page part of mar Loads offset part of mar Loads sr Complements carry flag of sr Puts page part of pc on mar page bus Puts 4 bits of ir on mar page bus Puts offset part of pc on mar offset bus Puts dbus on mar offset bus Puts offset part of pc on dbus Puts obus on dbus Puts external databus on internal dbus Puts all of mar on adbus Puts internal dbus on external databus Shifter shifts its input one place to the left Shifter shifts its input one place to the right Output of alu becomes and of its two inputs Output of alu becomes complement of its b input Output of alu becomes the same as its a input alu perfporms add operation on its two inputs Output of alu becomes the same as its b input alu perfporms subtraction of its two inputs Starts a memory read operation Starts a memory write operation Interrupts CPU
MAR SR MAR_BUS
Register Control Register Control Bus Control
load_page_mar, load_offset_mar load_sr, cm_carry_sr pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, dbus_on_mar_offset_bus
DBUS
Bus Control
pc_offset_on_dbus, obus_on_dbus, databus_on_dbus
ADBUS DATABUS SHU ALU
Bus Control Bus Control Logic Units Logic Units
mar_on_adbus dbus_on_databus arith_shift_left, arith_shift_right alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub
Others
I/O
read_mem, write_mem, interrupt
Inputs and outputs of Parwan control section Signals for flow of data and data clocking
CHAPTER 10
31
System Clock Control Signal 1 Control Signal 2
Control signals remain asserted for a complete clock cycle Allows logic unit propagation Clock data and control at the same time Clock data while control signals are still valid
Timing of control signals Assume falling edge trigger data and control
CHAPTER 10
32
Id 0 1 2 3 4 5
Opcode line alu_and alu_not alu_a alu_add alu_b alu_sub
Operation a AND b NOT b a b PLUS a b b MINUS a
Flags zn zn zn vczn zn vczn
Individual data components will be described in VHDL. Will also show hardware.
Operations and flags of alu A control signal for each operation
CHAPTER 10
33
ai
bi
alu_and
alu_not
0 1 2 3 4 5 VI CI ZI NI A B A B A B A B A B A B A B A B
ALU (3, 5) VO (3, 5) CO (0, 1, 2, 3, 4, 5) ZO (0, 1, 2, 3, 4, 5) NO

alu_a
alu_add
[0] [1] [2] [3] [4] [5] [6] [7]

alu_sub
+
alu_b
Parwan alu Logic symbol One bit gate level hardware
CHAPTER 10
34
LIBRARY cmos; USE cmos.basic_utilities.ALL; -PACKAGE alu_operations IS CONSTANT a_and_b : qit_vector (5 DOWNTO 0) := "000001"; CONSTANT b_compl : qit_vector (5 DOWNTO 0) := "000010"; CONSTANT a_input : qit_vector (5 DOWNTO 0) := "000100"; CONSTANT a_add_b : qit_vector (5 DOWNTO 0) := "001000"; CONSTANT b_input : qit_vector (5 DOWNTO 0) := "010000"; CONSTANT a_sub_b : qit_vector (5 DOWNTO 0) := "100000"; END alu_operations;
Package declaration for the alu_operations package Simplify code and add readability
CHAPTER 10
35

ENTITY arithmetic_logic_unit IS PORT (a_side, b_side : IN byte; alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit; in_flags : IN nibble; z_out : OUT byte; out_flags : OUT nibble); END arithmetic_logic_unit; -ARCHITECTURE behavioral OF arithmetic_logic_unit IS BEGIN coding: PROCESS (a_side, b_side, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub) VARIABLE t : qit_vector (9 DOWNTO 0); VARIABLE v, c, z, n : qit; ALIAS n_flag_in : qit IS in_flags(0); ALIAS z_flag_in : qit IS in_flags(1); ALIAS c_flag_in : qit IS in_flags(2); ALIAS v_flag_in : qit IS in_flags(3); BEGIN WHEN a_add_b => t := add_cv (b_side, a_side, c_flag_in); c := t(8); v := t(9); -- other flags are set at the end WHEN a_sub_b => t := sub_cv (b_side, a_side, c_flag_in); c := t(8); v := t(9); WHEN a_and_b => t (7 DOWNTO 0) := a_side AND b_side; c := c_flag_in; v := v_flag_in; WHEN a_input => t (7 DOWNTO 0) := a_side; c := c_flag_in; v := v_flag_in; WHEN b_input => t (7 DOWNTO 0) := b_side; c := c_flag_in; v := v_flag_in; WHEN b_compl => t (7 DOWNTO 0) := NOT b_side; c := c_flag_in; v := v_flag_in; WHEN OTHERS => NULL; END CASE; n := t(7); z := set_if_zero (t (7 DOWNTO 0)); z_out <= t (7 DOWNTO 0); out_flags <= (v, c, z, n); END PROCESS coding; END behavioral;
CASE qit_vector (5 DOWNTO 0) (alu_sub, alu_b, alu_add, alu_a, alu_not, alu_and) IS
Behavioral description of arithmetic logic unit of Parwan
CHAPTER 10
36
Input
Output
SHU L R VI CI ZI NI [0] [1] [2] [3] [4] [5] [6] [7]

i+1 i i
( L) VO (L) CO (L, R) ZO (L, R) NO
i-1
Parwan shu Logic symbol One bit hardware
CHAPTER 10
37

ENTITY shifter_unit IS PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN qit; in_flags : IN nibble; obus_side : OUT byte; out_flags : OUT nibble); END shifter_unit; -ARCHITECTURE behavioral OF shifter_unit IS BEGIN coding: PROCESS (alu_side, arith_shift_left, arith_shift_right) VARIABLE t : qit_vector (7 DOWNTO 0); VARIABLE v, c, z, n : qit; ALIAS n_flag_in : qit IS in_flags(0); ALIAS z_flag_in : qit IS in_flags(1); ALIAS c_flag_in : qit IS in_flags(2); ALIAS v_flag_in : qit IS in_flags(3); BEGIN IF arith_shift_right = '0' AND arith_shift_left = '0' THEN t := alu_side (7 DOWNTO 0); (v, c, z, n) := in_flags; ELSIF arith_shift_left = '1' THEN t := alu_side (6 DOWNTO 0) & '0'; n := t (7); z := set_if_zero (t); c := alu_side (7); v := alu_side (6) XOR alu_side (7); ELSIF arith_shift_right = '1' THEN t := alu_side (7) & alu_side (7 DOWNTO 1); n := t (7); z := set_if_zero (t); c := c_flag_in; v := v_flag_in; END IF; obus_side <= t; out_flags <= (v, c, z, n); END PROCESS coding; END behavioral;
Behavioral Description of the Shifter Unit of Parwan
CHAPTER 10
38
load cm_carry
G1 G2 C3
SR
N Z C V
1, 3D 1, 3D 1, 3D 2, 3D 1, 3D
[0] [1] [2] [3]
N Z C V
input c
2D
output c
load G1 cm_carry
1C2
The status register Logic symbol One bit hardware
CHAPTER 10
39
ENTITY status_register_unit IS PORT (in_flags : IN nibble; out_status : OUT nibble; load, cm_carry, ck : IN qit ); END status_register_unit; -ARCHITECTURE behavioral OF status_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : nibble := "0000"; ALIAS internal_c : qit IS internal_state (2); BEGIN IF (ck = '0') THEN IF (load = '1') THEN internal_state := in_flags; ELSIF (cm_carry = '1') THEN internal_c := NOT internal_c; END IF; out_status <= internal_state; END IF; END PROCESS; END behavioral;
Behavioral description of the status register of Parwan
CHAPTER 10
40
load zero
G1 M2 M3 1C4
AC
zero
'0' I0 '0' I1 '0' I2 '0' I3 '0' I4 '0' I5 '0' I6 '0' I7
2, 4D 3, 4D 2, 4D 3, 4D 2, 4D 3, 4D 2, 4D 3, 4D 2, 4D 3, 4D 2, 4D 3, 4D 2, 4D 3, 4D 2, 4D 3, 4D
[0] [1] [2] [3] [4] [5] [6] [7]
o0 o1
2D
Oi
I
o2 o3 o4 o5 o6 o7
G1
1C2
Parwan accumulator Logic symbol One bit hardware
CHAPTER 10
41
ENTITY accumulator_unit IS PORT (i8 : IN byte; o8 : OUT byte; load, zero, ck : IN qit); END accumulator_unit; -ARCHITECTURE dataflow OF accumulator_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED "00000000" WHEN zero = '1' ELSE i8; END BLOCK clocking; END BLOCK enable; END dataflow;
Dataflow description of Parwan accumulator
CHAPTER 10
42
IR LOAD CI 1C2
I
I0 I1 I2 I3 I4 I5 I6 I7 2D 2D 2D 2D 2D 2D 2D 2D [0] [1] [2] [3] [4] [5] [6] [7] o0 o1 o2 o3 o4
2D
Oi
load
o5 o6 o7
G1
1C2
The Parwan instruction register Logic symbol One bit hardware
CHAPTER 10
43
ENTITY instruction_register_unit IS PORT (i8 : IN byte; o8 : OUT byte; load, ck : IN qit); END instruction_register_unit; -ARCHITECTURE dataflow OF instruction_register_unit IS BEGIN enable : BLOCK (load = '1') BEGIN clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD ) BEGIN o8 <= GUARDED i8; END BLOCK clocking; END BLOCK enable; END dataflow;
Dataflow description of the instruction register of Parwan
CHAPTER 10
44
reset load_page load_offset increment
3R G1 G2 G4 C3/4+
PC
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11
2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 1, 3D 1, 3D 1, 3D 1, 3D
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
o0 o1 o2 o3
O i-1
reset
o4 o5 o6 o7 o8 o9 o10 o11
2R
Oi
G1
1T
C2
load_pc_offset clock
Parwan program counter Logic symbol One bit hardware
CHAPTER 10
45
ENTITY program_counter_unit IS PORT (i12 : IN twelve; o12 : OUT twelve; increment, load_page, load_offset, reset, ck : IN qit); END program_counter_unit; -ARCHITECTURE behavioral OF program_counter_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12; BEGIN IF (ck = '0' ) THEN IF reset = '1' THEN internal_state := zero_12; ELSIF increment = '1' THEN internal_state := inc (internal_state); ELSE IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8); END IF; IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0); END IF; END IF; o12 <= internal_state; END IF; END PROCESS; END behavioral;
Behavioral description of the program counter of Parwan
CHAPTER 10
46
MAR load_page load_offset G1 G2 C3
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11
2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 2, 3D 1, 3D 1, 3D 1, 3D 1, 3D
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11
2D
Oi
load
G1
1C2
Logic symbol for the memory address register of Parwan
CHAPTER 10
47
ENTITY memory_address_register_unit IS PORT (i12 : IN twelve; o12 : OUT twelve; load_page, load_offset, ck : IN qit); END memory_address_register_unit; -ARCHITECTURE behavioral OF memory_address_register_unit IS BEGIN PROCESS (ck) VARIABLE internal_state : twelve := zero_12; BEGIN IF (ck = '0' ) THEN IF load_page = '1' THEN internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8); END IF; IF load_offset = '1' THEN internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0); END IF; o12 <= internal_state; END IF; END PROCESS; END behavioral;
Behavioral description of the memory address register of Parwan
CHAPTER 10
48
ENTITY par_data_path IS
PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve;
clk : IN qit; -- register controls: load_ac, zero_ac, load_ir, increment_pc, load_page_pc, load_offset_pc, reset_pc, load_page_mar, load_offset_mar, load_sr, cm_carry_sr, -- bus connections: pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, dbus_on_mar_offset_bus, pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, mar_on_adbus, dbus_on_databus, -- logic unit function control inputs: arith_shift_left, arith_shift_right, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit; -- outputs to the controller: ir_lines : OUT byte; status : OUT nibble ); END par_data_path;
Entity Declaration of the Data Section of Parwan Wires all components Specifies bussing
CHAPTER 10
49
ARCHITECTURE structural OF par_data_path IS -COMPONENT ac PORT (i8: IN byte; o8: OUT byte; load, zero, ck: IN qit); END COMPONENT; FOR r1: ac USE ENTITY WORK.accumulator_unit (dataflow); -COMPONENT ir PORT (i8: IN byte; o8: OUT byte; load, ck: IN qit); END COMPONENT; FOR r2: ir USE ENTITY WORK.instruction_register_unit (dataflow); -COMPONENT pc PORT (i12 : IN twelve; o12 : OUT twelve; increment, load_page, load_offset, reset, ck : IN qit); END COMPONENT; FOR r3: pc USE ENTITY WORK.program_counter_unit (behavioral); -COMPONENT mar PORT (i12 : IN twelve; o12 : OUT twelve; load_page, load_offset, ck : IN qit); END COMPONENT; FOR r4: mar USE ENTITY WORK.memory_address_register_unit (behavioral); -COMPONENT sr PORT (in_flags : IN nibble; out_status : OUT nibble; load, cm_carry, ck : IN qit ); END COMPONENT; FOR r5 : sr USE ENTITY WORK.status_register_unit (behavioral); -COMPONENT alu in_flags : IN nibble; z_out : OUT byte; out_flags : OUT nibble); END COMPONENT; FOR l1 : alu USE ENTITY WORK.arithmetic_logic_unit (behavioral); -COMPONENT shu PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN qit; in_flags : IN nibble; obus_side : OUT byte; out_flags : OUT nibble); END COMPONENT; FOR l2 : shu USE ENTITY WORK.shifter_unit (behavioral); -SIGNAL ac_out, ir_out, alu_out, obus : byte; SIGNAL alu_a_inp : byte; SIGNAL pc_out, mar_out : twelve; SIGNAL dbus : wired_byte BUS; SIGNAL alu_flags, shu_flags, sr_out : nibble; SIGNAL mar_bus : wired_twelve BUS; SIGNAL mar_inp : twelve;
PORT (a_side, b_side : IN byte; alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit;
Declarative Part of the structural Architecture of par_data_path Components are declared Busses and signals are declared
BEGIN -- bus connections --dbus1: alu_a_inp <= qit_vector (dbus); dbus2: BLOCK (dbus_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED dbus; END BLOCK dbus2; dbus3: BLOCK (dbus_on_databus = '1') BEGIN databus <= GUARDED dbus; END BLOCK dbus3; -obus1: BLOCK (obus_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (obus); END BLOCK obus1; -databus1: BLOCK (databus_on_dbus = '1') BEGIN dbus <= GUARDED databus; END BLOCK databus1; -mar_bus1: mar_inp <= qit_vector (mar_bus); --- register connections --r1: ac PORT MAP (obus, ac_out, load_ac, zero_ac, clk); -r2: ir PORT MAP (obus, ir_out, load_ir, clk); ir1: ir_lines <= ir_out; ir2: BLOCK (ir_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0)); END BLOCK ir2;
Statement part of the par_data_path structural Architecture Uses block statements for bussing Register interconnections follow registers instantiation
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51
r3: pc PORT MAP (mar_out, pc_out, increment_pc, load_page_pc, load_offset_pc, reset_pc, clk); pc1: BLOCK (pc_on_mar_page_bus = '1') BEGIN mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8)); END BLOCK pc1; pc2: BLOCK (pc_on_mar_offset_bus = '1') BEGIN mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)); END BLOCK pc2; pc3: BLOCK (pc_offset_on_dbus = '1') BEGIN dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0)); END BLOCK pc3; -r4: mar PORT MAP (mar_inp, mar_out, load_page_mar, load_offset_mar, clk); mar1: BLOCK (mar_on_adbus = '1') BEGIN adbus <= GUARDED mar_out; END BLOCK mar1; -r5: sr PORT MAP (shu_flags, sr_out, load_sr, cm_carry_sr, clk); sr1: status <= sr_out; --- connection of logical and register structures --l1: alu PORT MAP (alu_a_inp, ac_out, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub, sr_out, alu_out, alu_flags); l2: shu PORT MAP (alu_out, arith_shift_left, arith_shift_right, alu_flags, obus, shu_flags); END structural;
Statement part of the par_data_path structural Architecture Ends with logic unit instantiations
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52
To other control FF inputs External Signals
logic block
control FF i Q All Signals Activating State i 1D i C1 signals issuing control signals control signals to data section en
system clock
For the Parwan controller, style, hardware and coding will be described.
Typical hardware surrounding a control flip-flop The logic block is designated by a bubble Controller is built using one-hot encoding
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53
csx
a b c logic block i d e logic block j csy
Q 1D i C1
en 1D j C1
en 1D k C1
clock
Example for the structure of Parwan control section Showing 3 states in a one-hot implementation
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54
ENTITY par_control_unit IS GENERIC (read_delay, write_delay : TIME := 3 NS); PORT (clk : IN qit; -- register control signals: load_ac, zero_ac, load_ir, increment_pc, load_page_pc, load_offset_pc, reset_pc, load_page_mar, load_offset_mar, load_sr, cm_carry_sr, -- bus connection control signals: pc_on_mar_page_bus, ir_on_mar_page_bus, pc_on_mar_offset_bus, dbus_on_mar_offset_bus, pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, mar_on_adbus, dbus_on_databus, -- logic unit function control outputs: arith_shift_left, arith_shift_right, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : OUT ored_qit BUS; -- inputs from the data section: ir_lines : IN byte; status : IN nibble; -- memory control and other external signals: read_mem, write_mem : OUT ored_qit BUS; interrupt : IN qit ); END par_control_unit; ------------------------------------------------------------------------------------------------ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := 000000001; BEGIN
Entity declaration of Parwan control section Showing signals for the data unit Declaring states of the machine is shown Declarative part of the par_control_unit dataflow architecture
CHAPTER 10
55
par_control_unit
control_signal_1
assignments to control_signal_1
control_signal_2
control_signal_3
oring_qit type signals
Assigning signals with implied oring, par_control_unit outputs
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56
s1: BLOCK (s(1) = '1') BEGIN -- start of fetch -- pc to mar pc_on_mar_page_bus <= GUARDED '1'; pc_on_mar_offset_bus <= GUARDED '1'; load_page_mar <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- reset pc if interrupt reset_pc <= GUARDED '1' WHEN interrupt = '1' ELSE '0'; -- goto 2 if interrupt is off ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1' WHEN interrupt = '1' ELSE '0'; s(2) <= GUARDED '1' WHEN interrupt /= '1' ELSE '0'; END BLOCK ck; END BLOCK s1;
pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar
reset_pc
1D
1 interrupt
C1
State 1: starting a fetch VHDL code Gate level hardware
CHAPTER 10
57
s2: BLOCK (s(2) = '1') BEGIN -- fetching continues -- read memory into ir mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; alu_a <= GUARDED 1; load_ir <= GUARDED '1'; -- increment pc increment_pc <= GUARDED '1'; -- goto 3 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(3) <= GUARDED '1'; END BLOCK ck; END BLOCK s2;
mar_on_adbus read_mem databus_on_dbus alu_a load_ir increment_pc
1D
C1
State 2: completing a fetch VHDL code Gate level hardware
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58

s3: BLOCK (s(3) = '1') BEGIN -- pc to mar, for next read pc_on_mar_page_bus <= GUARDED '1'; pc_on_mar_offset_bus <= GUARDED '1'; load_page_mar <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- goto 4 if not single byte instruction ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(4) <= GUARDED '1' WHEN ir_lines (7 DOWNTO 4) /= "1110" ELSE '0'; END BLOCK ck; -- perform single byte instructions sb: BLOCK ( (ir_lines (7 DOWNTO 4) = "1110") AND GUARD) BEGIN (alu_not, alu_b) <= GUARDED qit_vector(10) WHEN ir_lines (1) = 1 ELSE qit_vector( 01); arith_shift_left <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1000" ELSE '0'; arith_shift_right <= GUARDED '1' WHEN ir_lines (3 DOWNTO 0) = "1001" ELSE '0'; load_sr <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'; cm_carry_sr <= GUARDED '1' WHEN ir_lines (2) = '1' ELSE '0'; load_ac <= GUARDED '1' WHEN ( ir_lines (3) = '1' OR ir_lines (1) = '1' ) ELSE '0'; zero_ac <= GUARDED '1' WHEN ( ir_lines (3) = '0' AND ir_lines (0) = '1' ) ELSE '0'; ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'; END BLOCK ck; END BLOCK sb; END BLOCK s3;
State 3: preparing for address fetch Execution of single byte instructions VHDL code
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59

pc_on_mar_page_bus pc_on_mar_offset_bus load_page_mar load_offset_mar
1D
3 IR7 IR6 IR5 IR4
C1
IR3 2 1 0 IR3 2 1 0 IR1
arith_shift_left
arith_shift_right
alu_not
alu_b IR1 IR3 IR1 cm_carry_sr IR2 IR3 1 IR3 0 zero_ac load_ac load_sr
State 3: preparing for address fetch Execution of single byte instructions Gate level hardware
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60
s4: BLOCK (s(4) = '1') BEGIN -- page from ir, and offset from next memory makeup 12-bit address -- read memory into mar offset mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; dbus_on_mar_offset_bus <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- completed operand (dir/indir) address -- page from ir if not branch or jsr pg: BLOCK ( (ir_lines (7 DOWNTO 6) /= "11") AND GUARD) BEGIN ir_on_mar_page_bus <= GUARDED '1'; load_page_mar <= GUARDED '1'; -- goto 5 for indirect, 6 for direct ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(5) <= GUARDED '1' WHEN ir_lines (4) = '1' ELSE '0'; -- indir s(6) <= GUARDED '1' WHEN ir_lines (4) = '0' ELSE '0'; -- direct END BLOCK ck; END BLOCK pg; -- keep page in mar_page if jms or bra (same-page instructions) sp: BLOCK ( (ir_lines (7 DOWNTO 6) = "11") AND GUARD) BEGIN -- goto 7 for jsr, 9 for bra ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(7) <= GUARDED '1' WHEN ir_lines (5) = '0' ELSE '0'; -- jsr s(9) <= GUARDED '1' WHEN ir_lines (5) = '1' ELSE '0'; -- bra END BLOCK ck; END BLOCK sp; -- increment pc increment_pc <= GUARDED '1'; END BLOCK s4;
State 4: completing address of full address instructions Branching for indirect, direct, jsr, and branch VHDL code Gate level hardware
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61
mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offet_bus load_offset_mar increment_pc ir_on_mar_page_bus load_page_mar IR7 1D 4 6 5
C1
IR4
IR5
State 4: completing address of full address instructions Branching for indirect, direct, jsr, and branch Gate level hardware
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62
s5: BLOCK (s(5) = '1') BEGIN -- indirect addressing -- read actual operand from memory into mar offset mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; dbus_on_mar_offset_bus <= GUARDED '1'; load_offset_mar <= GUARDED '1'; -- goto 6 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(6) <= GUARDED '1'; END BLOCK ck; END BLOCK s5;
mar_on_adbus read_mem databus_on_dbus dbus_on_mar_offset_bus load_offset_mar
1D
c1
State 5: taking care of indirect addressing Actual address will now go in MAR
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63

s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN ... END BLOCK jm; st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN ... END BLOCK st; rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN ... END BLOCK rd; -- perform lda, and, add, sub END BLOCK s6;
jm ir7 6 5
2 load_page_pc load_offset_pc
1D
C1
st ir7 6 5
1 mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem
rd ir7
1
mar_on_adbus read_mem databus_on_dbus load_sr load_ac
ir6 ir5 alu_a
alu_and
alu_add
alu_sub
State 6: reading the actual operand, Reading and executing jmp, sta, lda, and, add, and sub instructions Outline of the VHDL code Outline of the hardware Three separate blocks for [jmp], [sta], and [lda, and, add, sub]
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64
s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD BEGIN load_page_pc <= GUARDED '1'; load_offset_pc <= GUARDED '1'; -- goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'; END BLOCK ck; END BLOCK jm; ... END BLOCK s6;
State 6: reading the actual operand, Reading and executing jmp instruction VHDL code Two more blocks for [sta], and [lda, and, add, sub]
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65
s6: BLOCK (s(6) = '1') BEGIN ... st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -- mar on adbus, ac on databus, write to memory mar_on_adbus <= GUARDED '1'; alu_b <= GUARDED 1; obus_on_dbus <= GUARDED '1'; dbus_on_databus <= GUARDED '1'; write_mem <= GUARDED '1' AFTER write_delay; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK st; ... END BLOCK s6;
State 6: reading the actual operand, Reading and executing sta instruction Partial VHDL code Need one more block for handling [lda, and, add, sub]
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66
s6: BLOCK (s(6) = '1') BEGIN ... rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -- mar on adbus, read memory for operand, perform operation mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; alu_a <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 00 ELSE 0; alu_and <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 01 ELSE 0; alu_add <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 10 ELSE 0; alu_sub <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 11 ELSE 0; load_sr <= GUARDED '1'; load_ac <= GUARDED '1'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK rd; -- perform lda, and, add, sub END BLOCK s6;
State 6: reading the actual operand, Reading and executing jmp, sta, lda, and, add, and sub instructions Completing the VHDL code This last block handles [lda, and, add, sub]
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67

s6: BLOCK (s(6) = '1') BEGIN jm : BLOCK ( (ir_lines (7 DOWNTO 5) = "100" ) AND GUARD) BEGIN load_page_pc <= GUARDED '1'; load_offset_pc <= GUARDED '1'; -- goto 2 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(2) <= GUARDED '1'; END BLOCK ck; END BLOCK jm; st: BLOCK ( (ir_lines (7 DOWNTO 5) = "101") AND GUARD) BEGIN -- mar on adbus, ac on databus, write to memory mar_on_adbus <= GUARDED '1'; alu_b <= GUARDED 1; obus_on_dbus <= GUARDED '1'; dbus_on_databus <= GUARDED '1'; write_mem <= GUARDED '1' AFTER write_delay; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK st; rd: BLOCK ( (ir_lines (7) = '0') AND GUARD) BEGIN -- mar on adbus, read memory for operand, perform operation mar_on_adbus <= GUARDED '1'; read_mem <= GUARDED '1' AFTER read_delay; databus_on_dbus <= GUARDED '1'; alu_a <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 00 ELSE 0; alu_and <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 01 ELSE 0; alu_add <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 10 ELSE 0; alu_sub <= GUARDED 1 WHEN ir_lines (6 DOWNTO 5) = 11 ELSE 0; load_sr <= GUARDED '1'; load_ac <= GUARDED '1'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK rd; -- perform lda, and, add, sub END BLOCK s6;
State 6: reading the actual operand, and executing jmp, sta, lda, and, add, and sub instructions Complete VHDL code
CHAPTER 10
68

jm ir7 6 5
2 load_page_pc load_offset_pc
1D
C1
st ir7 6 5
1
mar_on_adbus alu_b obus_on_dbus dbus_on_databus write_mem
rd ir7
1
mar_on_adbus read_mem databus_on_dbus load_sr load_ac
ir6 ir5 alu_a
alu_and
alu_add
alu_sub
State 6: reading the actual operand, and executing jmp, sta, lda, and, add, and sub instructions Complete gate level hardware
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69
s7: BLOCK (s(7) = '1') BEGIN -- jsr -- write pc offset to top of subroutine mar_on_adbus <= GUARDED '1'; pc_offset_on_dbus <= GUARDED '1'; dbus_on_databus <= GUARDED '1'; write_mem <= GUARDED '1' AFTER write_delay; -- address of subroutine to pc load_offset_pc <= GUARDED '1'; -- goto 8 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(8) <= GUARDED '1'; END BLOCK ck; END BLOCK s7;
mar_on_adbus pc_offset_on_dbus dbus_on_databus write_mem load_offset_pc
1D
c1
State 7: writing return address of subroutine Making pc point to top of subroutine Complete VHDL code Hardware
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70
s8: BLOCK (s(8) = '1') BEGIN -- increment pc increment_pc <= GUARDED '1'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK s8;
increment_pc
1D
c1
State 8: incrementing pc to skip location reserved for return address VHDL code Hardware
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71
s9: BLOCK (s(9) = '1') BEGIN load_offset_pc <= GUARDED '1' WHEN (status AND ir_lines (3 DOWNTO 0)) /= "0000" ELSE '0'; -- goto 1 ck: BLOCK ( (clk = '0' AND NOT clk'STABLE) AND GUARD ) BEGIN s(1) <= GUARDED '1'; END BLOCK ck; END BLOCK s9;
ir3 status3 ir2 status2 load_offset_pc ir1 status1
ir0 status0
1
1D
C1
State 9: conditional loading of pc for branch instructions VHDL code Gate level hardware
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72
ARCHITECTURE dataflow OF par_control_unit IS SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := 000000001; BEGIN

S1: BLOCK (s(1) = '1') BEGIN ... BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s1; S2: BLOCK (s(2) = '1') BEGIN ... BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s2;
OOOO
S8: BLOCK (s(8) = '1') BEGIN ... BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s8; S9: BLOCK (s(9) = '1') BEGIN ... BEGIN s(next) <= GUARDED '1'; END BLOCK ck; END BLOCK s9;
ck: BLOCK ( clk = '0' AND NOT clk'STABLE ) BEGIN s (9 DOWNTO 1) <= GUARDED "000000000"; END BLOCK ck; -- State blocks end here END dataflow;
Ending the dataflow description of the par_control_unit Controller outline Need to clock all states A zero driver is placed on all state,.
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73
Q 1D 1 C1
en 1D 2 C1
Q 3 C1
en
Q 1D 4 C1
en 1D 5 C1
Q 1D 6 C1
en
Q 1D 7 C1 1D 8 C1
Q 1D 9 C1
Complete control unit Wire individual control flip-flops Oring is done at inputs of states when branching is done to them
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74
ENTITY par_central_processing_unit IS PORT (clk : IN qit; interrupt : IN qit; read_mem, write_mem : OUT qit; databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve ); END par_central_processing_unit;
Entity declaration of the Parwan CPU for its dataflow description Complete CPU wires data and control
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75

ARCHITECTURE dataflow OF par_central_processing_unit IS COMPONENT par_data_path PORT (databus : INOUT wired_byte; adbus : OUT twelve; clk : IN qit; load_ac, zero_ac, . . . ir_lines : OUT byte; status : OUT nibble ); END COMPONENT; FOR data: par_data_path USE ENTITY WORK.par_data_path (structural); -COMPONENT par_control_unit PORT (clk : IN qit; load_ac, zero_ac, . . . ir_lines : IN byte; status : IN nibble; read_mem, write_mem : OUT qit; interrupt : IN qit ); END COMPONENT; FOR ctrl: par_control_unit USE ENTITY WORK.par_control_unit (dataflow); -SIGNAL load_ac, zero_ac, . . . SIGNAL ir_lines : byte; SIGNAL status : nibble; BEGIN data: par_data_path PORT MAP (databus, adbus, clk, load_ac, zero_ac, . . . ir_lines, status ); ctrl: par_control_unit PORT MAP (clk, load_ac, zero_ac, . . . ir_lines, status, read_mem, write_mem, interrupt ); END dataflow;
The general outline of dataflow architectture of Parwan CPU. Data and control declarations Data and control wiring
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76
A TEST BENCH FOR THE PARWAN CPU

ARCHITECTURE input_output OF parwan_tester IS COMPONENT parwan PORT (clk : IN qit; interrupt : IN qit; read_mem, write_mem : OUT qit; databus : INOUT wired_byte BUS; adbus : OUT twelve ); END COMPONENT; SIGNAL clock, interrupt, read, write : qit; SIGNAL data : wired_byte := "ZZZZZZZZ"; SIGNAL address : twelve; TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte; BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock; cpu : parwan PORT MAP (clock, interrupt, read, write, data, address); mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000", "00011000", "10100000", "00011001", --lda 24, sta 25 "00100000", "00011010", "01000000", "00011011", --and 26, add 27 "11100010", "11101001", "01100000", "00011100", --cac, asr, sub 28 "00010000", "00011101", "11000000", "00100100", --lda i 29, jsr 36 "11101000", "11100000", "10000000", "00100000", --asl, nop, jmp 32 "00000000", "00000000", "00000000", "00000000", "01011100", "00000000", "01110000", "00010010", --(24, 25, 26, 27) "00001100", "00011111", "00000000", "01011010", --(28, 29, 30, 31) "10000000", "00010010", "00000000", "00000000", --jmp 18 "00000000", "11100010", "10010000", "00100100", -- , cma, jmp i 36 OTHERS => (OTHERS => 0)); VARIABLE ia : INTEGER; BEGIN WAIT ON read, write; qit2int (address, ia); IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ"; ELSE data <= wired_byte ( memory (ia) ); END IF; WAIT UNTIL read = '0'; data <= "ZZZZZZZZ"; ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ); END IF; WAIT UNTIL write = '0'; END IF; END PROCESS mem; END input_output;
A simple test bench for Parwan behavioral and dataflow descriptions. A simple testbench Include CPU instantiation, a short memory, and read/write handshaking
ARCHITECTURE input_output OF parwan_tester IS ... SIGNAL clock, interrupt, read, write : qit; SIGNAL data : wired_byte := "ZZZZZZZZ"; SIGNAL address : twelve; TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte; BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock; cpu : parwan PORT MAP (clock, interrupt, read, write, data, address); mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000", "00011000", "10100000", "00011001", --lda 24, sta 25 "00100000", "00011010", "01000000", "00011011", --and 26, add 27 "11100010", "11101001", "01100000", "00011100", --cac, asr, sub 28 "00010000", "00011101", "11000000", "00100100", --lda i 29, jsr 36 "11101000", "11100000", "10000000", "00100000", --asl, nop, jmp 32 "00000000", "00000000", "00000000", "00000000", "01011100", "00000000", "01110000", "00010010", --(24, 25, 26, 27) "00001100", "00011111", "00000000", "01011010", --(28, 29, 30, 31) "10000000", "00010010", "00000000", "00000000", --jmp 18 "00000000", "11100010", "10010000", "00100100", -- , cma, jmp i 36 OTHERS => (OTHERS => 0)); VARIABLE ia : INTEGER; BEGIN ... END input_output;
Initializing memory for Parwan instructions
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78

ARCHITECTURE input_output OF parwan_tester IS ... SIGNAL clock, interrupt, read, write : qit; SIGNAL data : wired_byte := "ZZZZZZZZ"; SIGNAL address : twelve; TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte; BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock; cpu : parwan PORT MAP (clock, interrupt, read, write, data, address); mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ... VARIABLE ia : INTEGER; BEGIN WAIT ON read, write; qit2int (address, ia); IF read = '1' THEN IF ia >= 64 THEN data <= "ZZZZZZZZ"; ELSE data <= wired_byte ( memory (ia) ); END IF; WAIT UNTIL read = '0'; data <= "ZZZZZZZZ"; ELSIF write = '1' THEN IF ia < 64 THEN memory (ia) := byte ( data ); END IF; WAIT UNTIL write = '0'; END IF; END PROCESS mem; END input_output;
Produce test waveforms on interrupt and clock signals Testing is done by modeling memory read and write operations A single process assigns values from memory to databus Same process handles memory write
CHAPTER 10
79
CONFIGURATION behavior OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY behavioral.par_central_processing_unit(behavioral); END FOR; END FOR; END behavior; (a)
CONFIGURATION dataflow OF parwan_tester IS FOR input_output FOR cpu : parwan USE ENTITY par_dataflow.par_central_processing_unit(dataflow); END FOR; END FOR; END dataflow;
(b)
Parwan tester applies data to Parwan buses Component is declared, binding will be done by configuration declaration Hold data normally at z (High Impedance)
CHAPTER 10
80
A MORE REALISTIC PARWAN
WHEN instr_fetch => ---------------------------------------2 -- read memory into ir read_mem <= '1'; IF grant = '1' THEN mar_on_adbus <= '1'; IF ready = '1' THEN databus_on_dbus <= '1'; alu_a <= 1; load_ir <= '1'; increment_pc <= '1'; next_state <= do_one_bytes; ELSE next_state <= instr_fetch; END IF; ELSE next_state <= instr_fetch; END IF; WHEN do_one_bytes => --------------------------------------3
...
Memory and bus signaling for fetch state of controller Signals provide for slower memory handshaking Buss access signals are included
CHAPTER 10
81
SUMMARY
This chapter showed how VHDL could be used to describe a system at the behavioral level before the system is even designed, and at the dataflow level after major design decisions have been made. The behavioral description aids designers as they verify their understanding of the problem, while the dataflow description can be used to verify the bussing and register structure of the design. A design carried to the stage where a dataflow model can be generated is only a few simple steps away from complete hardware realization. For completing the design of Parwan, flip-flop and gate interconnections should replace the component descriptions in the Parwan dataflow model. We consider the design presented here a manual design. We used one-to-one hardware correspondence so that no intelligent tools are required for the generation of hardware. The use of VHDL as a top-down partitioning and verification tool has helped us form such a methodology for manual design. The
methodology presented here can be applied to designs of much larger magnitude.
End of Chapter 10
CHAPTER 10
82
CHAPTER 11 INTERFACE DESIGN AND MODELING
11.1 SYSTEM OVERVIEW 11.2 CPU TIMING 11.3 MEMORY SIGNALS 11.4 SHARING SYSTEM BUSES 11.4.1 Arbitration Operation 11.4.2 Wait Operation 11.4.3 Arbiter Model 11.5 DMA DEVICE 11.5.1 Serial Connection 11.5.2 Interface Through Arbiter 11.5.3 Interface to CPU 11.5.4 DMA Controller 11.6 CPU CACHE 11.6.1 Cache Structure 11.6.2 Cache Interface 11.6.3 Cache Structure Modeling 11.6.4 Controller Modeling 11.7 COMPLETE SYSTEM 11.8 SUMMARY
CHAPTER 11
SYSTEM OVERVIEW
Arbiter Memory 4096*8
DMA Device Serial To Parallel serial_in
DMA Controller cache memory & controller Address Decoder CPU
Bussing arrangement and system components.
CHAPTER 11
SYSTEM OVERVIEW
8
dat abu s
12
ad bu s rea gra rea w dy nt d_ rite me _m m em
8-bit CPU (Parwan)
halted interrupt
CPU interface
CHAPTER 11
MEMORY SIGNALS
clock read_mem grant ready
adbus
valid
databus
valid (a)
CPU read and write requests
CHAPTER 11
MEMORY SIGNALS
clock write_mem grant ready
adbus
valid
databus
valid (b)
CPU read and write requests
CHAPTER 11
MEMORY SIGNALS
cs rwbar
Memory 4096*8
dat abu s
Memory interface
adb us
CHAPTER 11
MEMORY SIGNALS
Memory Wait cs rwbar
adbus
databus
valid
Memory read operation
CHAPTER 11
SHARING SYSTEM BUSES
memsel rwbar ready

gra wr nt ite rea _req d_ ue req st ue st
clock
Bus Arbiter and Wait Handler

skip_wait
port 1
port 2
port 3
port 4
Controlling bus access
CHAPTER 11
clock read_request i grant i memsel rwbar ready
wait for bus access
wait for device wait for wait state to complete
Bus grant for read operation
CHAPTER 11

ENTITY arbitrator IS GENERIC (wait_states : natural_vector (3 DOWNTO 0) := (OTHERS => 1); clock_period : TIME := 1 US); PORT (read_request, write_request : IN nibble; grant : BUFFER nibble; clock, skip_wait : IN qit; memsel, rwbar, ready : OUT qit); END arbitrator; -ARCHITECTURE behavioral OF arbitrator IS BEGIN -- Works with consecuitive requests wait_cycle: PROCESS BEGIN IF clock = '0' THEN WAIT FOR 20 NS; FOR i IN read_request'RANGE LOOP IF read_request(i) = '1' OR write_request(i) = '1' THEN grant <= "0000"; grant (i) <= '1'; memsel <= '1'; rwbar <= read_request (i); ready <= '0'; IF wait_states (i) /= 0 THEN wait: FOR j IN 1 TO wait_states (i) LOOP EXIT WHEN skip_wait = '1'; WAIT FOR clock_period; END LOOP wait; END IF; ready <= '1'; EXIT; ELSE grant (i) <= '0'; memsel <= '0'; END IF; END LOOP; END IF; WAIT ON clock; END PROCESS wait_cycle; END behavioral;
Arbiter VHDL description
CHAPTER 11
10
DMA DEVICE
Serial To Parallel
serial
pa ral lel _o ut ov err u fra n m_ err or
11
Interface of serial-to-parallel converter
CHAPTER 11
da tar ea rec dy eiv ed

DMA DEVICE
8
de v_ da ta
er err de de ro or v_ v_ r2 1 rd rc y v
read_mem write_mem databus grant
DMA Controller
addressbus ready status_write

clk sel ect _re g
status_read
Interface of the DMA controller
CHAPTER 11
12
DMA DEVICE
Address
1111:1111_1100 1111:1111_1101 1111:1111_1110 1111:1111_1111
DMA Registers Least 8 bits of starting address Most 4 bits of start Number of bytes to transfer done ie er2 er1 ie wr rd go
DMA Registers
CHAPTER 11
13
DMA DEVICE
adbus
Address Decoder
active
Decoding for selecting DMA registers
CHAPTER 11
14
DMA DEVICE
ENTITY quad_adrdcd IS GENERIC (addresses : twelve := "111111111100"); PORT (adbus : IN twelve; active : OUT qit; selects : OUT nibble); END quad_adrdcd; -ARCHITECTURE behavioral OF quad_adrdcd IS BEGIN PROCESS (adbus) BEGIN IF to_bitvector (addresses AND adbus) = to_bitvector (addresses) THEN active <= '1'; CASE adbus (1 DOWNTO 0) IS WHEN "00" => selects <= "0001"; WHEN "01" => selects <= "0010"; WHEN "10" => selects <= "0100"; WHEN "11" => selects <= "1000"; WHEN OTHERS => selects <= "0000"; END CASE; ELSE active <= '0'; selects <= "0000"; END IF; END PROCESS; END behavioral;
VHDL description of DMA register address decoder
CHAPTER 11
15
DMA DEVICE
S2P
serial
8
de er err dev dev v_ ro r2 or1 _rdy _rcv da ta
read_mem 8 write_mem databus grant ready 12 addressbus status_read status_write

sel ect _re g
adbus
status_sel active
DMA device
pa ral lel _o ut ov err u fra n m_ e da rror tar rec ead eiv y ed
DMA
selects
Decoder
DMA DEVICE
ENTITY dma_controller IS PORT (clk : IN qit; -- memory signals read_mem, write_mem : OUT qit := '0'; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve := "ZZZZZZZZZZZZ"; ready, grant : IN qit; -- cpu signals select_reg : IN nibble; status_rd, status_wr : IN qit; --device signals error1, error2, dev_rdy : IN qit; dev_rcv : OUT qit; dev_data : IN byte ); END dma_controller;
DMA controller entity declaration
CHAPTER 11
17
DMA DEVICE
ARCHITECTURE behavioral of dma_controller IS Declarations (Figure 11.17) BEGIN get serial, put parallel process statement (Figure 11.18) -direct CPU communications blocks (Figure 11.19) END behavioral;
Outline of DMA controller architecture.
SIGNAL done : qit := '0'; TYPE r4 IS ARRAY (0 TO 3) OF byte; SIGNAL rfile : r4 REGISTER := (OTHERS => zero_8); ALIAS go : qit IS rfile(3)(0); ALIAS rd : qit IS rfile(3)(1); ALIAS wr : qit IS rfile(3)(2); ALIAS ie : qit IS rfile(3)(3);
DMA controller declarations.
CHAPTER 11
18
DMA DEVICE
get_put : PROCESS VARIABLE buff : byte := zero_8; VARIABLE pntr : twelve; VARIABLE numb : byte; BEGIN WAIT UNTIL go = '1'; done <= '0'; numb := rfile(2); pntr := rfile(1)(3 DOWNTO 0) & rfile(0); IF wr = '1' THEN writing : WHILE TO_INTEGER(numb) > 0 LOOP numb := numb - 1; -- get data IF dev_rdy /= '1' THEN WAIT UNTIL dev_rdy = '1'; END IF; buff := dev_data; WAIT UNTIL clk = '1'; dev_rcv <= '1'; WAIT UNTIL clk = '0'; dev_rcv <= '0'; -- put to mem write_mem <= '1'; WAIT UNTIL grant = '1'; databus <= buff; adbus <= pntr; pntr := pntr + 1; WAIT UNTIL ready = '1'; databus <= "ZZZZZZZZ"; adbus <= "ZZZZZZZZZZZZ"; write_mem <= '0'; END LOOP writing; done <= '1'; END IF; END PROCESS get_put;
DMA controller get serial and put parallel process
CHAPTER 11
19
DMA DEVICE
cpu_direct : FOR i IN 0 TO 3 GENERATE databus <= rfile(i) WHEN select_reg(i) = '1' AND status_rd = '1' ELSE "ZZZZZZZZ"; r0to3 : BLOCK ((clk'EVENT AND clk = '0') AND select_reg(i) = '1' AND status_wr = '1') BEGIN rfile (i) <= GUARDED databus; END BLOCK; END GENERATE cpu_direct; r3 : BLOCK ((clk'EVENT AND clk = '0') AND done = '1') BEGIN rfile (3)(7 DOWNTO 4) <= GUARDED ('1', ie, error2, error1); END BLOCK;
DMA controller direct CPU communications blocks
CHAPTER 11
20
DMA DEVICE
ENTITY dma_serial_device IS PORT (clk : IN qit; -- memory signals read_mem, write_mem : OUT qit := '0'; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve; ready, grant : IN qit; status_rd, status_wr : IN qit; status_sel : OUT qit; serial_in : IN qit); END dma_serial_device; -ARCHITECTURE structural OF dma_serial_device IS COMPONENT dma IS PORT (clk : IN qit; read_mem, write_mem : OUT qit; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve; ready, grant : IN qit; select_reg : IN nibble; status_rd, status_wr : IN qit; error1, error2, dev_rdy : IN qit; dev_rcv : OUT qit; dev_data : IN byte ); END COMPONENT dma; COMPONENT dcd IS GENERIC (addresses : twelve := "1111111111XX"); PORT (adbus : IN twelve; active : OUT qit; selects : OUT nibble); END COMPONENT dcd; COMPONENT s2p IS GENERIC (bps : INTEGER := 9600); PORT (serial, received : IN qit; dataready : BUFFER qit; overrun, frame_error : OUT qit; parallel_out : BUFFER qit_vector (7 DOWNTO 0)); END COMPONENT s2p; SIGNAL s2p_rdy, s2p_rcv, s2p_er1, s2p_er2 : qit; SIGNAL s2p_par : byte; SIGNAL cpu_mem_data : byte; SIGNAL cpu_mem_addr : twelve; SIGNAL select_reg : nibble; BEGIN c1 : dma PORT MAP (clk, read_mem, write_mem, databus, adbus, ready, grant, select_reg, status_rd, status_wr, s2p_er1, s2p_er2, s2p_rdy, s2p_rcv, s2p_par); c2 : dcd PORT MAP (adbus, status_sel, select_reg); c3 : s2p PORT MAP (serial_in, s2p_rcv, s2p_rdy, s2p_er1, s2p_er2, s2p_par); END structural;
DMA serial device, description for diagram of Figure 11.14
CHAPTER 11
21
CPU CACHE
adbus valid set tag 5 To 32
tag
line Way 0 Way 1
DCD
LSB
MSB
8 8 v=1 & v=1 Match & Match 0 8
Hit
Cache Block Diagram
CHAPTER 11
22
CPU CACHE
adbus
5 7 MSB LSB
5 To 32
1: If a recent data was found in Way 0; 0: If a recent data was found in Way 1.
DCD
lru
The lru table
CHAPTER 11
23
CPU CACHE
me me m_ m_ ad dat bu abu s s
rea gra wr read dy nt_ ite_ _m _m m m e em em em m
cache
da tab us ad bu s rea dy gra nt wr ite rea d
24
clk
Cache Interface
CHAPTER 11
CPU CACHE
ENTITY cache_system IS PORT (clk : IN qit; -- memory signals read_mem, write_mem : OUT qit; grant_mem, ready_mem : IN qit; mem_databus : INOUT byte := "ZZZZZZZZ"; mem_adbus : INOUT twelve := "ZZZZZZZZZZZZ"; -- cpu signals read, write : IN qit; grant, ready : OUT qit; databus : INOUT byte := "ZZZZZZZZ"; adbus : INOUT twelve := "ZZZZZZZZZZZZ" ); END cache_system;
Cache Entity Declaration
CHAPTER 11
25
CPU CACHE
ARCHITECTURE control_and_memory of cache_system IS structure declarations BEGIN PROCESS local declarations BEGIN wait for request look for data in the cache For read, write If hit: For read, pass data to CPU For write, write data in cache and memory If miss: Find least recently used For write, write data in cache and memory For read, read from memory and pass on to CPU Wait until (read OR write)=1; END PROCESS; END control_and_memory;
Outline of cache VHDL description
CHAPTER 11
26
CPU CACHE
SUBTYPE ways IS INTEGER RANGE 0 TO 1; SUBTYPE sets IS INTEGER RANGE 0 TO 31; TYPE line IS ARRAY (0 TO 0) OF byte; SUBTYPE tags IS qit_vector (6 DOWNTO 0); TYPE lru_type IS ARRAY (sets) OF ways; TYPE entry IS RECORD valid : BOOLEAN; tag : tags; data : line; END RECORD; TYPE each_cache IS ARRAY (sets) OF entry; TYPE cache_type IS ARRAY (ways) OF each_cache; SIGNAL cache : cache_type; SIGNAL lru : lru_type;
Cache structure declarations
VARIABLE s : sets; VARIABLE hit : BOOLEAN; VARIABLE w, free : ways; TYPE ww IS ARRAY(ways) OF ways; CONSTANT nw : ww := (1, 0); ALIAS set_value : qit_vector (4 DOWNTO 0) IS adbus (4 DOWNTO 0); ALIAS tag_value : tags IS adbus (11 DOWNTO 5);
Controller local declarations
CHAPTER 11
27
CPU CACHE
grant <= '1'; ready <= '0'; WAIT UNTIL clk = '0'; s := TO_INTEGER (set_value); hit := FALSE; FOR i IN ways LOOP IF cache(i)(s).tag = tag_value AND cache(i)(s).valid THEN hit := TRUE; w := i; END IF; END LOOP;
Controller search in cache

IF hit THEN lru (s) <= nw (w); IF read = '1' THEN ready <= '1'; databus <= cache(w)(s).data(0); WAIT UNTIL read = '0'; databus <= "ZZZZZZZZ"; ELSIF write = '1' THEN cache(w)(s).data(0) <= databus; cache(w)(s).valid <= TRUE; write_mem <= '1'; WAIT UNTIL grant_mem = '1'; mem_databus <= databus; mem_adbus <= adbus; WAIT UNTIL ready_mem = '1'; mem_databus <= "ZZZZZZZZ"; mem_adbus <= "ZZZZZZZZZZZZ"; write_mem <= '0'; ready <= '1'; WAIT UNTIL write = '0'; END IF; ready <= '0';
Controller code for cache hit
CHAPTER 11
28
CPU CACHE
ELSE -- miss free := lru (s); lru (s) <= nw (lru (s)); IF write = '1' THEN cache(free)(s).tag <= tag_value; cache(free)(s).data(0) <= databus; cache(free)(s).valid <= TRUE; write_mem <= '1'; WAIT UNTIL grant_mem = '1'; mem_databus <= databus; mem_adbus <= adbus; WAIT UNTIL ready_mem = '1'; mem_databus <= "ZZZZZZZZ"; mem_adbus <= "ZZZZZZZZZZZZ"; write_mem <= '0'; ready <= '1'; WAIT UNTIL write = '0'; ready <= '0'; ELSIF read = '1' THEN read_mem <= '1'; WAIT UNTIL grant_mem = '1'; mem_adbus <= adbus; WAIT UNTIL ready_mem = '1'; cache(free)(s).tag <= tag_value; cache(free)(s).data(0) <= mem_databus; cache(free)(s).valid <= TRUE; databus <= mem_databus; mem_adbus <= "ZZZZZZZZZZZZ"; read_mem <= '0'; ready <= '1'; WAIT UNTIL read = '0'; ready <= '0'; END IF; END IF;
Controller code for cache miss
CHAPTER 11
29
CPU CACHE
Arbiter s2p Mem
DMA
Cache
Decoder
Parwan CPU
Board level interface
CHAPTER 11
30
CPU CACHE
ENTITY parwan_tester IS END parwan_tester; -ARCHITECTURE system OF parwan_tester IS BEGIN int : interrupt <= '1', '0' AFTER 4500 NS; clk : clock <= NOT clock AFTER duty WHEN halted = '0' ELSE clock; arb : arbitr GENERIC MAP ((OTHERS => 2), period) PORT MAP (rd_req, wr_req, grant_mem, clock, skip_wait, cs, rwbar, ready); dev : serial PORT MAP (clock, rd_req(0), wr_req(0), data, address, ready, grant_mem(0), cpu_read, cpu_write, skip_wait, serial_in); csh : cache PORT MAP (clock, rd_req(1), wr_req(1), grant_mem(1), ready, data, address, cpu_read, cpu_write, csh_grant, csh_ready, cpu_data, cpu_address); cpu : parwan PORT MAP (clock, interrupt, cpu_read, cpu_write, cpu_data, cpu_address, halted, csh_ready, csh_grant); mem : memory PORT MAP (cs, rwbar, data, address); srg : sergen PORT MAP (serial_in); END system;
Interface board VHDL description
CHAPTER 11
31
SUMMARY
In this chapter we presented a board level design in VHDL. We illustrated the use of VHDL in a component level design environment. Language constructs for behavioral
descriptions and timing and control were emphasized. Several components with differing handshaking
schemes were independently described. The interface of the memory component is non-responsive, while other
components such as the CPU and cache controller have two or three line fully-responsive or partially-responsive
handshaking schemes.
We have illustrated how such
handshaking schemes can be described in VHDL, and how VHDL constructs can be used for handing communication between various devices. As opposed to Chapter 10 in which hardware details of a design were of concern, this chapter presented design at a higher level of abstraction. VHDL constructs used in this chapter were primarily at the behavioral level as discussed in Chapter 9. The examples presented here, show various forms of using wait statements in describing a design.
End of Chapter 11
CHAPTER 11
32

VHDL Lecture Notes - Navabi

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VHDL Lecture Notes - Navabi

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Chapter 1

Hardware design environments

1999, Z. Navabi and McGraw-Hill Inc.

A digital system design process

1999, Z. Navabi and McGraw-Hill Inc.

Result of the data path design phase.

MAIN LOGIC UNIT

Dataflow description Control Data partitioning

1999, Z. Navabi and McGraw-Hill Inc.

An ISPS example, a simple processor.

Behavioral Example Only describing functionality

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An AHPL example, a sequential multiplier.

1999, Z. Navabi and McGraw-Hill Inc.

Full-adder, logical diagram and Verilog code.

Hardware Description (Model)

Simulation Hardware Model

Simulation Engine Component Library (Models)

Simulation Results (Output)

Test Data (Stimuli)

1999, Z. Navabi and McGraw-Hill Inc.

Verifying each design stage.

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1999, Z. Navabi and McGraw-Hill Inc.

FUNCTION Input Input NOT NOT AND AND OR

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Event driven simulation.

OR 2 b Inp 0 NOT 0 AND 0 4 6

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Categories of synthesis tools.

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Synthesizable Model Synthesis Hardware Description Scheduling Synthesis Directives

Synthesized Hardware (Netlist)

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1999, Z. Navabi and McGraw-Hill Inc.

1999, Z. Navabi and McGraw-Hill Inc.

1981 DoD Woods Hole MA : Workshop on HDLs Part of VHSIC program

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1999, Z. Navabi and McGraw-Hill Inc.

AHPL CDL CONLAN IDL ISPS TEGAS TI-HDL ZEUS

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1999, Z. Navabi and McGraw-Hill Inc.

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Example for hierarchical partitioning.

Recursive partitioning Simple components as terminals

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An example VHDL environment.

VHDL Simulator Layout Synthesizer Netlist Synthesizer Other Tools

VHDL defines library usage Tools define library management

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Interface and architectural specifications.

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Multiple architectural specifications.

ENTITY component_i IS PORT (. . )

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PACKAGE package_name IS component declarations. sub-program declasrations. END package_name;

PACKAGE BODY package_name IS type definitions. sub-programs. END package_name;

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Recursive partition procedure.