Anda di halaman 1dari 18

Computer Organization

and Architecture

Lecture 2
Structure of modern computer -
Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
Structure of modern computer -
Top Level

CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
What is a program?
„ A sequence of steps
„ For each step, an arithmetic or
logical operation is done
„ For each operation, a different set of
control signals is needed
Computer Components:
Top Level View
Instruction Cycle
„ Two steps:
• Fetch
• Execute
Fetch Cycle
„ Program Counter (PC) holds address of
next instruction to fetch
„ Processor fetches instruction from
memory location pointed to by PC
„ Increment PC
• Unless told otherwise
„ Instruction loaded into Instruction
Register (IR)
„ Processor interprets instruction and
performs required actions
Execute Cycle
„ Processor-memory
• data transfer between CPU and main memory
„ Processor I/O
• Data transfer between CPU and I/O module
„ Data processing
• Some arithmetic or logical operation on data
„ Control
• Alteration of sequence of operations
• e.g. jump
„ Combination of above
Example of Program Execution
Interrupts

„ Mechanism by which other modules (e.g.


I/O) may interrupt normal sequence of
processing
Program Flow Control
Interrupt Cycle

„ Added to instruction cycle


„ Processor checks for interrupt
• Indicated by an interrupt signal
„ If no interrupt, fetch next instruction
„ If interrupt pending:
• Suspend execution of current program
• Save status
• Set PC to start address of interrupt handler routine
• Process interrupt
• Restore status and continue interrupted program
Transfer of Control via
Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Multiple Interrupts
„ Disable interrupts
• Processor will ignore further interrupts while
processing one interrupt
• Interrupts remain pending and are checked
after first interrupt has been processed
• Interrupts handled in sequence as they occur
„ Define priorities
• Low priority interrupts can be interrupted by
higher priority interrupts
• When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Time Sequence of Multiple
Interrupts